KR100282086B1 - Semiconductor wafer fabrication - Google Patents

Abstract

In the specification of the present application, a method for fabricating a semiconductor integrated circuit (IC) is described. In this method, a defect density due to conductive particle debris formed at the edge of a wafer is measured. By burying and reducing the edge of the metal layer when forming the metal layers, it prevents the edge of the metal layer from being exposed in subsequent manufacturing process steps.

Description

Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit wafer manufacturing method {SEMICONDUCTOR WAFER FABRICATION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor wafer, and more particularly, to improve the yield of semiconductor devices by reducing particle defects.

Device defects in typical semiconductor fabrication methods are caused by metal particulates that occur during the patterning of the metal layers and the interlevel dielectric layer between them. Particulates are produced from a variety of sources, but in particular the problem is that the edge of the metal layer at the edge of the wafer may be exposed during subsequent processing. This problem is exacerbated by a typical edge bead removal process in which the previous metal levels are exposed so that edge debris from those metal levels are removed during the manufacturing process. It may also be attached to. These metal edge debris short the integrated circuit (IC) under manufacture. Since such a short circuit is detected after the IC processing is completed, a large cost is wasted in dealing with such a bad device.

In view of this problem, it is an object of the present invention to provide a technique for preventing the formation of edge pieces by keeping the metal level edge covered during the entire process.

1-18 schematically illustrate a typical semiconductor wafer fabrication method using polysilicon and two levels of metal, showing the exposure of metal edges during the processing process and illustrating typical semiconductor wafer fabrication possibilities illustrating the formation of edge pieces. Schematic of the method,

19 is a schematic diagram of a semiconductor wafer showing edge dimensions used in the description;

20-34 are schematic diagrams illustrating steps of a wafer fabrication method for embedding a metal edge in accordance with one embodiment of the present invention;

35 to 40 are schematic diagrams similar to FIGS. 20 to 34 showing another embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

12: wafer edge 51: substrate

52, 55, 59, 64: dielectric layer 53, 57, 62: metal layer

54, 56, 58, 61, 63, 65: photomask

This object can be achieved by embedding the metal edge in the interlayer dielectric layer. This ″ edge buried ″ process protects each underlayer when forming a new level and prevents exposure of metal edges previously formed even during window etch. According to the present invention, this result can be obtained by etching the peripheral ring of each metal level at the edge of the wafer and attaching an interlayer dielectric so that the dielectric covers the edge of the underlying metal layer. In a preferred embodiment, the outer perimeter ring of each interlayer dielectric layer at the edge of the wafer is also removed, with the width of each interlayer dielectric ring removed being less than the width of the metal ring being removed so that each interlayer dielectric layer is a wafer edge rather than the metal layer. By extending closer to the edge, the edges of each metal layer are buried. The purpose of this embodiment is to eliminate the layer formed on the outer periphery of the wafer so that there is no attached material that will fall off and form debris during the handling and fixing of the wafer. This technique essentially replaces the edge bead removal process typically used in wafer processing.

Two options in the case of removing the outer ring of each metal layer will be described. One preferred option is to basically make the size of the outer ring of each metal layer the same, while the other option reduces the size of the outer ring of each metal layer which is provided sequentially, making each metal more certain during subsequent processing. The edge of the layer is well protected.

In the process to be described later, the wafer to be processed is a silicon wafer. However, other semiconductor wafers, for example, III-V or II-VI semiconductor wafers can be processed in a similar manner, and the principles of the present invention can be equally applied to such semiconductor materials. In silicon processing, which is the most typical semiconductor processing, the first layer is a layer on which oxide is grown. Subsequent layers are a gate oxide layer, one or more polysilicon layers and one or more metal layers such as aluminum layers. Process sequences are described in the order of a single poly, two metals, stepped portions for the understanding of the present invention. Clearly, the described features will apply to other processes using one, two, or even three metal layer levels in addition to dual poly and / or poly level (s). Interlevel dielectrics are typically those described above using SiO ₂ attached or other insulating materials such as Si ₃ N _4, and spin-on insulators such as various glass compositions and polyimides. The advantages of the present invention may also be obtained.

The field oxide layer is typically patterned by the well-known Local Oxidation Of Silicon (LOCOS) type of process. The first conductor level, typically polysilicon, is attached using chemical vapor deposition (CVD) or other suitable process and patterned using standard photolithography. A photoresist layer is spun onto the polysilicon layer to form edge beads at the edge of the wafer. Edge beads are formed due to fluid dynamics at the surface discontinuities, for example surface tension. The formation of edge beads is largely unavoidable. The results of edge beads are well known. After photoresist exposure, development, and stripping, residues of undesired photoresist may remain at the edge of the wafer, masking small edge regions, which may later cause fragmentation. As residue from the photoresist edge bead layer accumulates, particulate defects occur and disrupt normal processes.

Photoresist edge beads are generally unavoidable but can be removed by an edge bead removal process. The edge bead removal process is a standard process in the art, and there are generally two types. Masks for photoresist exposure may mask the edge bead regions (for positive resist) or expose (for negative resist) to be removed during development of the photoresist at the edge of the wafer. A typical development may not remove all edge beads during cleaning of exposed edge beads so that the edge beads are completely removed by subsequent photoresist stripping. Alternatively, edge beads are removed using chemical etch prior to photoresist exposure and development. In this process, the edge beads on the upper surface of the wafer under processing are exposed to the injection of photoresist stripping fluid. Typically, a baffle is placed at the edge of the wafer and the wafer is rotated in the flow of stripping liquid. Typically a few millimeters of photoresist at the edge of the wafer is removed.

As will be apparent from the following description with reference to FIGS. 1-18, removing the edge beads in a general manner reveals the edge stacks of all layers, exposing the edges of previously formed layers. If such an exposed layer is a metal layer, it is important that a piece of metal may form at the edge of the metal layer during subsequent processing, resulting in conductive particulate bonding in the final device. This problem arises from the usual process in the following manner.

1 shows a semiconductor substrate 21 and a layer 22 in processing, typically a SiO ₂ layer. Oxide layer 22 is a field oxide, which is patterned by growing the layer over a surface that is masked with a silicon nitride region. This part of the process proceeds in the region of the wafer removed from the edge and is not shown in the figure. In a typical process, the first conductor level 23, which is a polysilicon layer, is deposited by chemical vapor deposition (CVD) or by any suitable method to provide the structure shown in FIG. The polysilicon layer and subsequent layers in this process are patterned by standard photolithography. Some processes use a hard mask, or oxide mask, to pattern the polysilicon layer, but alternatives are well known in the art. Referring to FIG. 3, photoresist is shown with reference numeral 24 and edge beads are shown with reference numeral 25. Referring to FIG. The width S of the photoresist strip removed from the edge of the wafer during the edge bead removal process is shown in FIG. 4. This dimension S is a dimension from the edge 12 of the wafer to the edge of the photoresist 24, which is typically 1-10 mm.

5 shows a region of a polysilicon layer exposed and etched by a patterned photomask 24. The structure after photoresist stripping is shown in FIG. 6, in which there is no conductive material in region 26 of width S. In FIG.

In this process step the source drain window is open and the next step involves the formation of a gate dielectric. These steps are not related to the portion of the wafer shown in the figures, and these well known steps and others that are not important to the present invention are omitted to avoid complications.

A first interlevel dielectric layer 27 attached over the patterned polysilicon 23 is shown in FIG. 7. In patterning the interlayer dielectric layer 27, the patterned photoresist layer 28 is spaced apart from the edge 12 of the wafer by a distance of S after its edge bead portion is removed. The edge portion of the interlayer dielectric 27 is removed as shown in FIG. Typically etching methods, such as plasma etch, are standard and well known. After stripping of the photoresist, the deposition of the first metal level 29 over the first interlayer dielectric layer 27 and the exposed field oxide 22 is shown in FIG. 10. The metal level may be aluminum or other suitable conductor and may be attached by evaporation or other techniques. The photoresist layer 31 used to pattern the first metal level is spaced S apart from the edge 12 of the wafer as shown in FIG. 11. In FIG. 12, after patterning of the first metal level 29, the edges of each of the layers 23, 27, 29 are basically aligned by a distance of S from the edge 12 of the wafer. In FIG. 13, a second interlayer dielectric layer 32 is blanket deposited over the wafer, and then in FIG. 14, a photoresist layer having the same edge portion S as removed in the previous photoresist steps ( 33 is shown. After etching the exposed portion of the second interlayer dielectric layer 33, the structure shown in FIG. 15 appears. Finally, a blanketed second level metal layer 34 is shown in FIG. 16, and a patterned photomask spaced S distance from the edge 12 of the wafer is shown in FIG. 17. The structure after etching the exposed portion of the second metal level 34 is shown in FIG. 18. Since the edges 41, 42, 43 of each metal layer 23, 29, 34 are respectively exposed, it is apparent that there is a possibility that conductive particulate pieces are formed. It is also clear that the edges of those metal layers are exposed during the process up to this stage. Such exposure of metal level edges during the processing process results from an edge bead removal process that causes all layers to terminate at the same distance (here ″ S ″) from the edge of the wafer.

An improved method according to the present invention will be described with reference to FIGS. 19 to 34. 19 is a top view of a typical wafer 55 having chip sites 56. Dimensions S ₁ and S ₂ are the separation distance from wafer edge 12 to be used in the following description.

20 shows a substrate 51 having a field oxide 52 and a polysilicon layer 53. The mask for patterning the polysilicon layer 53 is shown at 54 and is separated by the distance of S ₁ from the edge 12 of the wafer. The wafer after etching the polysilicon level and removing the photomask 54 is shown in FIG. 21. A first interlayer dielectric layer 55 attached over the patterned polysilicon layer 53 is shown in FIG. 22. As shown in FIG. 23, the first interlayer dielectric layer is patterned into a photomask having an edge of the photomask positioned at a distance S ₂ from the edge 12 of the wafer, where S ₂ <S ₁ . . Typically S ₁ is on the order of 1-5 mm and S ₂ according to the invention is made to be substantially less than 75% of S ₁ .

The structure after patterning the first interlayer dielectric layer 55 is shown in FIG. 24, where the edges of the polysilicon layer 53 are embedded in the dielectric layers 52, 55.

A first level metal layer 57 blanketed over the first interlayer dielectric layer 55 is shown in FIG. 25. In FIG. 26, the first metal level 57 is patterned by a photomask 58 having an edge of the photomask that is separated by a distance of S ₁ from the edge 12 of the wafer. The distance S ₁ used to etch all the conductive layers is approximately the same in each case. The structure after etching the first metal level and removing the photoresist is shown in FIG. 27.

A second interlayer dielectric layer 59 attached over the patterned first metal level 57 is shown in FIG. 28. As shown in FIG. 29, the second interlayer dielectric layer is patterned into a photomask 61 spaced apart by the distance of S ₂ from the edge 12 of the wafer. The distance S ₂ is approximately equal for each interlayer dielectric layer. The structure after etching the interlayer dielectric layer 59 and removing the photoresist 61 is shown in FIG. The edges of all three metal layers are embedded by the dielectric layer as shown. As is evident from the series of steps just described, the edge of each conductive layer is buried when covered by the next dielectric layer and is not exposed during subsequent processing. This is because the distance S ₁ from the edge of the wafer to the edge of each metal layer is greater than the distance S ₂ to the dielectric layer. In terms of processing, the result is that the outer periphery of the photoresist removed from the mask layer used to pattern the metal layer is removed from the mask layer used to pattern the dielectric layers. Because it is larger than the area.

Also, it is clear that in this embodiment the edges of the conductor levels are aligned vertically as in the structure of FIG. 18, but these edges are buried differently from the structure of FIG. 18.

The second level metal layer 62 is blanket attached over the second interlayer dielectric layer 59 as shown in FIG. 31. The second level metal layer is patterned by a photomask 63 located at a distance of S ₁ from the wafer edge 12 as shown in FIG. The structure after etching the second metal level and removing the photoresist is shown in FIG. 33. The final dielectric layer 64 is attached over the second metal layer as shown in FIG. As is apparent from the series of steps just described and FIG. 34, each edge of each conductor level 53, 57, 62 remains embedded by dielectric layers 52, 55, 59, 64 during the wafer processing process. This eliminates the possibility of forming conductive particulate pieces at the edge of the conductive layer during the treatment process.

In the embodiment of the present invention just described, each interlayer dielectric layer is located a distance of S ₂ from the wafer edge 12, assuming that S ₂ is finite. In addition, when S ₂ is zero, it is also possible to maintain the purpose of the present invention, i.e., the edge of the conductivity level, buried.

A preferred technique for obtaining the distance between S ₁ and S ₂ is photolithographic patterning. However, as described above, the photoresist can be removed by dissolving with a solvent prior to exposure by spraying a solvent directly on the edge of the wafer. The apparatus used for this purpose can be adjusted to enable the removal of photoresists of several different dimensions and can be used according to the principles of the invention such that S ₁ and S ₂ of the different dimensions specified above are obtained.

As is apparent from FIG. 34, as the edges of the metal layers 53, 57, 62 are aligned, large steps are formed in the topography of the wafer. Such steps can be reduced in the embodiment shown in FIGS. 35-40. The large step in FIG. 34 results from the common distance S ₁ from the wafer edge to the photoresist used to pattern the conductive layer. By staggering this distance, the steps can be reduced and the edges of each conductive layer side protected during subsequent etching of the layers.

Referring to FIG. 35, polysilicon layer 53 over field oxide 52 is patterned with photoresist layer 54. Outer peripheral region is removed from the photoresist layer is defined as _a S, where S _a is 3 mm, for example. After etching the polysilicon layer 53, stripping the photoresist layer 54, attaching the first interlayer dielectric layer 55, and masking the first interlayer dielectric layer with a photomask 56, the dielectric layer The edge of the photomask for patterning 55 is spaced apart by the distance of S ₂ from the edge 12 of the wafer as shown in FIG.

In FIG. 37, a second level metal layer 57 is blanket attached over the first interlayer dielectric layer 55. The photoresist layer used to pattern the second level metal layer 57 is shown as reference numeral 58 in FIG. 37. The edge of this photoresist layer is located at a distance of S _b from the edge 12 of the wafer, where S _b <S _a . For example, as previously suggested, if S _a is 3 mm, then S _b may be about 2.5 mm. 38 shows a patterned first level metal layer 57 and a second interlayer dielectric layer 59 blanketed over the first metal level. The second interlayer dielectric layer is patterned by the photoresist layer 61. The edge of the photoresist layer is located a distance of S ₂ from the wafer edge 12. Referring to FIG. 39, the last metal layer 62, which is the second level metal, is attached over the dielectric layer 59, and the photoresist layer used to pattern the metal layer 62 is denoted by reference numeral 63. Shown. The edge of this photoresist layer is located at a distance of S _c from the edge of the wafer, where S _c &lt; S _b . If the dimensions for S _a and S _b are as given previously, the most suitable dimension for S _c is 2.0 mm. The most suitable dimension of S ₂ is 1.5 mm. In an embodiment of the present invention, the dimensions S _a , S _b , S _c, and S ₂ have a relationship S _a > S _b > S _c > S ₂ . The final structure is shown in FIG. The structure of FIG. 40 differs from that of FIG. 34, wherein the edges of the metal layers 53, 57, 62 are staggered along the wafer surface to form a gradual step in topography, and also the conductor level edge in the lateral direction. Landfill them.

In the above description, the polysilicon layer is referred to as a metal layer because it is conductive, and fragments at the polysilicon layer edge may potentially cause conductive particulate defects. However, as mentioned above, various metalized materials may be used. In the silicon processing process the metal level is typically aluminum. However, other metals and alloys such as TiPtAu are used in the III-V and II-VI treatment processes. A common property of these conductive materials that cause potential defects in finished devices is that they are electrically conductive.

The dielectric layers are typically oxides but may be of other materials as previously presented. The thickness of these layers is common. In practice, all of the processes described herein follow existing established manufacturing processes and only allow the edge portion of the photolithographic mask to be slightly adjusted. Thus, no photolithography or etching step is added, so there is basically no added cost.

As is apparent from the foregoing description, an aspect of the present invention relates to the relative size of the edge portion of the photoresist layer removed during the processing process. The definition of important sizes will be clearly understood with reference to the drawings. For clarity of this dimension, the size of the peripheral area of the photoresist layer removed during the processing process is measured from the edge of the wafer to the edge of the photomask along the diameter direction of the wafer.

Those skilled in the art will appreciate that various additional modifications of the invention are possible. Basically, all the modifications in accordance with the specific disclosure in the specification that depend on the principles of the invention and the equivalent modifications that advance the art fall within the scope of the invention as described and claimed.

As described above, according to the present invention, since the edge of the metal layer is not exposed during the entire process, the metal edge fragments are not generated, thereby improving the yield of the semiconductor device.

Claims (14)

A method for manufacturing a semiconductor integrated circuit (IC) on a semiconductor wafer, the method comprising a plurality of photolithography process, the photolithography process, (a) coating the semiconductor wafer with photoresist to form a photoresist layer, (b) forming a photolithographic pattern in the photoresist layer, the photolithographic pattern comprising a peripheral region at the edge of the wafer from which the photoresist layer is removed; , Repeating steps (a) and (b) In the semiconductor integrated circuit manufacturing method comprising: The outer periphery region of the photoresist layer formed in step (b) has a distance dimension of S ₁ from the edge of the wafer towards the center of the wafer and is removed at least once in step (b). A peripheral region of the layer has a distance dimension of S ₂ from the edge of the wafer toward the center of the wafer, wherein S ₂ &lt; S ₁ . The method of claim 1, S ₂ is less than 75% of S ₁ . In the semiconductor integrated circuit wafer manufacturing method, a. Forming a first dielectric layer over the semiconductor substrate; b. Attaching a first conductive layer over the first dielectric layer; c. Photolithographically masking the first conductive layer using a photomask; d. Etching the portion of the first conductive layer exposed by the photomask to pattern the first conductive layer, wherein the portion includes an outer periphery region of the first conductive layer near the periphery of the wafer; A peripheral edge of the first conductive layer spaced from the edge of the wafer, wherein the peripheral region is dimension S from the edge of the wafer to the peripheral edge of the first conductive layer along the radial direction of the wafer _{Having 1} , e. Attaching a second dielectric layer over the patterned first conductive layer; f. Photolithographically masking the second conductive layer using a photomask; g. Etching a portion of the second dielectric layer exposed by the photomask to pattern the second dielectric layer, the portion including an outer periphery region of the second dielectric layer near the periphery of the wafer, The outer periphery region has a dimension S ₂ that is smaller than the dimension S ₁ along the radial direction of the wafer from the edge of the wafer such that a portion of the second dielectric layer remaining after etching is at the outer edge of the first conductive layer. Steps covered Semiconductor integrated circuit wafer manufacturing method comprising a. The method of claim 3, wherein And the outer periphery region of the first conductive layer and the outer periphery region of the second dielectric layer extend near the entire outer periphery of the wafer. The method of claim 4, wherein Wherein said dimensions S ₁ and S ₂ are 1-10 mm. The method of claim 5, S ₂ is less than 75% of S ₁ . The method of claim 3, wherein Wherein the semiconductor wafer is silicon and the first and second dielectric layers comprise SiO ₂ . The method of claim 7, wherein And the first conductive layer is polysilicon. The method of claim 3, wherein h. Attaching a second conductive layer over the patterned second dielectric layer; i. Photolithographically masking the second conductive layer using a photomask; j. Etching the portion of the second conductive layer exposed by the photomask to pattern the second conductive layer, wherein the portion includes an outer periphery region of the second conductive layer near the periphery of the wafer; Forming an outer edge of the first conductive layer spaced from an edge of the wafer, the outer peripheral area having the dimension S ₁ ; k. Attaching a third dielectric layer over the patterned second conductive layer; l. Photolithographically masking the third dielectric layer using a photomask; m. Etching a portion of the third dielectric layer exposed by the photomask to pattern the third dielectric layer, the portion including an outer periphery region of the third dielectric layer near the periphery of the wafer, Said outer periphery region having said dimension S _{2 such} that a portion of said third dielectric layer remaining after etching covers an outer peripheral edge of said second conductive layer A semiconductor integrated circuit wafer manufacturing method further comprising. In the semiconductor integrated circuit wafer manufacturing method, a. Forming a first dielectric layer over the semiconductor substrate; b. Attaching a first conductive layer over the first dielectric layer; c. Photolithographically masking the first conductive layer using a photomask; d. Etching the portion of the first conductive layer exposed by the photomask to pattern the first conductive layer, wherein the portion includes an outer periphery region of the first conductive layer near the outer periphery of the wafer; A peripheral edge of the first conductive layer spaced from the edge of the wafer, wherein the peripheral region is dimension S from the edge of the wafer to the peripheral edge of the first conductive layer along the radial direction of the wafer _{Having 1} , e. Attaching a second dielectric layer over the patterned first conductive layer; f. Photolithographically masking the second dielectric layer using a photomask; g. Etching the portion of the second dielectric layer exposed by the photomask to pattern the second dielectric layer, the portion including an outer periphery region of the second dielectric layer near the periphery of the wafer; Wherein the outer periphery region has a dimension S ₂ that is smaller than the dimension S ₁ along the radial direction of the wafer from the edge of the wafer such that a portion of the second dielectric layer remaining after etching is the outer periphery of the first conductive layer. The edges covered, h. Attaching a second conductive layer over the patterned second dielectric layer; i. Photolithographically masking the second conductive layer using a photomask; j. Etching the portion of the second conductive layer exposed by the photomask to pattern the second conductive layer, wherein the portion includes an outer periphery region of the second conductive layer near the periphery of the wafer; Forming an outer edge of the first conductive layer spaced from an edge of the wafer, the outer peripheral area having the dimension S ₁ ; k. Attaching a third dielectric layer over the patterned second conductive layer; l. Photolithographically masking the third dielectric layer using a photomask; m. Etching a portion of the third dielectric layer exposed by the photomask to pattern the third dielectric layer, the portion including an outer periphery region of the third dielectric layer near the periphery of the wafer, Said outer peripheral region having said dimension S _{2 such} that a portion of said third dielectric layer remaining after etching covers an outer peripheral edge of said second conductive layer; n. Attaching a third conductive layer over the patterned third dielectric layer; o. Photolithographically masking the third conductive layer using a photomask; p. Etching a portion of the third conductive layer exposed by the photomask to pattern the third conductive layer, wherein the portion includes an outer periphery region of the third conductive layer near the periphery of the wafer; Forming an outer edge of the first conductive layer spaced from an edge of the wafer, the outer peripheral area having the dimension S ₁ ; q. Attaching a fourth dielectric layer over the patterned second conductive layer, wherein the fourth dielectric layer extends over the outer edge of the third conductive layer Semiconductor integrated circuit wafer manufacturing method comprising a. In the semiconductor integrated circuit wafer manufacturing method, a. Forming a first dielectric layer over the semiconductor substrate; b. Attaching a first conductive layer over the first dielectric layer; c. Photolithographically masking the first conductive layer using a photomask; d. Etching the portion of the first conductive layer exposed by the photomask to pattern the first conductive layer, wherein the portion includes an outer periphery region of the first conductive layer near the periphery of the wafer; A peripheral edge of the first conductive layer spaced from the edge of the wafer, wherein the peripheral region is dimension S from the edge of the wafer to the peripheral edge of the first conductive layer along the radial direction of the wafer having _a , e. Attaching a second dielectric layer over the patterned first conductive layer; f. Photolithographically masking the second dielectric layer using a photomask; g. Etching a portion of the second dielectric layer exposed to the photomask to pattern the second dielectric layer, the portion including an outer periphery region of the second dielectric layer near the periphery of the wafer, The outer periphery region has a dimension S ₂ along the radial direction of the wafer from an edge of the wafer, h. Attaching a second conductive layer over the patterned second dielectric layer; i. Photolithographically masking the second conductive layer using a photomask; j. Etching the portion of the second conductive layer exposed by the photomask to pattern the second conductive layer, wherein the portion includes an outer periphery region of the second conductive layer near the periphery of the wafer; Forming an outer edge of the first conductive layer spaced from the edge of the wafer, the outer peripheral area having a dimension S _b from the edge of the wafer to the outer edge of the second conductive layer along the radial direction of the wafer; Having a step, k. Attaching a third dielectric layer over the patterned second conductive layer; l. Photolithographically masking the third dielectric layer using a photomask; m. Etching a portion of the third dielectric layer exposed by the photomask to pattern the third dielectric layer, the portion including an outer periphery region of the third dielectric layer near the periphery of the wafer, Said outer peripheral region having said dimension S _{2 such} that a portion of said third dielectric layer remaining after etching covers an outer peripheral edge of said second conductive layer; n. Attaching a third conductive layer over the patterned third dielectric layer; o. Photolithographically masking the third conductive layer using a photomask; p. Etching a portion of the third conductive layer exposed by the photomask to pattern the third conductive layer, wherein the portion includes an outer periphery region of the third conductive layer near the periphery of the wafer; Forming an outer edge of the first conductive layer spaced from an edge of the wafer, the outer peripheral area having the dimension S ₁ ; q. Attaching a fourth dielectric layer over the patterned second conductive layer, the fourth dielectric layer extending over the outer edge of the third conductive layer and having the dimensions S _a , S _b , S _c and S ₂ Has a relationship of S _a > S _b > S _c > S ₂ so that the third conductive layer and the fourth dielectric layer cover the outer edges of the second conductive layer, and the second conductive layer and the third A dielectric layer covering an outer peripheral edge of the first conductive layer Semiconductor integrated circuit wafer manufacturing method comprising a. The method of claim 10, Wherein said dimension S ₂ is zero. The method of claim 11, Wherein said dimension S ₂ is zero. The method of claim 3, wherein And wherein the outer periphery region is formed by removing a portion of the mask prior to exposing the photolithographic mask.