CN115831865A - Structure and method for reducing arc discharge in wafer marking area - Google Patents
Structure and method for reducing arc discharge in wafer marking area Download PDFInfo
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- CN115831865A CN115831865A CN202310160100.XA CN202310160100A CN115831865A CN 115831865 A CN115831865 A CN 115831865A CN 202310160100 A CN202310160100 A CN 202310160100A CN 115831865 A CN115831865 A CN 115831865A
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Abstract
The invention provides a structure and a method for reducing arc discharge in a wafer marking area, wherein the method comprises the following steps: providing a substrate, and forming a lower metal interconnection layer on the substrate, wherein the lower metal interconnection layer comprises a metal connecting layer and a dielectric layer; forming an exposed metal connecting layer contact through hole in the dielectric layer; filling metal in the contact through hole to form a conductive plug electrically connected with the metal connecting layer; and forming and patterning a top metal layer on the dielectric layer, wherein the part of the top metal layer used as the wafer mark is electrically connected with the lower metal interconnection layer through a conductive plug. According to the invention, the conductive plug is arranged below the wafer marking top metal layer, and the wafer marking top metal layer, the lower metal interconnection layer and the substrate are interconnected through the conductive plug, so that the uniform distribution of charges on the metal connection layer and the substrate is realized, the electric arc discharge caused by the partial accumulation of the charges collected by the wafer marking top metal layer is avoided, the probability of the electric arc discharge is reduced, and the yield is improved; moreover, the etching parameters of the passivation layer are not required to be reduced, and the productivity is improved.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and relates to a structure and a method for reducing arc discharge in a wafer marking area.
Background
In the manufacturing process of a semiconductor integrated circuit, a Passivation layer (Passivation) is used as a protection structure of an integrated circuit device and a metal connecting line, so that on one hand, certain stress buffering is provided, the device is not damaged by subsequent processes such as cutting, cleaning, packaging and the like, and on the other hand, a product is protected from moisture and contamination, and an internal structure is protected from being corroded.
The passivation layer is formed by depositing one or more layers of SiO 2 Finally depositing a layer of dense Si 3 N 4 . The back-end Passivation layer etching process is mainly used for opening a Passivation layer to form a PAD (PAD), and a plasma etching Passivation layer is usually adopted, which becomes a process procedure with the highest frequency of Wafer arcing due to its specific higher radio frequency Power (RF Power), which is also one of the main common problems faced by the current integrated circuit Passivation layer etching (PAS-ET) process, and the arcing region is usually a Wafer Mark (Wafer Mark), a Scribe Line (Scribe Line), a closed Ring (Seal Ring), and the like.
Mechanism of arcing in the marked area of the wafer: before the finished wafer is shipped out, laser Mark (Laser Mark) is usually performed according to the requirement, and in order to avoid the influence of the lower layer Pattern (Pattern) on the Laser Mark of the wafer, the photoresist on the top metal of the wafer Mark area is not exposed, so that the metal of a larger area is reserved for the Laser Mark of the wafer and is not etched. However, since High Density Plasma (HDP) is usually used to ensure that the open portion of the top metal is sufficiently filled when depositing the oxide layer on the top metal, this causes the large area metal in the wafer mark area to act as an "antenna" to collect a large amount of charge. Moreover, the Wafer mark is usually located in the edge area of the Wafer, the passivation layer and the photoresist are easily incompletely covered and have a defect (Weak Point), when a High radio frequency Power (High RF Power) passivation layer etching process is performed at the rear end, charges in the High-concentration plasma locally and intensively accumulate a large amount of charges on the top layer metal at the Wafer mark through the Weak Point area, when the charge accumulation degree exceeds the bearing range, wafer discharge (Wafer Arcing) occurs, and once the Wafer discharge occurs, the Wafer yield is low, the cavity is polluted, and the like, so that loss is caused. The problem of wafer discharge is generally improved by reducing the etching parameters of the passivation layer, such as RF Power, but the reduction of the etching process parameters greatly reduces the production efficiency and increases the cost.
Therefore, a need exists in the art for a structure and a method for reducing arcing in a wafer mark area to reduce the risk of arcing in the wafer mark area, improve yield, improve efficiency, and reduce cost.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a structure and a method for reducing arc discharge in a wafer mark region, so as to solve the problems in the prior art that arc discharge is easily generated in a passivation layer etching step in the wafer mark region, a wafer rejection rate is high, and a production cost is high.
To achieve the above and other related objects, the present invention provides a method for reducing arcing in a marking area of a wafer, comprising the steps of:
providing a substrate, and forming a lower metal interconnection layer on the substrate, wherein the lower metal interconnection layer comprises a metal connection layer and a dielectric layer covering the metal connection layer, and the metal connection layer is electrically connected with the substrate;
forming a first contact through hole and a second contact through hole in the dielectric layer, wherein the first contact through hole and the second contact through hole expose the upper surface of the metal connecting layer;
filling metal in the first contact through hole and the second contact through hole to form a first conductive plug and a second conductive plug which are electrically connected with the metal connecting layer;
and forming a top metal layer on the dielectric layer and patterning the top metal layer to obtain an electrode lead-out layer and a wafer marking layer, wherein the electrode lead-out layer is electrically connected with the lower metal interconnection layer through the first conductive plug, and the wafer marking layer is electrically connected with the lower metal interconnection layer through the second conductive plug.
Optionally, the method further comprises the following steps:
forming a passivation layer on the patterned top metal layer, wherein the passivation layer covers the top metal layer and is filled into the gap of the top metal layer;
forming a first opening in the passivation layer above the electrode extraction layer, the first opening exposing an upper surface of the electrode extraction layer;
and forming a second opening in the passivation layer above the wafer marking layer, wherein the second opening exposes the upper surface of the wafer marking layer.
Optionally, a method of forming the passivation layer includes a high density plasma chemical vapor deposition method, a method of forming the first opening includes a plasma etching method, and a method of forming the second opening includes a laser etching method.
Optionally, the metal connection layer includes a plurality of conductive layers arranged at intervals in a vertical direction, and two adjacent conductive layers are electrically connected through a conductive plug.
Optionally, the metal connection layer and the top metal layer are made of aluminum, and the conductive plug is made of tungsten.
The invention also provides a structure for reducing arc discharge in a wafer marking area, which comprises the following components:
a substrate;
the lower metal interconnection layer is positioned above the substrate and comprises a metal connecting layer and a dielectric layer covering the metal connecting layer, and the metal connecting layer is electrically connected with the substrate;
the first conductive plug is positioned in the dielectric layer and is electrically connected with the metal connecting layer;
the second conductive plug is positioned in the dielectric layer and electrically connected with the metal connecting layer, wherein the second conductive plug and the first conductive plug are separated by a preset distance;
the top metal layer is positioned above the dielectric layer and comprises an electrode leading-out layer and a wafer marking layer, the electrode leading-out layer is electrically connected with the lower metal interconnection layer through the first conductive plug, and the wafer marking layer is electrically connected with the lower metal interconnection layer through the second conductive plug.
Optionally, the method further comprises:
the passivation layer is positioned above the top metal layer and covers the top metal layer, and is filled into a gap between the top metal layers;
a first opening in the passivation layer above the electrode extraction layer, the first opening exposing the electrode extraction layer;
and the second opening is positioned in the passivation layer above the wafer marking layer, and the second opening exposes the wafer marking layer.
Optionally, the metal connection layer includes a plurality of conductive layers spaced apart in a vertical direction, and two adjacent conductive layers are electrically connected by a conductive plug.
As described above, in the structure and method for reducing arc discharge in the wafer marking area, the second conductive plug is arranged below the wafer marking layer, and the wafer marking layer, the lower metal interconnection layer and the substrate are interconnected through the second conductive plug, so that uniform distribution of charges on the metal connection layer and the substrate is realized, partial accumulation of charges collected by the wafer marking layer is prevented from generating arc discharge, the probability of generating arc discharge is reduced, the yield is improved, and the cost is reduced; moreover, the etching parameters of the passivation layer are not required to be reduced, and the productivity is greatly improved.
Drawings
FIG. 1 is a schematic diagram showing the arcing of the top metal layer in the wafer mark area.
FIG. 2 is a process flow diagram illustrating a method of reducing arcing in a mark area of a wafer according to the present invention.
FIG. 3 is a schematic diagram illustrating a method of reducing arcing in a mark area of a wafer according to the present invention, in which a substrate is provided and an underlying metal interconnect layer is formed on the substrate.
FIG. 4 is a schematic diagram illustrating the formation of a first contact via and a second contact via in a dielectric layer in the method for reducing arcing in a mark region of a wafer according to the present invention.
FIG. 5 is a schematic diagram of a method for reducing arcing in a mark area of a wafer according to the present invention, in which a first conductive plug is formed in a first contact via and a second conductive plug is formed in a second contact via.
FIG. 6 is a schematic diagram illustrating the formation of a top metal layer on a dielectric layer in the method for reducing arcing in the scribe line region of a wafer according to the present invention.
FIG. 7 is a schematic diagram of a top metal layer patterned in the method for reducing arcing in the wafer mark area according to the present invention.
FIG. 8 is a schematic diagram illustrating the formation of a passivation layer on the top metal layer in the method for reducing arcing in the mark area of the wafer according to the present invention.
FIG. 9 is a schematic diagram illustrating the formation of a first opening and a second opening in a passivation layer in the method for reducing arcing in a mark region of a wafer according to the present invention.
FIG. 10 is a schematic view illustrating the reduction of the arcing in the mark area of the wafer according to the method of the present invention.
Element number description: 1-a substrate; 2-lower metal interconnection layer, 20-metal connection layer, 21-dielectric layer; 30-a first contact via, 31-a second contact via; 40-a first conductive plug, 41-a second conductive plug; 5-a top metal layer, 50-an electrode leading-out layer and 51-a wafer marking layer; 6-a passivation layer; 70-a first opening, 71-a second opening; 8-a photoresist layer; S1-S4: and (5) carrying out the following steps.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, which is a schematic diagram illustrating arc discharge occurring in the top metal layer of the wafer mark area, the top metal layer 5 includes an electrode lead-out layer and a wafer mark layer, and in order to ensure that the opening of the top metal layer 5 is fully filled, a passivation layer 6 is formed by a High Density Plasma (HDP) deposition method, so that the large area metal of the wafer mark area acts as an "antenna" to collect a large amount of charges. The wafer mark is usually located in the edge area of the wafer, the passivation layer 6 and the photoresist 8 are prone to incomplete coverage as the passivation layer is closer to the edge area, arrows indicate plasma etching, when the passivation layer is etched by high radio frequency power, a large amount of charges are locally and intensively accumulated on the top layer metal at the wafer mark by the charges in high-concentration plasma, and when the charge accumulation degree exceeds the bearing range, wafer discharging occurs. The probability of arc discharge in the marked area can be reduced to a certain extent by reducing the etching process of the passivation layer, but the production efficiency is improved and the cost is increased by reducing the process parameters. Therefore, an object of the present invention is to provide a structure and a method for reducing arc discharge in a wafer marking area, which can reduce the probability of arc discharge in the wafer marking area without reducing the etching parameters of a passivation layer, thereby improving the yield, improving the efficiency, and reducing the cost.
The present embodiment provides a method for reducing arcing in the mark area of a wafer, referring to fig. 2, which is a process flow diagram of the method, comprising the steps of:
s1: providing a substrate, and forming a lower metal interconnection layer on the substrate, wherein the lower metal interconnection layer comprises a metal connection layer and a dielectric layer covering the metal connection layer, and the metal connection layer is electrically connected with the substrate;
s2: forming a first contact through hole and a second contact through hole in the dielectric layer, wherein the first contact through hole and the second contact through hole expose the upper surface of the metal connecting layer;
s3: filling metal in the first contact through hole and the second contact through hole to form a first conductive plug and a second conductive plug which are electrically connected with the metal connecting layer;
s4: and forming a top metal layer on the dielectric layer and patterning the top metal layer to obtain an electrode lead-out layer and a wafer marking layer, wherein the electrode lead-out layer is electrically connected with the lower metal interconnection layer through the first conductive plug, and the wafer marking layer is electrically connected with the lower metal interconnection layer through the second conductive plug.
First, referring to fig. 3, step S1 is executed: providing a substrate 1, and forming a lower metal interconnection layer 2 on the substrate 1, wherein the lower metal interconnection layer 2 comprises a metal connection layer 20 and a dielectric layer 21 covering the metal connection layer 20, and the metal connection layer 20 is electrically connected with the substrate 1.
By way of example, the substrate 1 is not particularly limited and may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or any other suitable substrate.
As an example, the metal connection layer 20 is electrically connected to the substrate 1 through a conductive plug, specifically, before forming the metal connection layer 20, a bottom dielectric layer is formed on the upper surface of the substrate 1, then the bottom dielectric layer is patterned to obtain a through hole exposing the substrate 1, then the conductive plug filling the through hole and electrically connected to the substrate 1 is formed, then the metal connection layer 20 electrically connected to the conductive plug is formed on the bottom dielectric layer, and a top dielectric layer covering the metal connection layer 20 is formed; when the metal connection layer 20 is a multilayer, the bottom dielectric layer, the through hole, the conductive plug, and the metal connection layer 20 are formed multiple times.
By way of example, the metal connection layer 20 may be any suitable metal layer, and in this embodiment, the metal connection layer 20 is an aluminum (Al) conductive layer.
By way of example, the conductive plug may be any suitable conductive metal, and in this embodiment, tungsten (W) is used for the conductive plug.
By way of example, the dielectric layer 21 may be any suitable insulating dielectric layer, and in this embodiment, the dielectric layer 21 is made of silicon oxide.
Next, referring to fig. 4, step S2 is executed: forming a first contact through hole 30 and a second contact through hole 31 in the dielectric layer 21, wherein the first contact through hole 30 and the second contact through hole 31 both expose the upper surface of the metal connection layer 20.
As an example, when the metal connection layer 20 is a multilayer, the first contact via 30 and the second contact via 31 expose the upper surface of the uppermost metal connection layer 20, and the method for forming the first contact via 30 and the second contact via 31 includes dry etching, wet etching, laser drilling or other suitable methods; the first contact through hole 30 is located in an electrode lead-out region, and the second contact through hole 31 is located in a wafer marking region.
Next, referring to fig. 5, step S3 is executed: the first contact via 30 and the second contact via 31 are filled with metal to form a first conductive plug 40 and a second conductive plug 41 electrically connected to the metal connection layer 20.
As an example, the method of forming the first conductive plug 40 and the second conductive plug 41 includes electroplating, electroless plating, evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable method; the first conductive plug 40 and the second conductive plug 41 may be made of any suitable conductive material, and in this embodiment, the first conductive plug 40 and the second conductive plug 41 are made of tungsten.
Next, referring to fig. 6 and 7, step S4 is executed: and forming a top metal layer 5 on the dielectric layer 21 and patterning to obtain an electrode lead-out layer 50 and a wafer mark layer 51, wherein the electrode lead-out layer 50 is electrically connected with the lower metal interconnection layer 2 through the first conductive plug 40, and the wafer mark layer 51 is electrically connected with the lower metal interconnection layer 2 through the second conductive plug 41.
As an example, the top metal layer 5 is formed by electroplating, electroless plating, evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods, and the top metal layer 5 is patterned according to the electrode position and the wafer mark position.
As an example, further comprising the steps of:
as shown in fig. 8, a passivation layer 6 is formed on the patterned top metal layer 5, and the passivation layer 6 covers the top metal layer 5 and fills gaps between the top metal layers 5.
As an example, in order to ensure that the opened portion of the top metal layer 5 is sufficiently filled, the passivation layer 6 is formed by a High Density Plasma (HDP) vapor deposition method, and the material of the passivation layer 6 includes silicon oxide. Compared with the prior art that a large amount of charges are collected and accumulated in a marking area by the wafer marking layer 51 as an antenna in the process of forming the passivation layer 6, the second contact through hole 31 is arranged below the wafer marking layer 51 in the application, the second conductive plug 41 is arranged in the second contact through hole 31, the wafer marking layer 51 is interconnected with the lower metal interconnection layer 2 and the substrate 1 through the second conductive plug 41, the charges are uniformly distributed on the metal connection layer 20 and the substrate 1, and the local accumulation and excessive concentration of the charges collected by the wafer marking layer 51 are avoided.
(ii) as shown in fig. 9, a first opening 70 is formed in the passivation layer 6 above the electrode lead-out layer 50, and the first opening 70 exposes the upper surface of the electrode lead-out layer 50.
As an example, a photoresist layer is formed on the passivation layer 6 and patterned, and the passivation layer 6 is etched based on the patterned photoresist layer to form the first opening 70 (pad opening).
As an example, the second conductive plug 41 is arranged below the wafer marking layer 51, so that charges can be introduced into the lower metal interconnection layer 2 and the substrate 1, local accumulation and excessive concentration of the charges collected by the wafer marking layer 51 are avoided, the risk of arc discharge of the wafer marking is reduced, the rejection rate of the wafer is reduced, and the production cost is reduced; and the downtime frequency can be reduced, the cavity pollution is reduced, and the effective utilization rate of the machine is increased. In addition, a higher radio frequency power can be adopted in the process of etching the passivation layer 6 by a plasma etching method to form the first opening 70, the radio frequency power is increased within the range of ensuring that the arc discharge frequency of the Wafer marking area is acceptable, the yield Per Hour (Wafer Per Hour, WPH) is greatly improved, and the capacity is improved.
(iii) forming a second opening 71 in the passivation layer 6 above the wafer mark layer 51, wherein the second opening 71 exposes the upper surface of the wafer mark layer 51.
As an example, the passivation layer 6 is etched by laser etching to form the second opening 71 for wafer marking.
As an example, as shown in fig. 10, which is a schematic view showing that the arc discharge in the mark area is reduced in the method for reducing the arc discharge in the mark area of the wafer, since the second conductive plug is disposed below the mark layer of the wafer, the mark layer of the wafer is interconnected with the lower metal interconnection layer and the substrate through the second conductive plug, so that the charges are uniformly distributed on the metal connection layer and the substrate, and the arc discharge caused by the local accumulation of the charges collected by the mark layer of the wafer is avoided.
Thus, a structure for reducing arc discharge in a wafer marking area is manufactured, as shown in fig. 9, the structure includes a substrate 1, a lower metal interconnection layer 2, a first conductive plug 40, a second conductive plug 41, and a top metal layer 5, where the lower metal interconnection layer 2 is located above the substrate 1, the lower metal interconnection layer 2 includes a metal connection layer 20 and a dielectric layer 21 covering the metal connection layer 20, and the metal connection layer 20 is electrically connected to the substrate 1; the first conductive plug 40 is located in the dielectric layer 21, and the first conductive plug 40 is electrically connected with the metal connecting layer 20; the second conductive plug 41 is located in the dielectric layer 21, the second conductive plug 41 is electrically connected to the metal connection layer 20, and the second conductive plug 41 and the first conductive plug 40 are separated by a predetermined distance; the top metal layer 5 is located above the dielectric layer 21, the top metal layer 5 includes an electrode lead-out layer 50 and a wafer mark layer 51, the electrode lead-out layer 50 is electrically connected with the lower metal interconnection layer 2 through the first conductive plug 40, and the wafer mark layer 51 is electrically connected with the lower metal interconnection layer 2 through the second conductive plug 41.
By way of example, the substrate 1 is not particularly limited and may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or any other suitable substrate.
As an example, the metal connection layer 20 is electrically connected to the substrate 1 through a conductive plug, and the metal connection layer 20 includes a plurality of conductive layers spaced apart in a vertical direction, and two adjacent conductive layers are electrically connected through a conductive plug.
As an example, the second conductive plug 41 is disposed below the wafer mark layer 51, and the wafer mark layer 51, the lower metal interconnection layer 2 and the substrate 1 are interconnected through the second conductive plug 41, so that charges are uniformly distributed on the metal connection layer 20 and the substrate 1, and arc discharge caused by local accumulation and excessive concentration of charges collected by the wafer mark layer 51 is avoided.
In summary, in the structure and method for reducing arc discharge in the wafer marking area, the conductive plug is arranged below the wafer marking layer, and the wafer marking layer, the lower metal interconnection layer and the substrate are interconnected through the conductive plug, so that uniform distribution of charges on the metal connection layer and the substrate is realized, the occurrence of arc discharge due to local accumulation of charges collected by the wafer marking layer is avoided, the probability of arc discharge is reduced, the yield is improved, and the cost is reduced; moreover, the etching parameters of the passivation layer are not required to be reduced, and the productivity is greatly improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for reducing arcing in a marking area of a wafer, comprising the steps of:
providing a substrate, and forming a lower metal interconnection layer on the substrate, wherein the lower metal interconnection layer comprises a metal connection layer and a dielectric layer covering the metal connection layer, and the metal connection layer is electrically connected with the substrate;
forming a first contact through hole and a second contact through hole in the dielectric layer, wherein the first contact through hole and the second contact through hole expose the upper surface of the metal connecting layer;
filling metal in the first contact through hole and the second contact through hole to form a first conductive plug and a second conductive plug which are electrically connected with the metal connecting layer;
and forming a top metal layer on the dielectric layer and patterning the top metal layer to obtain an electrode lead-out layer and a wafer marking layer, wherein the electrode lead-out layer is electrically connected with the lower metal interconnection layer through the first conductive plug, and the wafer marking layer is electrically connected with the lower metal interconnection layer through the second conductive plug.
2. The method for reducing wafer marking area arcing as recited in claim 1, further comprising the steps of:
forming a passivation layer on the patterned top metal layer, wherein the passivation layer covers the top metal layer and is filled into the gap of the top metal layer;
forming a first opening in the passivation layer above the electrode extraction layer, the first opening exposing an upper surface of the electrode extraction layer;
and forming a second opening in the passivation layer above the wafer marking layer, wherein the second opening exposes the upper surface of the wafer marking layer.
3. The method of claim 2, wherein the wafer marking area arcing is reduced by: the method for forming the passivation layer comprises a high-density plasma chemical vapor deposition method, the method for forming the first opening comprises a plasma etching method, and the method for forming the second opening comprises a laser etching method.
4. The method of claim 1, wherein the wafer marking area arcing is reduced by: the metal connecting layer comprises a plurality of conducting layers arranged at intervals in the vertical direction, and the adjacent two conducting layers are electrically connected through a conducting plug.
5. The method of claim 1, wherein the wafer marking area arcing is reduced by: the metal connecting layer and the top metal layer are made of aluminum, and the first conductive plug and the second conductive plug are made of tungsten.
6. A structure for reducing arcing in a wafer marking area, comprising:
a substrate;
the lower metal interconnection layer is positioned above the substrate and comprises a metal connecting layer and a dielectric layer covering the metal connecting layer, and the metal connecting layer is electrically connected with the substrate;
the first conductive plug is positioned in the dielectric layer and is electrically connected with the metal connecting layer;
the second conductive plug is positioned in the dielectric layer and is electrically connected with the metal connecting layer, and the second conductive plug and the first conductive plug are separated by a preset distance;
the top metal layer is positioned above the dielectric layer and comprises an electrode leading-out layer and a wafer marking layer, the electrode leading-out layer is electrically connected with the lower metal interconnection layer through the first conductive plug, and the wafer marking layer is electrically connected with the lower metal interconnection layer through the second conductive plug.
7. The structure for reducing wafer mark area arcing as recited in claim 6, further comprising:
the passivation layer is positioned above the top metal layer and covers the top metal layer, and is filled into a gap between the top metal layers;
a first opening in the passivation layer above the electrode extraction layer, the first opening exposing the electrode extraction layer;
and the second opening is positioned in the passivation layer above the wafer marking layer, and the second opening exposes the wafer marking layer.
8. The structure for reducing wafer mark area arcing as recited in claim 6, wherein: the metal connecting layer comprises a plurality of conducting layers arranged at intervals in the vertical direction, and two adjacent conducting layers are electrically connected through a conducting plug.
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| CN (1) | CN115831865A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117238767A (en) * | 2023-11-13 | 2023-12-15 | 粤芯半导体技术股份有限公司 | Wafer etching method, semiconductor device manufacturing method and semiconductor device |
| CN117293083A (en) * | 2023-11-27 | 2023-12-26 | 江西萨瑞半导体技术有限公司 | Wafer processing method for reducing wafer arc discharge and wafer structure |
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| CN102683173A (en) * | 2012-03-31 | 2012-09-19 | 上海宏力半导体制造有限公司 | Method for reducing wafer arc discharge, and manufacturing method of integrated circuit |
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| CN1604316A (en) * | 2003-09-30 | 2005-04-06 | 株式会社东芝 | Semiconductor device which prevents peeling of low-permittivity film by using multilevel interconnection |
| CN101789391A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117238767A (en) * | 2023-11-13 | 2023-12-15 | 粤芯半导体技术股份有限公司 | Wafer etching method, semiconductor device manufacturing method and semiconductor device |
| CN117293083A (en) * | 2023-11-27 | 2023-12-26 | 江西萨瑞半导体技术有限公司 | Wafer processing method for reducing wafer arc discharge and wafer structure |
| CN117293083B (en) * | 2023-11-27 | 2024-02-06 | 江西萨瑞半导体技术有限公司 | Wafer processing method for reducing wafer arc discharge and wafer structure |
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