JPH03129743A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03129743A JPH03129743A JP9036590A JP3659090A JPH03129743A JP H03129743 A JPH03129743 A JP H03129743A JP 9036590 A JP9036590 A JP 9036590A JP 3659090 A JP3659090 A JP 3659090A JP H03129743 A JPH03129743 A JP H03129743A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- implanted
- ions
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 abstract description 53
- 150000002500 ions Chemical class 0.000 abstract description 7
- 239000002344 surface layer Substances 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- SXAAVRUIADQETA-UHFFFAOYSA-N 2-chloro-n-(2-methoxyethyl)-n-(2-methylphenyl)acetamide Chemical compound COCCN(C(=O)CCl)C1=CC=CC=C1C SXAAVRUIADQETA-UHFFFAOYSA-N 0.000 description 1
- 101100145155 Escherichia phage lambda cIII gene Proteins 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、縦型ＭＯ３ＦＥＴ、ＩＧＢＴ、スマートパワ
ーデバイスのように第一導電形の第一領域の表面部に選
択的に第二導電形の第二領域が形成され、第二領域の表
面部に選択的に第一導電形の第三領域が形成され、第二
領域の第一領域および第三領域にはさまれた領域をチャ
ネル形成領域としてその上にゲート絶縁膜を介してゲー
ト電極が設けられるＭＯＳ型の半導体装置の製造方法に
関する。Detailed Description of the Invention [Industrial Field of Application] The present invention is directed to selectively injecting a second conductive type into the surface of a first region of a first conductive type, such as a vertical MO3FET, IGBT, or smart power device. A second region is formed, a third region of the first conductivity type is selectively formed on the surface of the second region, and a region sandwiched between the first region and the third region of the second region is used as a channel forming region. The present invention relates to a method of manufacturing a MOS type semiconductor device on which a gate electrode is provided via a gate insulating film.
縦型ＭＯ３ＦＥＴは第１図に示す構造を有する。 The vertical MO3FET has a structure shown in FIG.
図において、 ドレイン層（第一領域）はｎ−Ｆｉｔお
よびｎ３層２よりなり、 ｎ−層の表面部にｐ〜ベース
層３（第二領域〉が選択的に形成されている。In the figure, the drain layer (first region) consists of an n-Fit and n3 layer 2, and a p~base layer 3 (second region) is selectively formed on the surface of the n-layer.
さらに、ベース層３の表面部にはｎ＋ソース層４〈第三
領域〉が選択的に形成されている。このソース層４とト
ルイン層１にはさまれたベース層３の領域がチャネル形
成領域５であり、その上にゲート酸化膜６を介してゲー
ト電極７が備えられている。ゲート電極７の上には絶縁
膜８を介してソース電極９が設けられ、絶縁膜８の開口
部でベース層３およびソース層４に接触しているが、ベ
ース層３のソース電極９との接触部分には高濃度ベース
層（９４層〉１０が形成されている。また、高濃度ドレ
イン層２にはドレイン電極１１が接触してぃる。このｎ
チャネルＭＯ３ＦＥＴのｎ＋高濃度ドレイン層の代わり
にｐ＋層を形成したものがｎチャネルＩ ＧＢＴである
。Furthermore, an n+ source layer 4 (third region) is selectively formed on the surface of the base layer 3. A region of the base layer 3 sandwiched between the source layer 4 and the toluin layer 1 is a channel forming region 5, and a gate electrode 7 is provided thereon with a gate oxide film 6 interposed therebetween. A source electrode 9 is provided on the gate electrode 7 via an insulating film 8 and is in contact with the base layer 3 and the source layer 4 at the opening of the insulating film 8. A high concentration base layer (94 layers) 10 is formed in the contact portion. Also, a drain electrode 11 is in contact with the high concentration drain layer 2.
An n-channel IGBT is a channel MO3FET in which a p+ layer is formed in place of the n+ heavily doped drain layer.
このような半導体装置においては、 ｎ＋ソース層４．
ｐ−ベース層３およびｎ−ドレイン層１からなる寄生ｎ
ｐｎ）ランジスタが存在し、ソース層４の下のベース層
３を電流が流れる際の電圧降下が大きいとこの寄生トラ
ンジスタがターンオンするので、Ｌ負荷耐量が低下する
。そこでｐ＋高濃度ソース層１０の拡散を深くする方法
、ベース層３にほう素を多く注入してソース層４の下側
部分の抵抗を下げる方法あるいはこの両者を併用するこ
とが行われる。In such a semiconductor device, an n+ source layer 4.
Parasitic n consisting of p-base layer 3 and n-drain layer 1
If a pn) transistor is present and a large voltage drop occurs when current flows through the base layer 3 under the source layer 4, this parasitic transistor is turned on, resulting in a decrease in L load withstand capability. Therefore, a method of deepening the diffusion of the p+ high concentration source layer 10, a method of implanting a large amount of boron into the base layer 3 to lower the resistance of the lower part of the source layer 4, or a combination of both are used.
表面のＭＯ８構造のチャネル形成領域５にチャネルを形
成するためのスレッシュホルド電圧は、ｐ−ベース層３
の抵抗を下げるほど高くなる。The threshold voltage for forming a channel in the channel forming region 5 of the MO8 structure on the surface is
The lower the resistance, the higher it becomes.
例えばｐ−層３のほう素（Ｂ）８度が１０１５〜” ／
ｃｆｆｌのときにはスレッシュホルド電圧は４■であ
るが、５ＸｌＯ”／ｃ１１！にすると５．５Ｖｌ：ナル
。For example, the boron (B) 8 degree of p- layer 3 is 1015~” /
When cffl, the threshold voltage is 4■, but when it is set to 5XlO''/c11!, it is 5.5Vl: null.
本発明の目的は、Ｌ負荷耐量を向上させるためにソース
層の下のベース層の抵抗を下げるときにもチャネル形成
のためのスレッシュホルド電圧が高くならない半導体装
置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the threshold voltage for channel formation does not increase even when the resistance of the base layer below the source layer is lowered in order to improve the L load withstand capability. .
上記の目的を達成するために、本発明は、第一導電形の
第一領域の表面部に選択的に第二導電形の第二領域が形
成され、第二領域の表面部に選択的に第一導電形の第三
領域が形成され、第二領域の第一領域および第三領域に
はさまれた領域をチャネル形成領域としてその上にゲー
ト絶縁膜を介してゲート電極が設けられる半導体装置の
製造方法において、第一領域の表面層に第一導電形のた
めの不純物を打込んだのち、選択的に第二導電形の第二
領域を形成するものとする。In order to achieve the above object, the present invention provides that a second region of a second conductivity type is selectively formed on the surface of the first region of the first conductivity type, and a second region of the second conductivity type is selectively formed on the surface of the second region. A semiconductor device in which a third region of the first conductivity type is formed, a region sandwiched between the first region and the third region of the second region is used as a channel formation region, and a gate electrode is provided thereon via a gate insulating film. In the manufacturing method, after impurities for the first conductivity type are implanted into the surface layer of the first region, a second region of the second conductivity type is selectively formed.
第一領域の表面層に打込まれた第一導電形のための不純
物は、そのあとで形成される第二領域の第二導電形のた
めの不純物の電気的作用を減少させる。従って第二領域
表面層の第二導電形のチャネル形成領域の実効的不純物
濃度が減少し、チャネル形成のためのスレッシュホルド
電圧の増加が抑制される。The impurity of the first conductivity type implanted into the surface layer of the first region reduces the electrical effect of the impurity of the second conductivity type of the second region subsequently formed. Therefore, the effective impurity concentration of the second conductivity type channel formation region of the second region surface layer is reduced, and an increase in the threshold voltage for channel formation is suppressed.
以下本発明の一実施例を第１図を引用して説明する。ｎ
“層２とｎ−層１からなるシリコン基板の ｎ−層１の
表面にひ素（＾Ｓ）イオンを注入する。An embodiment of the present invention will be described below with reference to FIG. n
“Arsenic (^S) ions are implanted into the surface of n-layer 1 of a silicon substrate consisting of layer 2 and n-layer 1.
図で点線の斜線１２で示したＡｓイオン注入領域のＡｓ
濃度は５×１０′６／ｃＩＩＩ程度になる。次にゲート
酸化膜６を形成し、その上に多結晶シリコンを堆積、パ
ターニングすることによりゲート電極７を形成する。次
いで、ゲート酸化膜６およびゲート電極７をマスクにし
て ｐ−層３のためのＢイオンを注入し、さらにレジス
トパターンを作成し、それをマスクにして ｐ＋層１０
のための深いＢイオン注入を行う。そしてｐ−層３．
ｐ“層１０の拡散のための加熱を行う。それにより深
さ４〜５μｍのｐ−層３゜深さ８μｍのｐ“層１０が生
ずる。このあと、ゲート酸化膜６．ゲート電極７および
レジストパターンをマスクにして深さ０．３μｍ程度の
ｎ＋層４のための＾Ｓイオンの注入、加熱を行い、ＰＳ
Ｇからなる絶縁膜の被覆、パターニングののち、Ａｌの
蒸着。As in the As ion implantation region indicated by dotted diagonal lines 12 in the figure
The concentration will be approximately 5×10′6/cIII. Next, a gate oxide film 6 is formed, and polycrystalline silicon is deposited thereon and patterned to form a gate electrode 7. Next, using the gate oxide film 6 and the gate electrode 7 as a mask, B ions for the p- layer 3 are implanted, and a resist pattern is created, and using this as a mask, the p+ layer 10 is implanted.
Perform deep B ion implantation for this purpose. and p-layer 3.
Heating is carried out for the diffusion of the p" layer 10. This results in a p" layer 10 with a depth of 4 to 5 .mu.m and a p" layer 3.degree. with a depth of 8 .mu.m. After this, gate oxide film 6. Using the gate electrode 7 and the resist pattern as a mask, ^S ions are implanted and heated for the n+ layer 4 to a depth of about 0.3 μm, and PS
After coating and patterning an insulating film made of G, evaporation of Al is performed.
パターニングによりソース電極９を形成する。この場合
、 ｐ−層３（ＤＢ１度Ｉｔ ５ ＸＩＯ”／ｃｉｉ度
テあるが、表面層はＡｓイオン注入領域１２が存在する
ため高抵抗になり、チャネル形成領域５へのｎチャネル
形成のためのスレッシュホルド電圧は４ｖ以下に低くな
る。なお、ｎ゛層２代わりにｐ＋層を有する ＩＧＢＴ
においても以上と同様に実施できる。また、導電形を逆
にしたｐチャネルＭＯ３型半導体装置にも実施できる。A source electrode 9 is formed by patterning. In this case, the p-layer 3 (DB1 degree It 5 The threshold voltage is lowered to 4V or less.In addition, the IGBT has a p+ layer instead of the n layer 2.
The above can also be implemented in the same way. Further, the present invention can also be implemented in a p-channel MO3 type semiconductor device in which the conductivity type is reversed.
本発明によれば、寄生トランジスタをターンオンしに（
くするために表面層にチャネル形成領域を有するベース
層の不純物濃度を高め抵抗を下げた場合にチャネル形成
のためのスレッシュホルド電圧が増加する問題が、予め
表面層にベース層と反対の導電形のための不純物を打込
むことによりチャネル形成領域の抵抗を高めることによ
って解決することができた。この結果、Ｌ負荷耐量が高
く、かつＭＯ３構造のスレッシュホルド電圧の低いＭＯ
３型半導体装置を得ることができた。According to the present invention, in order to turn on the parasitic transistor (
When the impurity concentration of the base layer with a channel formation region in the surface layer is increased to lower the resistance, the threshold voltage for channel formation increases. This problem could be solved by increasing the resistance of the channel forming region by implanting impurities. As a result, the MO3 structure has a high L load capacity and a low threshold voltage.
A type 3 semiconductor device could be obtained.
第１図は本発明の実施された縦型ＭＯ３ＦＥＴの断面図
である。
ｌｎ−ドレイン層（第一領域）、３ｐ−ベース層（第二
領域）、４ｎ＋ソ一ス層（第三領域）、５ チャネル形
成領域、６ ゲート酸化膜、７ゲート電極、１２ ＾
Ｓイオン注入領域。
〃
第１図FIG. 1 is a sectional view of a vertical MO3FET in which the present invention is implemented. ln- drain layer (first region), 3p-base layer (second region), 4n+ source layer (third region), 5 channel formation region, 6 gate oxide film, 7 gate electrode, 12 ^
S ion implantation region. 〃 Figure 1
Claims (1)
形の第二領域が形成され、第二領域の表面部に選択的に
第一導電形の第三領域が形成され、第二領域の第一領域
および第三領域にはさまれた領域をチャネル形成領域と
してその上にゲート絶縁膜を介してゲート電極が設けら
れる半導体装置の製造方法において、第一領域の表面層
に第一導電形のための不純物を打込んだのち、選択的に
第二導電形の第二領域を形成することを特徴とする半導
体装置の製造方法。1) A second region of the second conductivity type is selectively formed on the surface of the first region of the first conductivity type, and a third region of the first conductivity type is selectively formed on the surface of the second region. , a method for manufacturing a semiconductor device in which a region sandwiched between the first region and the third region of the second region is used as a channel formation region and a gate electrode is provided thereon via a gate insulating film; 1. A method of manufacturing a semiconductor device, comprising implanting impurities for a first conductivity type into a semiconductor device, and then selectively forming a second region of a second conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9036590A JPH03129743A (en) | 1989-07-07 | 1990-02-17 | Manufacture of semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-175941 | 1989-07-07 | ||
| JP17594189 | 1989-07-07 | ||
| JP9036590A JPH03129743A (en) | 1989-07-07 | 1990-02-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03129743A true JPH03129743A (en) | 1991-06-03 |
Family
ID=16004936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9036590A Pending JPH03129743A (en) | 1989-07-07 | 1990-02-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03129743A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04256368A (en) * | 1991-02-08 | 1992-09-11 | Nec Yamagata Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150769A (en) * | 1985-12-24 | 1987-07-04 | Fuji Electric Co Ltd | Semiconductor device |
-
1990
- 1990-02-17 JP JP9036590A patent/JPH03129743A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150769A (en) * | 1985-12-24 | 1987-07-04 | Fuji Electric Co Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04256368A (en) * | 1991-02-08 | 1992-09-11 | Nec Yamagata Ltd | Semiconductor device |
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