JPH03124240U - - Google Patents
Info
- Publication number
- JPH03124240U JPH03124240U JP3439190U JP3439190U JPH03124240U JP H03124240 U JPH03124240 U JP H03124240U JP 3439190 U JP3439190 U JP 3439190U JP 3439190 U JP3439190 U JP 3439190U JP H03124240 U JPH03124240 U JP H03124240U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- channel
- channels
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005055 memory storage Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案に係る多チヤネルデータのメモ
リ格納装置の一実施例を示す回路構成図、第２図
はメモリ内のデータの様子を示す図、第３図は従
来のメモリ格納装置のメモリ内のデータの配列を
示す図である。
１……メモリ、２……マルチプレクサ、３……
チヤネルセレクタ、４……Ａ／Ｄ変換器、５……
パルス発生器、６……１１ビツトカウンタ。
Fig. 1 is a circuit configuration diagram showing an embodiment of a multi-channel data memory storage device according to the present invention, Fig. 2 is a diagram showing the state of data in the memory, and Fig. 3 is a memory of a conventional memory storage device. FIG. 1...Memory, 2...Multiplexer, 3...
Channel selector, 4... A/D converter, 5...
Pulse generator, 6...11 bit counter.
Claims (1)
おいて、 所定のビツト数のアドレス空間を持つメモリと
、 複数チヤネルを有し、これらのチヤネルに入力
されるアナログ信号を選択的に取り込むマルチプ
レクサと、 このマルチプレクサに一定のビツト数の制御信
号を与えチヤネルを選択するとともにこのビツト
信号を前記メモリの上位ビツトのアドレスに接続
するチヤネルセレクタと、 前記マルチプレクサに接続されるアナログ・デ
ジタル変換器と、 指定されたチヤネル数全てをメモリに格納した
後にステツプ終了パルス信号を発生するパルス発
生器と、 このパルス発生器からの入力パルスに基づいて
カウントアツプしていくとともに、このカウント
値を前記メモリの下位にビツトアドレスとして導
入するビツトカウンタとを具備し、 前記チヤネルセレクタで指定された上位アドレ
スでチヤネル分けを行い、前記ビツトカウンタで
指定された下位アドレスでチヤネル分けされたア
ドレスに、随時前記アナログ・デジタル変換器に
よりデジタル値に変換されたデータを格納するこ
とを特徴とする多チヤネルデータのメモリ格納装
置。[Claims for Utility Model Registration] A device for storing multi-channel data in a memory, which has a memory with an address space of a predetermined number of bits and multiple channels, and selectively selects analog signals input to these channels. a channel selector that selects a channel by applying a control signal of a certain number of bits to this multiplexer and connects this bit signal to the address of the upper bit of the memory; and an analog-to-digital converter connected to the multiplexer. A pulse generator that generates a step end pulse signal after storing all the specified number of channels in memory, and a pulse generator that counts up based on the input pulse from this pulse generator and converts this count value to the above value. It is equipped with a bit counter that is introduced as a bit address in the lower part of the memory, performs channel division using the upper address specified by the channel selector, and inputs the aforementioned information to the address divided into channels by the lower address specified by the bit counter at any time. A multi-channel data memory storage device characterized by storing data converted into digital values by an analog-to-digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3439190U JPH03124240U (en) | 1990-03-30 | 1990-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3439190U JPH03124240U (en) | 1990-03-30 | 1990-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03124240U true JPH03124240U (en) | 1991-12-17 |
Family
ID=31538822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3439190U Pending JPH03124240U (en) | 1990-03-30 | 1990-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03124240U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008103324A (en) * | 2006-10-19 | 2008-05-01 | Samsung Sdi Co Ltd | Secondary battery and its manufacturing method |
-
1990
- 1990-03-30 JP JP3439190U patent/JPH03124240U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008103324A (en) * | 2006-10-19 | 2008-05-01 | Samsung Sdi Co Ltd | Secondary battery and its manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH03124240U (en) | ||
| JPH03124239U (en) | ||
| JPS5832597U (en) | waveform storage device | |
| JPS5821117A (en) | Parallel head recorder | |
| JPS59108938U (en) | data acquisition circuit | |
| JPS5813733U (en) | Channel selection device | |
| KR940007584B1 (en) | Digital recording and reproducing circuit of computer audio system | |
| JPH0418370U (en) | ||
| JPS6429926U (en) | ||
| JPS6356834U (en) | ||
| JPH0242173B2 (en) | ||
| JPS5832503U (en) | Multi-channel continuous output D/A conversion circuit | |
| KR930007332B1 (en) | High speed insulated d/a converter used for bipolar ram | |
| JPS5914425U (en) | Analog-digital converter | |
| JPH051773Y2 (en) | ||
| SU1015369A1 (en) | Analog signal input-output device | |
| JPH0172628U (en) | ||
| JPH10106171A (en) | Digital data writing method, storage medium and storage device | |
| JPH0381564U (en) | ||
| JPH04306919A (en) | A/d converter | |
| JPS6214854B2 (en) | ||
| JPH0221566U (en) | ||
| JPS6277929U (en) | ||
| JPS6199239U (en) | ||
| JPS5826690B2 (en) | Channel selection device |