JPH03124034A - Manufacture of mos type semiconductor device - Google Patents

Abstract

PURPOSE:To set an impurity depth shallowly in a region other than plug parts of source and drain regions by injecting impurity supporting materials into parts corresponding to the source and drain regions in an insulating film and forming the plug parts by diffusing impurities thermally and then, exposing the source and drain regions after removing the impurity supporting materials. CONSTITUTION:Impurity supporting materials 4 and 5 which hold an n-type or a p-type impurity are injected into openings that are provided at parts corresponding to source and drain regions S and D in an interlayer insulating film 2 and the above materials are heated and diffused thermally in the S and D regions and then, plug parts 6 are formed. Further, the supporting materials 4 and 5 are removed by performing anisotropic etching on the upper faces of the plug parts and then, the S and D regions are exposed. As a result, no crystal disorder takes place on the surface of a substrate when the plug parts 6 are formed and, as heating conditions are relieved all the more, regions other than the plug parts in the S and D regions are set so as to make their impurity depths shallow and their operation characteristics are improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a MOS type semiconductor device, and in particular,
The present invention relates to a method for manufacturing a MOSO8 type conductor device having plug portions in the source and drain.

[Prior Art] As a conventional MOS type semiconductor device, for example, an n-type semiconductor device will be explained as an example.
type single crystal silicon substrate (a), and this silicon substrate (
Source/drain (S) (D) formed by n-type impurities such as phosphorus (P) introduced into the film (a) and provided on both sides of the gate (G), and an insulating film (b) such as 8102. The gate (G) and source/drain (S) (D
), the main part of which is connected to the wiring parts (C) to (C), and the voltage (V
, ) is applied to the gate (G), and the gate voltage (Vo
), a channel is formed in the silicon substrate (a) and acts as an ON state, while the gate voltage (
A device is widely known that operates as an OFF state as the channel is no longer formed as V6) is lowered.

By the way, when attempting to miniaturize this MOS type semiconductor device, in order to maintain the function of the semiconductor device before the reduction, it is necessary to reduce the thickness direction in accordance with the reduction rate in the horizontal direction. S)(
The depth of introduction of the impurities constituting D) into the silicon substrate (a) also had to be set shallow in accordance with the reduction ratio, as shown in FIG.

However, if the depth of introduction of the impurities constituting the source/drain (S) (D>) is set shallow, the insulation gl(b)
When providing the openings (e) (e) in the parts corresponding to the source/drain (S) (D) of the source/drain (S) (
The D) side may also be etched to expose the silicon substrate (a), and the wiring portion (C) and the silicon substrate (a) may be short-circuited at this exposed portion.

Furthermore, even if the etching conditions are set strictly to prevent etching on the source/drain (S) and (D) sides, metal atoms such as aluminum constituting the wiring portion (C) may be removed from the silicon substrate (a > side, and due to this diffusion phenomenon, the wiring portion (C) and the silicon substrate (a) may be short-circuited as shown in FIG.

When the wiring part (C) and the silicon substrate (a) are short-circuited, electrons or holes supplied from the source, drain, (S) and (D) flow into the silicon substrate (a). Therefore, there was a drawback that it no longer functions as an MO3 type semiconductor device.

Therefore, conventionally, as shown in FIG. 8, the impurity is introduced deeper into the silicon substrate (a) into the connection region with the wiring part (C) in the source/drain (S) (D) than in other parts. A method has been adopted in which a plug portion (f) set large is provided to prevent short circuit between the wiring portion (C) and the silicon substrate (a) to eliminate the above-mentioned drawbacks.

By the way, when forming the plug portion <1> in the source/drain (S) (D), the following method has conventionally been used.

That is, as shown in FIG. 9, an insulating film (b) is formed in a negative shape on a silicon substrate (a) on which thin layers of sources and drains (S) and (D) are formed, and an etching process is performed. As a result, openings (e) ~<e
), as shown in FIG. 10, a resist (r) is formed in a region other than the region where the plug portion (f) is to be formed.

Next, the above openings (
After implanting n-type or p-type impurities into the regions corresponding to e) to (e) by ion implantation and applying a planarizing material as necessary, the silicon substrate (a) accompanying the above ion implantation is prepared. In order to repair the disordered crystals on the surface and to thermally diffuse the implanted impurity to a predetermined depth, the silicon substrate (a) is exposed to high temperature for a long time to form a plug part (f) as shown in FIG. They were formed at predetermined locations of the source/drain (S) and (D).

[Problems to be Solved by the Invention] As described above, in the conventional method, the silicon substrate (a) is heated for a long time at high temperature for the purpose of repairing the crystal disorder of the silicon substrate (a) and thermally diffusing impurities. Since a time-exposure step is required, as shown in FIG. 12, this heat treatment may also thermally diffuse impurities in regions other than the plug portions (f) of the source/drain (S) and (D). - There was a problem that the depth of introduction of impurities constituting the drains (S) and (D) became significantly deeper than the reduction rate of the semiconductor device, resulting in fluctuations in its operating characteristics.

In addition, 0MOS which is a combination of nMOS type and DMOS type
When forming a plug portion in a type semiconductor device, according to the conventional method, it is necessary to ion-implant different types of impurities into the nMO3 type region and the pMO3 type region, so the resist forming process is required twice. Therefore, there was a problem that the manufacturing process was complicated.

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned problems, and its object is to provide a simple and easy way to set the impurity depth in regions other than the source/drain plug portions to be shallow. An object of the present invention is to provide a method for manufacturing a MOS type semiconductor device 0.

In other words, the invention according to claim 1 provides a substrate, a source/drain formed of n-type or n-type impurity introduced into the substrate and provided respectively with a gate therebetween, and a source/drain connected to the gate and source/drain via an insulating film. A method for manufacturing an MO3 type semiconductor device, comprising a wiring part connected to the drain, and a plug part in which the depth of impurity introduction into the substrate is set to be larger in the region connected to the source/drain wiring part than in other parts. As a premise, there is an implantation step of injecting an n-type or an impurity retaining material that retains an n-type impurity into the openings provided in the portions of the insulating film corresponding to the source and drain, and heating the implanted impurity retaining material. a heating step of thermally diffusing impurities of the impurity holding material into the source/drain region to form the plug portion; and a removal step of removing the impurity holding material injected into the opening to expose the source/drain. On the other hand, the invention according to claim 2 is characterized in that the impurity retaining material is made of an insulating flattening material that flattens the surface of the insulating film, and・This device is characterized in that the removal process for exposing the drain is performed using a reactive ion etching method.

In the invention according to claims 1 and 2, the impurities held by the impurity holding material (for nMO3 type source/drain, phosphorus (P), antimony (Sb), arsenic ( n-type impurities such as As) can be applied, and n-type impurities such as gallium (Ga), boron (B), and indium (In) can be applied to the pMO3 type source/drain.

In addition, as an impurity retaining material that retains this impurity, a material that retains the impurity and has fluidity that can be injected into the opening of the insulating film by a coating method such as a spin code method is suitable. For example, S, 0. G (Spin O
Silanol-based or siloxane-based silicon compounds, etc., which are widely used as planarizing materials in the coating method (n Glass: coated and fired oxide film), can be used. Further, as a means for retaining impurities with these materials, for example, a method of adding impurities such as P2O5 to the base material in the manufacturing step of the silanol-based or siloxane-based silicon compound, etc. can be adopted.

Note that when the latter planarizing material is used as the impurity retaining material, the planarizing process can be performed at the same time, which has the advantage of reducing the number of steps. In addition, when these technical means are applied to the manufacturing method of a 0MOS type semiconductor device that is a combination of nMO3 type and 1) MOS type, other Since it becomes difficult for the impurity holding material to be implanted, there is an advantage that the resist forming step for regulating the impurity introduction region can be performed only once.

On the other hand, as a heating means for thermally diffusing impurities held by the impurity holding material to form a plug part, a heating furnace method in which the entire substrate is introduced into a furnace to cause thermal diffusion, as well as Ar+, Kr+ ion lasers such as, gas lasers such as C02, or ArF, XeC1, KrF, etc. (D
Neat? A thermal energy irradiation method that causes thermal diffusion by irradiating L'-saW thermal energy or the like can be applied.

In addition, in this technical means, when forming the plug part, a thermal diffusion method using an impurity retaining material (i.e., solid phase diffusion method) is adopted, and the ion implantation method used in the conventional method is not used. This makes it difficult for crystal disorder on the substrate surface to occur. Therefore, since no heat treatment is required to repair the crystal, the heating time when forming the plug portion is shortened, and the source and
It becomes possible to set the impurity depth of the drain to be shallow. Particularly, when the latter thermal energy irradiation method is adopted as the heating means, the heating time becomes extremely short, so there is an advantage that the impurity depth can be set shallower.

Further, as a means for removing the impurity retaining material implanted into the opening of the insulating film and exposing the source/drain, an appropriate etching method such as reactive ion etching (RIE) method or wet etching method can be applied. . Note that the impurity retaining material is made of a flattening material such as SOG, and RIE is used as an etching means in the removal process.
When the method is adopted, the impurity retaining material injected into the opening of the insulating film and this insulating film are anisotropically etched and the M is removed in the thickness direction of each, so that the opening gradient in the opening is reduced. will be processed into a loose state. Therefore, there is an advantage that disconnection of the wiring portion is less likely to occur in this opening.

Furthermore, regarding the scope of application of these technical means, nMO3
In addition, it can be applied to the manufacturing of semiconductor devices of the type semiconductor device, pMO3 type semiconductor device, and cMO3 type semiconductor device that is a combination of these devices, and can also be applied to the production of hot carriers by setting the impurity concentration on the side of the source/drain opposite to the gate to be low. LDD (Lightly Doped Drain) to prevent occurrence
Naturally, the present invention can also be applied to manufacturing a MOS type semiconductor device having a structure.

Furthermore, when these technical means are applied to the manufacture of cMOS type semiconductor devices, if the thermal diffusion coefficient of the impurity used on the pMOS side or nMOS side is large, the depth of impurity introduction into the source/drain becomes slightly deeper. Therefore, there may be no need to take the trouble to provide a plug portion at that location.

In such a case, it goes without saying that the plug portion only needs to be formed in the source/drain on the side where the introduction depth is set to be shallow.

[Operation] According to the invention according to claim 1, an implantation step of implanting an impurity retaining material retaining an n-type or p-type impurity into an opening provided in a portion corresponding to the source/drain of the insulating film; heating the implanted impurity holding material and thermally diffusing the impurities of the impurity holding material into the source/drain region to form the plug portion;
and a removal step of removing the impurity retaining material injected into the opening to expose the source/drain, and the heating conditions are changed accordingly so that crystal disorder on the substrate surface does not occur when forming the plug part. Since the impurity is relaxed, it becomes possible to set the impurity depth in the region other than the source/drain plug portion to be shallow.On the other hand, according to the invention according to claim 2, the impurity retaining material flattens the surface of the insulating film. The material is made of a reactive planarization material, and the removal process to expose the source and drain is performed using a reactive ion etching method. Moreover, it becomes possible to set the opening slope of the opening in the insulating film to be gentle.

[Example] First Example Hereinafter, an example in which the present invention is applied to a method for manufacturing a cMO3 type O3 transistor as shown in FIG. 1 will be described in detail with reference to the drawings.

First, as shown in FIG. 2(A), BF2 ions are implanted slightly deeply to form a thick p-MOS source.
Drains (S) (D) and thin film nMOS side source/drain (S) (D>) formed by relatively shallow implantation of POCl3 ions are provided, and these source/drain (S) (D>) are provided.
An interlayer insulating film (2) made of SiO2 is laminated in a --like manner on the surface of a single crystal silicon substrate (1) in which gates (G) (G) are provided between drains (S) (D), and Etching treatment is performed according to the photolithography method described above, and openings (31) to 3 are formed in the interlayer insulating film (2) at portions corresponding to gate 1-(G) and source/drain (S) (D), respectively.
(32) will be established.

Next, as shown in FIG. 2(B), a resist (r) is selectively formed on the pMOS side, and the opening (3) of the interlayer insulating film (2) is
After partially blocking 1) to (31) with this resist (r), SOG having the following composition to which phosphorus (P) was added (however, viscosity 4.0 CP>) was applied by spin code method. As shown in FIG. 2 (C), an impurity retaining material (4) made of SOG is injected into the openings (32) to (32) of the interlayer insulating film (2) on the nMO5 side, and at the same time
A baking treatment was performed for 15 seconds at a temperature of .degree.

In this case, the coating conditions are coater rotation speed: 2000 to 4
000 rpm, coating time = 30 seconds, and at room temperature.

Further, the composition of the SOG to which phosphorus was added was as follows.

1=1 mixture of tetrahydroxysilane monomer and tri-droxymethylsilane monomer (Sio2 equivalent concentration)...8
Methyl alcohol......50 Parts propylene glycol...25 parts by weight Phosphorus...0.5 parts by weight Next, the resist (r) was removed to form an opening on the 0MOS side. After exposing the parts (31) to (31), SOG having the same structure except that it does not contain phosphorus is applied under the same conditions by the spin-to-1 method to enter the openings (31) to (31). S
Inject the oG flattening material (5) (see second diagram),
And beta treatment was carried out for about 15 seconds at a temperature of 150-200''C.

Here, when the flattening material (5) is applied by the spin code method, the frontage part (32) to <32 on the nMOS side
Since the impurity holding material (4) made of SOG has already been implanted inside, this planarization material (5) is hardly implanted into the openings (32) to (32) on the nMOS side.

Then, the silicon substrate (1) in which the impurity holding material 44 (4) made of SOG and the planarization material (5) are injected into the openings (31) to (32) is introduced into a clean oven,
Heat the above S at 400°C for 15 minutes in a nitrogen atmosphere.
OG is thermally polymerized to flatten the surface of the interlayer insulating film (2), and phosphorus in the impurity holding material (4) is thermally diffused into the source/drain (S) and (D) regions on the nMOS side. A plug portion (6) as shown in (E) was formed.

Furthermore, this surface was subjected to reactive ion etching treatment using CF4+H2 gas, and the impurity retaining material (4) made of SOG was injected into the surface of the interlayer insulating film (2) and into the openings aTl (31) to (32). ) and the planarization material (5) are anisotropically etched. Through this etching process, the interlayer insulating film (2) is formed in the openings (31) to (32).
Since the impurity retaining material (4) and the flattening material (5) are removed in equivalent amounts in the thickness direction, the opening slope of the openings (31) to (32) is as shown in FIG. 2 (F). As shown, the openings (31) to (32) become looser and the openings (31) to (32)
) are removed to expose the source/drain (S) and (D).

Next, the above nMOS is made of metal such as aluminum.
side, and source/drain (S) (D) on the 0MOS side
A cMOS type O8 transistor as shown in FIG. 2(G) was obtained by arranging wiring portions (7) to (7) connected to the gate (G) and the gate (G).

As described above, according to the manufacturing method according to this embodiment, when forming the plug part (6), a thermal diffusion method (that is, a solid phase diffusion method) using an impurity retaining material (4) made of SOG containing phosphorus is used. Since the ion implantation method used in the conventional method is not adopted, crystal disorder on the surface of the single crystal silicon substrate (1) is less likely to occur during the formation of the plug portion. Since no heat treatment is required to repair the crystal, the heating time required to form the plug portion is shortened, so the plug portion (
It becomes possible to set the impurity depth of the source/drain (S) (D) shallow in regions other than 6).

Therefore, the source/drain (S) (D) plug portion (6
) can be set shallow in accordance with the reduction rate of the semiconductor device, which has the advantage that a cMOS,',lt-transistor that maintains the operating characteristics before reduction can be easily manufactured.

Furthermore, an impurity retaining material (4) made of SOG, which is used as a flattening material, is used, and the openings (31) to (3) are
Since reactive ion etching is used as a means of removing the impurity retaining material (4) and planarizing material (5) in 2), it is possible to planarize the interlayer insulating film (2) and remove the above opening. The opening slopes of the portions (31) to (32) can be set gently.

Therefore, cMO is unlikely to cause disconnection of wiring parts (7) to (7).
It has the advantage that a 3-type O3 transistor can be manufactured easily.

◎Second Embodiment The method for manufacturing a cMOS type O8 transistor according to this embodiment is to
The manufacturing method of this embodiment is similar to that of the first embodiment, except that the means for removing the impurity retaining material (4) and the planarization material (5) is a wet etching method.

That is, the flattening material (5) is placed inside the openings (31) to (31) on the LDMOS side, and the opening (3) is placed on the nMOS side.
2) After implanting the impurity holding material (4) into (32) by the spin code method, this silicon substrate (1) is introduced into a clean oven, and the phosphorus in the impurity holding material (4) is transferred to the nMOS side. The plug portion 6) as shown in FIG. 3(A) was formed by thermal diffusion (solid phase diffusion) into the source/drain (S) and (D) regions.

Next, it remains on the surface of the interlayer insulating film (2) and forms the opening (
The SOGM impurity holding material (4) and planarization material (5) implanted in 31) to (32) are removed by wet etching using HF, as shown in Fig. 3(B)k. Source/drain (S) on 0MOS side and nMO3 side (
1)) Expose.

Furthermore, the wiring portions <7) to 7 are formed in the same manner as in the first embodiment.
) to obtain a 0MOS type transistor as shown in FIG. 3<C).

In the manufacturing method according to this example as well, as in the first example, a 5o-GFJ impurity retaining material containing phosphorus (4
) thermal diffusion method (in other words, solid phase expansion RLI method), it is possible to set the impurity depth of the source/drain (S) (D) shallow in the region other than the plug part (6). It becomes possible.

Therefore, the source/drain (S) (D) plug portion (6
) can be set to be shallow in accordance with the reduction rate of the semiconductor device, which has the advantage that a cMO3 type O3 transistor that maintains the operating characteristics before reduction can be easily manufactured.

However, according to the manufacturing method according to this embodiment, unlike the first embodiment which adopted the reactive ion etching method, a wet etching method is adopted, so that the manufacturing method shown in FIG.
), the opening slopes of the openings <31) to (32) cannot be set gently, and the manufacturing method according to the first embodiment is slightly superior in this respect.

However, when manufacturing MOS transistors with a not very high degree of integration (reduction rate), this method cannot be applied because disconnection of the wiring parts (7) to (7) is unlikely to occur even if the aperture slope is slightly severe. In addition, by employing a simple wet etching method, this embodiment has the advantage of improving manufacturing efficiency compared to the first embodiment.

In this example, similarly to the first example, the silicon substrate (1) is introduced into a clean oven, and the phosphorus in the impurity holding material (4) is removed from the source/drain (S) of the nMOS full. D) Thermal diffusion (solid phase diffusion) is applied to the region, but instead of this method, for example, an ion laser such as Ar+ or Kr+, a gas laser such as CO2, or
rF, XeCl.

A method using thermal energy such as an excimer laser such as KrF can also be applied. In this case, since the heating time is extremely short compared to the method using the clean oven, there is an advantage that the impurity depth can be set shallower.

◎Third Embodiment The method for manufacturing a cMOS type O8 transistor according to this embodiment is to
This is similar to the manufacturing method according to the first embodiment except that plug portions are also formed at the source/drain (S) and (D) on the MOS side.

That is, as shown in FIGS. 2(A) to (C), nMO
SO containing phosphorus in the openings (32) to (32) on the S side
After implanting the impurity holding material (4) made of G and removing the resist (r) provided on the pMOS side, the same structure as that of the first embodiment was used except that boron (B) was included instead of phosphorus. SOG having the same composition as the impurity retaining material was applied by the spin code method under the same conditions to form the openings (31) on the 0MO3 side.
An impurity retaining material (4'') made of SOG was injected into (31) (see Figure 4A) and baked for about 3 minutes at a temperature of 150 to 200°C. When the impurity retaining material (4°) made of SOG containing SOG is applied by the spin code method, the openings (32) to (32) on the nMO3 side
32) Inside is an SOG impurity retaining material (4) containing phosphorus.
) has already been implanted, the SOG impurity retaining material (4°) containing boron is inserted into the opening (32) on the 0MOS side.
~(32) was almost never injected. Therefore, the manufacturing method according to this embodiment has the advantage that the resist forming step for regulating the region into which impurities is introduced can be performed only once, compared to the conventional method.

Then, the silicon substrate (1) into which SOG impurity retaining materials (4) (4°) containing phosphorus or boron were injected into the openings (31) to (32), respectively, was introduced into a clean oven. , heated at 400°C for 15 minutes in a nitrogen atmosphere to thermally polymerize the SOG to flatten the surface of the interlayer insulating film <2) and impurity retaining material <4) (4
By thermally diffusing phosphorus or boron in the source/drain (S) and (D) regions on the nMO3 side and the pMOS side, respectively, a plug part (6) <6° as shown in FIG. 4(B) is formed.
) was formed.

Furthermore, this surface is subjected to a reactive ion etching process to form the surface of the interlayer insulating film (2) and the openings (31) to (
32) SOGM impurity retaining material injected into (4)
(4°) is anisotropically etched.

By this etching process, the openings (31) to (3) are etched.
In 2), the interlayer insulating film (2) and the impurity retaining material (4')
(4°) is removed by an equivalent amount in the thickness direction, the opening slope of the openings (31) to <32) becomes gentle as shown in FIG. 4(C), and the opening Impurity retaining material (4) in parts (31) to (32) <
4°) are removed respectively, and the source and drain (S) (D>
is exposed.

Next, the 0MOS side is made of metal such as aluminum,
In addition, wiring parts (7) to (7) connected to the source/drain (S) (D) and gate (G) on the pMOS side are arranged to form a cMOS type O8 transistor as shown in Fig. 4 (D). I got it.

Also in this example, as in the manufacturing method according to the first example, the operating characteristics before reduction are maintained, and
cMOS type O8 where new lines in wiring part (7) to (7) are difficult to occur
This has the advantage that the resistor can be easily manufactured.

Furthermore, as mentioned above, plug portions (6) (6
Despite the formation of the impurity-introducing region (°), only one resist forming step is required to control the region into which impurities are introduced, so this method has the advantage of further improving manufacturing efficiency compared to the conventional method.

[Effects of the Invention] According to the invention according to claim 1, since the crystals on the surface of the substrate are not disordered when forming the plug portion, and the heating conditions are relaxed accordingly, the region other than the source/drain plug portion is It becomes possible to set the impurity depth shallowly.

Therefore, the impurity depth in the regions other than the plug portions of the source and drain can be set to be shallow in accordance with the reduction rate of the semiconductor device, which has the effect of easily manufacturing a MOS type semiconductor device that maintains the operating characteristics before reduction. There is.

On the other hand, according to the invention according to claim 2, in addition to being able to set the impurity depth to be shallow, it is also possible to perform a planarization process.
Moreover, it becomes possible to set the opening slope of the opening in the insulating film to be gentle.

Therefore, it is not possible to easily manufacture a MOS type semiconductor device that maintains the operating characteristics before shrinkage and is less likely to be disconnected in the wiring portion at the opening.

[Brief explanation of the drawing]

1 to 4 show embodiments of the present invention, FIG. 1 is a sectional view showing the structure of a 0MOS type transistor according to the first embodiment, and FIGS. Process diagrams showing the manufacturing process of a transistor according to one embodiment, FIGS.
C) is a process diagram showing the manufacturing process of the transistor according to the second embodiment, and FIGS. 5 and 6 are cross-sectional views showing the groove formation of a MOS type semiconductor device obtained by the conventional method, and FIGS. 7, 8, and 12 are partially enlarged views of FIG. 6, and FIG. 9, respectively. Figures 10 and 11
The figure is a process diagram showing the manufacturing process of a conventional CMOS type semiconductor device. [Explanation of symbols] (S)... Source (D)... Drain (G)... Gate 1)... Substrate 2)... Interlayer insulating film 4)... Impurity holding material 5> ...Flattening material 6)...Plug part (7)...Wiring part (31) (32)...Opening part Fig. 7 Fig. 10

Claims (2)

[Claims] (1) A substrate, a source/drain formed by n-type or p-type impurities introduced into the substrate and provided on both sides of the gate, and wiring connected to the gate and source/drain via an insulating film. and the above source/
In a method for manufacturing a MOS type semiconductor device having a plug portion in which the depth of impurity introduction into the substrate is set to be larger than in other portions in a region connected to a drain wiring portion, the plug portion is provided in a portion of the insulating film corresponding to the source/drain. An implantation step of injecting an impurity holding material that holds an n-type or p-type impurity into the opened opening, and heating the implanted impurity holding material to thermally diffuse the impurities of the impurity holding material into the source/drain region. A method for manufacturing a MOS type semiconductor device, comprising: a heating step of forming the plug portion using a metal oxide, and a removing step of removing the impurity retaining material injected into the opening to expose the source/drain. . (2) The impurity retaining material is made of an insulating planarizing material that flattens the surface of the insulating film, and the removal process that exposes the source and drain is performed using reactive ions.
A method for manufacturing a MOS type semiconductor device according to claim 1, characterized in that the method is constructed by an etching method.