JPH07321313A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress short-channel effect in a MOS transistor, etc., and to improve the function for preventing punch-through. CONSTITUTION:A gate oxide film 2 is formed on the surface of single-crystal silicon substrate 1, a gate electrode 3 and silicon oxide film 4 are laminated and formed on the gate oxide film 2, and at the same time ions are implanted into the single-crystal silicon substrate 1 with the silicon oxide film 4 as a mask, and amorphous parts 6a and 6b are formed below the surface of the single-crystal silicon substrate 1. Further, after performing ion implantation of an impurity into a part excluding each tail part 6 of the amorphous parts 6a and 6b, heat treatment is made, the above amorphous parts 6a and 6b are subjected to solid phase growth and a single crystal is recovered, and at the same time diffusion layers 10a and 10b with thin diffusion layers 10c and 10c are formed at an opposing part by diffusing the impurity where ions are implanted into the amorphous parts 6a and 6b and the tail part 6c.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device such as a MOS transistor.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional LDD (Lightly Doped Dr).
FIG. 6 is a cross-sectional structure diagram showing a manufacturing process of a MOS transistor having an ain source) structure. First, as shown in FIG. 5A, the single crystal silicon substrate 1
The surface of is thermally oxidized to form the gate oxide film 2 on the surface of the single crystal silicon substrate 1. After that, polycrystalline silicon is deposited on the surface of the gate oxide film 2 by the CVD method, and subsequently, a silicon oxide film is deposited to a predetermined thickness, respectively, and the gate electrode 3 of polycrystalline silicon is stacked in a photolithography process. The oxide film 4 is patterned.

Next, as shown in FIG. 5B, using the silicon oxide film 4 as a mask, n-type impurity ions such as phosphorus are implanted from the surface side of the gate oxide film 2 to form the gate oxide film 2. N ⁻ type diffusion layers 9a and 9b, which are diffusion layers having a low impurity concentration, are formed at a predetermined depth from the surface of the single crystal silicon substrate 1 on the lower side. Both diffusion layers 9a and 9b
The opposite end portions (referred to as tail portions) 9c are located under the gate electrode 3 in such a manner that they partially overlap with each other.

As shown in FIG. 5C, after forming a side wall spacer (hereinafter simply referred to as a spacer) 14 made of a thick polycrystalline silicon film so as to cover the side peripheral surface of the gate electrode 3, the arsenic is used as a mask. N-type impurity ions such as are implanted into the portion of the single crystal silicon substrate 1 under the gate oxide film 2 except the tail portions 9c of the diffusion layers 9a and 9b. MOS transistors are manufactured by forming certain n ⁺ type diffusion layers 17a and 17b. That is, the low impurity concentration diffusion layer 9
The a and 9b are formed by performing ion implantation before the spacer 14 is formed, and the high impurity concentration diffusion layer 17 is formed.
The a and 17b are formed by performing ion implantation after forming the spacer 14.

[0005]

By the way, as the miniaturization of elements progresses along with the progress of LSI technology, it is important to suppress the short channel effect in MOS transistors and prevent punch through. . It is known that reducing the junction depth of the diffusion layer is effective in solving this problem. However, in the impurity ion implantation performed to form the diffusion layer, a damaged layer due to the ion implantation is formed in the impurity-implanted region. The junction of the impurity diffusion layer becomes deep due to the large spread and the tail portion of the impurity injection region after the impurity injection deeply spreads to the single crystal silicon substrate. There is a drawback that it is difficult to prevent the through phenomenon.

The present invention has been made in view of the above circumstances, and an object thereof is to perform a heat treatment on an impurity region of a silicon substrate and diffuse the impurity into a non-impurity region to form a shallow junction. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can be formed.

A method of manufacturing a semiconductor device according to a first aspect of the invention is characterized in that an impurity region of a silicon substrate is heat-treated to diffuse the impurity into a non-impurity region.

A method of manufacturing a semiconductor device according to a second aspect of the present invention is a method of manufacturing a semiconductor device having an impurity diffusion layer below the surface of a single crystal silicon substrate, wherein the surface of the single crystal silicon substrate extends over a required depth. The step of amorphizing, the step of implanting impurities into the single crystal silicon substrate including the other part except the part of the amorphized part, the single crystal silicon substrate subjected to the heat treatment, Solid phase growth for repairing the crystalline portion, and diffusing the implanted impurities into a region of the amorphous portion where the impurities have not been implanted.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a gate electrode is provided on a surface of a single crystal silicon substrate with a gate oxide film interposed between the gate electrode and the single crystal silicon substrate below the gate oxide film. In a method of manufacturing a semiconductor device including a MOS transistor in which impurity diffusion layers forming source and drain regions are formed on both sides of the gate electrode, ion implantation is performed on both sides of the gate electrode from a surface side of a single crystal silicon substrate. And then amorphizing the single crystal silicon to a predetermined depth, and impurities are added to the single crystal silicon substrate including the other portion except the end of the amorphized portion facing under the gate oxide film. The step of implanting and performing a heat treatment on the single crystal silicon substrate to perform solid phase growth to restore the amorphous portion, and to implant the implanted impurities into the amorphous state. Characterized in that it comprises a step of diffusing into the opposite ends of the parts.

[0010]

In the first aspect of the present invention, the impurity diffusion region is controlled by heat-treating the impurity region of the silicon substrate to diffuse the impurity into the non-impurity region, and the impurity diffusion layer having a shallow junction depth is controlled. Can be formed.

According to the second aspect of the present invention, a portion under the surface of the single crystal silicon substrate is thinly made amorphous, and impurities are ion-implanted into other portions except for a portion of the amorphous portions. The impurity diffusion region was the amorphous portion by diffusing the impurity into the portion of the amorphous portion where the impurity was not ion-implanted by the heat treatment during the solid phase growth of the crystalline portion. It is possible to form an impurity diffusion layer having an extremely shallow junction depth by limiting the content within the range.

According to the third aspect of the invention, the junction depth can be made shallow by making the opposite ends of the impurity diffusion layers in the single crystal silicon substrate under the gate electrode face only in the amorphous portions. Thus, it is possible to suppress the short channel effect and prevent punch through.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments.

(Embodiment 1) FIG. 1 shows a single embodiment of the present invention.
FIG. 6 is a cross-sectional structure diagram showing an outline of a manufacturing process when applied to manufacturing an n-type MOS transistor having an S / D (source / drain) structure.

First, as shown in FIG. 1A, the surface of the single crystal silicon substrate 1 is thermally oxidized to form a gate oxide film 2 on the surface of the single crystal silicon substrate 1. Then, a polycrystalline silicon film having a thickness of 2000 Å is formed on the surface of the gate oxide film 2 by a CVD method, and then a silicon oxide film having a thickness of 2500 is formed.
Å Accumulate. Then, the gate electrode 3 made of polycrystalline silicon and the silicon oxide film 4 are patterned and formed in a laminated state by a photolithography process.

Next, as shown in FIG. 1B, from the front surface side of the single crystal silicon substrate 1, with the silicon oxide film 4 as a mask, Si ions, Ge ions, or SiCl, SiC.
Ion 5 such as l ₂ and SiCl ₃ is implanted to form a gate electrode 3
On both sides of the region where is formed, and below the gate oxide film 2 in the single crystal silicon substrate 1, amorphization is performed to a required thickness to form 6a and 6b. The tail portions 6c and 6c, which are both ends of the amorphous portions 6a and 6b, extend below the gate electrode 3 and face each other with a predetermined gap therebetween.

Then, as shown in FIG. 1C, SiO
A spacer 7 having a required thickness is formed on the side peripheral surface of the gate electrode 3 by depositing ₂ and anisotropic etching, and then the silicon oxide film 4 and the spacer 7 are used as a mask to implant an n-type impurity ion 8. I do. As a result, the tail portions 6 of the amorphous portions 6a and 6b are formed on both sides of the gate electrode 3.
Single crystal silicon substrate 1 including other parts except c and 6c
Then, the diffusion layers 9a and 9b forming the source and the drain are formed over a range deeper than the amorphous portions 6a and 6b.

In order to repair the damaged portion due to ion implantation, heating is performed at a low temperature of several hundreds of degrees Celsius, and the single crystal is recovered by solid phase growth. At this time, the ion-implanted impurities diffuse into the tail portions 6c and 6c of the amorphous portions 6a and 6a and into the single crystal silicon in the single crystal silicon substrate 1, but do not diffuse into the tail portions 6c and 6c. Since it progresses faster than the diffusion into the single crystal silicon, by stopping the heat treatment at the time when the diffusion into the tail portions 6c, 6c is completed, it is possible to prevent the diffusion of impurities deeper into the single crystal silicon. Becomes As a result, as shown in FIG. 1D, diffusion layers 10a and 10b having extremely shallow tail portions 10c and 10c are formed below the gate electrode 3 with the gate oxide film 2 therebetween. After that, RTA (Rapid Therma
l Annealing) to perform activation.

In the first embodiment, the amorphous portions 6a and 6b are formed below the gate oxide film of the silicon substrate 1 so that the tail portions 6c thereof extend below the gate electrode 3, and the amorphous portions are formed. By diffusing the ion-implanted impurities in the amorphous portions 6a and 6b in the heat treatment process for single-crystallizing the high-quality portions 6a and 6b by solid-phase growth, the tail portions 10c and 10c having an extremely shallow junction depth are formed. Diffusion layers 10a, 1 having
0b can be formed.

(Embodiment 2) In Embodiment 2, the impurity concentration of the diffusion layer can be adjusted more appropriately by implanting the impurity twice. FIG. 2 is a sectional structural view showing the outline of the manufacturing process when the present invention is applied to the manufacture of an n-type MOS transistor having an LDD structure.

2A to 2 in the second embodiment.
The step shown in (d) is substantially the same as the step shown in to in Example 1. Therefore, Example 2 is the same as Example 1 except that
Further, it is substantially the same as the step shown in FIG. 2E is added, and the corresponding parts are given the same numbers and their explanations are omitted.

Same as Example 1 Same as Example 1 Same as Example 1 Same as Example 1 As shown in FIG. 2E, the silicon oxide film 4 and the spacer 7 are used as masks from the front surface side of the single crystal silicon substrate 1. By implanting the n-type impurity ions 11, the n ⁺ -type diffusion layers 12a and 12b, which are high-concentration impurity diffusion layers, are formed so as to substantially overlap with other portions of the diffusion layers 10a and 10b except the tail portion 10c. Form. Such Example 2
In that case, the impurity concentration can be set more appropriately by ion implantation of impurities as shown in FIG.

(Embodiment 3) In this embodiment 3, the distance between the diffusion layers can be arbitrarily set by changing the width of the spacer. FIG. 3 illustrates the present invention in an LDD structure MO.
FIG. 9 is a cross-sectional structure diagram showing an outline of the manufacturing process of Example 3 when applied to the manufacture of an S transistor.

The steps shown in FIGS. 3A to 3D are substantially the same as those of the first embodiment. Therefore, the third embodiment is substantially the same as the process of the first embodiment with the step shown in FIG. 3E added, and the corresponding parts will be denoted by the same reference numerals and description thereof will be omitted.

Same as Example 1 Same as Example 1 Same as Example 1 Same as Example 1 As shown in FIG. 3E, the side peripheral surface of the gate electrode 3 is covered by deposition of SiO ₂ and anisotropic etching. Spacer 7
After forming the spacer 14 with an increased thickness, n-type impurity ions 11 are implanted to form n ⁺ diffusion layers 12a and 12b which are high-concentration impurity diffusion layers. In the third embodiment as described above, by appropriately setting the width of the spacer 14, the distance between the diffusion layers 12a and 12b can be appropriately set and controlled.

(Embodiment 4) In Embodiment 4, Embodiments 1 to 1
This is a process in which the process of forming the spacers 7 and 14 used in 3 is omitted. FIG. 4 shows the present invention as a single S / D.
FIG. 9 is a cross-sectional structure diagram showing an outline of the manufacturing process of Example 4 showing the case of being applied to the manufacture of an n-type MOS transistor of (source / drain) structure.

Same as Example 1 Subsequently, as shown in FIG. 4B, a silicon oxide film 4 is formed.
Are used as masks to inject ions 5 such as Si ions and SiCl ions in a non-perpendicular state with respect to the surface of the single crystal silicon substrate 1, both sides of the region where the gate electrode 3 is formed, and the single crystal silicon substrate. Gate oxide film 2 in 1
The lower part of is amorphized to a required thickness to form 6a and 6b. These amorphous portions 6a and 6b are tail portions 6c which are both ends.
Extend below the gate electrode 3 and face each other with a predetermined gap therebetween.

Subsequently, as shown in FIG. 4C, n-type impurity ions 8 are implanted using the silicon oxide film 4 as a mask. By this, on both sides of the gate electrode 3,
The amorphous portion 6a is formed on the single crystal silicon substrate 1 including the portions other than the tail portions 6c and 6c of the amorphous portions 6a and 6b.
Diffusion layers 9a and 9b forming a source and a drain are formed over a range deeper than a and 6b.

The single crystal silicon substrate 1 is heated at a low temperature of several hundreds of degrees Celsius in order to repair the damage by ion implantation, and the single crystal is recovered by solid phase growth. At this time, the ion-implanted impurities are the tail portions 6c, 6 of the amorphous portions 6a, 6b.
c and into the single crystal silicon in the single crystal silicon substrate 1, but the diffusion into the tail portions 6c and 6c progresses faster than the diffusion into the single crystal silicon, and thus into the tail portions 6c and 6c. By stopping the heat treatment when the diffusion is completed, it is possible to prevent the impurities from diffusing deeper into the single crystal silicon. As a result, FIG. 4 (d)
As shown in FIG. 3, a diffusion layer 1 having extremely shallow tail portions 10c and 10c is formed under the gate electrode 3 with the gate oxide film 2 therebetween.
0a, 10b are formed. After that, high temperature, short time R
Activation processing is performed by TA (Rapid Thermal Annealing). In such Example 4, Examples 1-3
The step of forming the spacer 7 formed in step 2 is unnecessary,
Faster throughput time.

[0030]

According to the first aspect of the present invention, a diffusion layer having a shallow junction depth can be formed by heat-treating an impurity region and diffusing the impurity into a non-impurity region, thereby controlling the short channel effect. , The punch-through phenomenon prevention function can be enhanced.

In the second and third aspects of the invention, the single crystal silicon substrate is amorphized to a required depth from the surface thereof, and impurities are implanted into a portion other than a part of the amorphized portion, It is possible to keep the impurities in the amorphous portion by diffusing the impurities into a region of the amorphous portion where the impurities have not been implanted by performing heat treatment to cause solid phase growth in the amorphous portion. It becomes possible, the junction depth can be limited to the amorphous part, and the junction depth can be made extremely shallow.
Similarly, the control of the short channel effect and the function of preventing the punch-through phenomenon can be enhanced.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a manufacturing process when the present invention is applied to manufacturing a MOS transistor having a single S / D structure.

FIG. 2 is a sectional structural view showing a manufacturing process when the present invention is applied to manufacturing an LDD-structure MOS transistor.

FIG. 3 is a cross-sectional structure diagram showing a manufacturing process when the present invention is applied to manufacture of a MOS transistor having an LDD structure.

FIG. 4 is a sectional structural view showing a manufacturing process when the present invention is applied to manufacturing a MOS transistor having a single S / D structure.

FIG. 5 is a cross-sectional structure diagram showing a conventional LDD structure MOS transistor manufacturing process.

[Description of Reference Signs] 1 single crystal silicon substrate 2 gate oxide film 3 gate electrode 4 silicon oxide film 6a, 6b amorphous portion 6c tail portion 9a, 9b diffusion layer 10a, 10b diffusion layer

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H01L 29/78 301 L

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, which comprises subjecting an impurity region of a silicon substrate to a heat treatment to diffuse the impurity into a non-impurity region. 2. A method of manufacturing a semiconductor device having an impurity diffusion layer below the surface of a single crystal silicon substrate, the step of amorphizing to a required depth from the surface of the single crystal silicon substrate, and the amorphous A step of implanting an impurity into the single crystal silicon substrate including a part other than a part of the qualitative part, a heat treatment to the single crystal silicon substrate, and a solid phase growth for repairing the amorphous part; And a step of diffusing the implanted impurities into a region of the amorphous portion where the impurities are not implanted. 3. A single crystal silicon substrate is provided with a gate electrode on a surface thereof with a gate oxide film therebetween, and source and drain regions are formed on both sides of the gate electrode in the single crystal silicon substrate below the gate oxide film. In a method of manufacturing a semiconductor device including a MOS transistor in which an impurity diffusion layer is formed, ion implantation is performed on both sides of the gate electrode from the front surface side of a single crystal silicon substrate to remove single crystal silicon to a predetermined depth. A step of crystallizing, a step of implanting impurities into the single crystal silicon substrate including other portions except the end portions of the amorphized portions facing each other under the gate oxide film, A heat treatment is performed to perform solid phase growth to repair the amorphous portion, and the implanted impurities are diffused into opposite ends of the amorphous portion. A method for manufacturing a semiconductor device, which comprises: