JPH0312098A - Ram test system - Google Patents

Abstract

PURPOSE:To easily perform a test for a RAM circuit by effectively using data in a ROM circuit at an integrated circuit of large scale. CONSTITUTION:A RAM test instruction positive signal 101 from a RAM test instruction circuit 5 is supplied to a selection circuit 6, a count control circuit 7, and a voltage fluctuation instruction circuit 9, and a RAM test instruction negative signal 102 is supplied to the selection circuit 6. A data signal 103 for RAM in an ordinary operation is inputted to the selection circuit 6, and a RAM test count signal 104 in a RAM test is inputted to the count control part 7, and an address count signal is supplied to a RAM address register circuit 3 and a ROM address register circuit 4. A ROM address register signal 106 is supplied to the ROM circuit 1, and a RAM address signal 107 to the RAM circuit 2, respectively. A RAM write data signal 108 is supplied to the circuit 2, and a ROM output signal 109 to the selection circuit 6 and a comparator 8. A voltage fluctuation instruction signal 113 from the voltage fluctuation instruction circuit 9 is supplied to a power source for RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a RAM testing method, and particularly to a RAM testing method in a large-scale integrated circuit containing both a RAM circuit and a ROM circuit.

[Conventional technology]

Conventionally, this type of RAM test method has been used to test the RAM while keeping the DC voltage value supplied to the RAM circuit set to a normal value.
A method is used in which addresses and data are respectively supplied to the address register and data supply circuit for the integrated circuit through internal circuits of the integrated circuit, or a method in which addresses and data are directly supplied from external terminals of the integrated circuit.

[Problem to be solved by the invention]

The conventional RAM test method described above is a method in which addresses and data are supplied via the internal circuit of an integrated circuit.
The number of logic stages required for setting is deep, which is complicated, and the method of directly supplying addresses and data from external terminals requires a large number of terminals for testing, making it difficult to secure terminals. The disadvantage is that there are many.

Furthermore, since the DC voltage value supplied during the RAM test remains a normal value, there is a drawback that there is no guarantee that normal operation will be performed against voltage fluctuations.

[Means to solve the problem]

The RAM test method of the present invention uses a RAM test instruction circuit for instructing a RAM test, a ROM address register circuit for supplying an address for the ROM circuit, and a RAM test instruction circuit for instructing a RAM test in an integrated circuit incorporating a ROM circuit and a RAM circuit. a RAM address register circuit that supplies an address;
a selection circuit that switches an output signal of the ROM circuit to a data input of the RAM circuit when the RAM test instruction circuit instructs a RAM test; and a ROM address register circuit when the RAM test instruction circuit instructs a RAM test. a count control circuit that sequentially counts up each of the RAM address register circuit and the RAM address register circuit at the same time; a comparison circuit that detects a match between the output signal of the RAM circuit and the output signal of the ROM circuit when reading from the RAM circuit; and a voltage fluctuation instruction circuit for instructing at least a DC voltage value to be supplied to the RAM circuit when the test instruction circuit instructs a RAM test.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which an integrated circuit includes a ROM circuit 1, a RAM circuit 2, a ROM address register circuit 3, a RAM address register circuit 4, a RAM test instruction circuit 5, a selection circuit 6, and a count circuit. A control circuit 7, a comparator circuit 8 and a voltage variation instruction circuit 9 are shown. R
RAM test instruction positive signal 1 from AM test instruction circuit 5
01 is given to the selection circuit 6, count control circuit 7 and voltage fluctuation instruction circuit 9, and the RAM test instruction negative signal 102
is given to the selection circuit 6. The RAM data signal 103 during normal operation is input to the selection circuit 6, the RAM test count signal 104 during RAM test is input to the count control section 7, and the address count signal from the count control section 7 is input to the ROM address register circuit 3. and RAM
It is given to the address register circuit 4. Also ROM
The ROM address register output signal 106 from the address register circuit 3 is sent to the ROM circuit 1, and the RAM address register output signal 106 from the ROM address register circuit 4 is sent to the ROM circuit 1.
The RAM circuits 2 and 2 are respectively provided. 1+ RAM write data 01 from selection circuit 6 is applied to RAM circuit 2, and ROM output signal 109 from the ROM circuit is applied to selection circuit 6, comparison circuit 8, and internal circuits of the integrated circuit. Yet another RA
The M write signal 111 is given to the RAM circuit 2, and the RAM
The RAM output signal 110 from the circuit 2 is given to the comparator circuit 8 and the internal circuit of the integrated circuit, the error signal 112 is given from the comparator circuit 8 to the internal circuit of the integrated circuit, and the voltage from the voltage fluctuation instruction circuit 9 The configuration is such that the fluctuation instruction signal 113 is provided in the internal circuit of the integrated circuit and is supplied to the power supply for the RAM.

In the above configuration, during normal operation, the RAM test instruction circuit 5 is reset, the RAM test instruction Masaura No. 101 is @0'', and the RAM test instruction negative signal 102 is 1''.
It becomes. Therefore, the RAM data signal 103
is supplied to the RAM circuit 21C via the selection circuit 6. 9. Since the count control circuit 7 also operates only during the RAM test, the address count signal 105 is always 0°, and the ROM address register circuit 3 and the RAM address register circuit 4 operate independently.At this time, of course, Voltage fluctuation indicator port [9 is reset and RAM
The DC voltage value supplied to the circuit 2 remains at the normal value.

When performing a RAM test, the RAM test instruction circuit 5 is set to the set state, the RAM test instruction positive signal 101 becomes ``1'', and the RAM test instruction negative signal 102 becomes 0''. , the voltage variation instruction circuit 8 is set by the RAM test instruction positive signal 101, and a voltage value instruction is issued by the voltage variation instruction signal 113 to change the DC voltage value.The data written to the RAM circuit 2 is written in the ROM output signal. 109 is selected by the selection circuit 6 and supplied to the RAM circuit 2. Also, the count control circuit 7 sends out the RAM test count signal 105, and the RO
The M address register circuit 3 and the RAM address register circuit 4 are configured to simultaneously add 1 for each signal 105. By this addition, the ROM circuit and R
Since a common address is given to the AM circuit 2 at the same time, the ROM output signal 10 read on the ROM circuit
9 is RAM write signal 1 to the same address of RAM circuit 2
11. Then, the data of the ROM circuit 1 is continued to be written to all addresses of the RAM circuit 2 by sequentially adding l to the ROM address register circuit 3 and the RAM address register circuit 4, and
When the highest address is reached, the write operation is stopped.

When the write operation is completed in this way, in order to confirm the validity of the write data, the data is read from the RAM circuit 2, and the comparison circuit 8 compares this data with the ROM output signal 109 to check whether they match. However, if a mismatch occurs, an error signal 112 is output. Note that during a read operation, the RAM write signal 111 is not generated, only the address count signal 105 is generated, and the addition operation of the ROM address register circuit 3 and RAM address register circuit 4 is performed until the contents of all addresses in the RAM circuit 2 are read. Continue sequentially until the

In this way, in large scale integrated circuits in which both ROM and RAM circuits are housed, -numerical kRAM
By making effective use of the data written in the ROM circuit, where the number of logical stages of addresses and data supplied to the circuit is deep and cannot be easily supplied,
It becomes easier to supply data and test the RAM circuit.

In addition, by setting the DC voltage value to conditions that are more severe than during normal operation during RAM testing, it becomes possible to detect RAM elements that are starting to fail or are deteriorating at an early stage. This has the effect of improving reliability and preventing an increase in unnecessary external terminals for RAM circuit testing.

〔Effect of the invention〕

As explained above, the present invention provides a %RAM test instruction circuit and an RO
A ROM address register circuit that supplies the address of the M circuit, a RAM address register circuit that supplies the address of the RAM circuit, and a switching circuit that supplies the output signal of the ROM circuit as a data input signal of the RAM circuit during a RAM circuit test. , ROM address register circuit and RA
A count control circuit that simultaneously controls the addition of the M address register circuit, a comparison circuit that detects a match between the RAM circuit read data and the ROM output signal, and a KR during RAM test.
By having a voltage fluctuation instruction circuit that instructs fluctuations in the DC voltage value supplied to the AM circuit, it is easy to supply data input signals to the RAM circuit when testing the RAM circuit, and furthermore, it is possible to easily supply data input signals to the RAM circuit when testing the RAM circuit. The KL makes it easy to confirm the validity of the KL, improves the reliability of the RAM circuit, improves the failure detection rate of the RAM circuit, and prevents the increase in external terminals for testing purposes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. l...ROM circuit, 2...RAM circuit,
3...ROM address register circuit, 4...
...RAM address register circuit, 5...R
AM test instruction circuit, 6...Selection circuit, 7...
... Count control circuit, 8... Comparison circuit,
9... Voltage fluctuation indication circuit.

Claims (1)

[Claims] In an integrated circuit that includes a ROM circuit and a RAM circuit, a RAM test instruction circuit that instructs a RAM test, and an R
A ROM address register circuit that supplies the address of the OM circuit, a RAM address register circuit that supplies the address of the RAM circuit, and a RAM test instruction circuit that supplies the address of the RAM circuit.
a selection circuit that switches an output signal of the ROM circuit to a data input of the RAM circuit when a test is instructed;
A count control circuit that sequentially counts up each of the ROM address register circuit and the RAM address register circuit simultaneously when the AM test instruction circuit instructs a RAM test;
A comparison circuit for detecting a match between the output signal of the M circuit and the output signal of the ROM circuit, and a comparison circuit for detecting a match between the output signal of the M circuit and the output signal of the ROM circuit;
A RAM test method comprising: a voltage fluctuation instruction circuit that indicates a DC voltage value that is supplied to at least the RAM circuit when an AM test is instructed.