JPH02143351A - Parity inspection circuit - Google Patents

Abstract

PURPOSE:To simplify a work in an inspection process and to improve efficiency by inverse-controlling parity bit data in accordance with the output condition of a flip-flop circuit and generating a parity error. CONSTITUTION:When the function operating test of a parity error detection circuit 4 is executed at the time of reading, a program for test mode setting F/F circuit control 7 is executed by an external command (working instruction), and an F/F circuit 6 for test mode setting is made into a set state. Therefore, '1' is outputted to either end of the input terminal of an inverting circuit from the F/F circuit 6, the parity bit data inputted into the other input terminal is inverted, and outputted to the parity error detection circuit 4. Consequently, the parity error detection circuit 4 detects an error as error data, since the number of '1' is an odd number. In this case, if the error detection is not executed, the parity detection circuit 4 is abnormal. Thus, the parity test can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a random access memory circuit (hereinafter referred to as rRA).
It is called "M circuit". The present invention relates to a parity check circuit that detects whether or not there is an error in data read from a RAM circuit in a system that requires reliable access to a RAM circuit.

[Prior Art] Generally, in systems that require reliable access to a RAM circuit, a code is constructed by adding 1 redundant bit to n-1 bits of write data, and Give redundant bits (parity bits) so that the total number of “I” is even (or odd),
A parity check is performed to detect errors in the read data by checking whether the number of bits included in the data read from the RAM circuit is even (or odd). Checking of the read data is performed by a parity error detection circuit provided at the output stage of the RAM circuit.

Conventionally, when testing the functional operation of this parity error detection circuit, noise is injected into the parity error detection circuit part during a certain system operation to generate an error state, and the parity error detection circuit is tested. ,
In addition, when setting the test mode by hardware settings, an error parity bit generation circuit that generates an error state for certain pattern data is used. Relatively many methods are also used to generate error conditions.

[Problem to be solved by the invention]

However, with the conventional noise injection method described above, it is difficult to determine the timing of the occurrence of an error state, and since the state differs each time a test is performed, it is necessary to observe waveforms using a synchroscope, which is time-consuming. It has some inconveniences.

In addition, in the conventional method using hardware settings described above, when setting the test mode, an error parity pit generation circuit that causes an error state for certain pattern data is used, so it is necessary to generate an error in advance. This has the inconvenience of requiring data to be set.

[Purpose of the invention]

An object of the present invention is to improve the inconveniences of the conventional example, and in particular, to simplify the work and improve efficiency in the parity inspection process, and to improve the reliability of system inspection. The purpose is to provide a test circuit.

[Means to solve the problem]

In the present invention, a first RAM circuit inputs write data, a parity pinto generation circuit inputs the write data and generates parity bit data for detecting errors in the write data, and outputs from the parity bit generation circuit. A second RAM that inputs parity bit data.
It has a circuit. Also, these first. 2nd RAM
A parity error detection circuit is provided which inputs read data and parity bit data output from the circuit when reading the memory, and detects the presence or absence of a parity error based on the input read data and parity bit data. An inverting circuit is interposed between the second RAM circuit and the parity error detection circuit to invert the parity bit data output from the second RAM circuit when reading out when the test mode is set. The input stage is equipped with a programmable flip-flop circuit for setting test modes. This aims to achieve the above-mentioned objective.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

The embodiment shown in FIG. 1 is a data focusing RAM circuit 1 serving as a first RAM circuit into which write data is input.
a parity bit generation circuit 2 which inputs write data and generates parity bit data for detecting errors in the write data; and a second RA which inputs parity bit data output from the parity bit generation circuit 2.
A parity bit RAM circuit 3 is provided as an M circuit.

Of these, the parity pit generation circuit 2 constructs a code in which 1 bit of parity bit is added to the write data of n-1 bits, and each code is generated so that the total number of "1"s among the n bits is an even number. A parity bit of 0°° or °゛1' is generated in accordance with the input data.

A parity error detection circuit 4 is also provided at the output stage of the data bit RAM circuit 1. Between the parity error detection circuit 4 and the parity bit RAM circuit 3, an inversion circuit 5 consisting of an Ex and OR circuit (Exclusi-veOR circuit) is interposed. Therefore, at the time of memory reading, the read data output from the data bit RAM circuit 1 is input to the parity error detection circuit 4, and at the same time, the parity bit data output from the parity bit RAM circuit 3 is input to the parity error detection circuit 4. The signal is input to a parity error detection circuit 4.

Further, at the input stage of the inverting circuit 5, a flip-flop circuit (F/F circuit) 6 for setting a test mode is provided. This F/F circuit 6 is set by a test mode setting F/F circuit control program 7 executed by an external command (work command) via a 10 board.
The reset state is controlled. When this F/F circuit 6 is in the set state, rH is applied to one input terminal of the inverting circuit 5.

Sends a level (high level) output signal “°1’°,
In the reset state, an output signal IIO11 of "L" level (low level) is output.

Next, the operation of the above embodiment will be explained.

During writing, write data is externally input to the data bit RAM circuitry and stored. This write data is also input to the parity bit generation circuit 2 at the same time. Upon input of this write data, the parity pit generation circuit 2 generates parity bit data that gives even parity to the write data, and outputs it to the next stage parity bit RAM circuit 3. and,
This parity bit data is stored in the parity bit RAM.
It is stored in circuit 3.

On the other hand, when performing a functional operation test of the parity error detection circuit 4 during reading, the test mode setting F/F circuit control program 7 is executed by an external command (work command), and the test mode setting F/F circuit control program 7 is executed. /F circuit 6 is set. Therefore, 1''' is output from the F/F circuit 6 to one input terminal of the inversion circuit, and thereby the parity bit data input to the other input terminal is inverted and output to the parity error detection circuit 4. As a result, the parity error detection circuit 4 detects an error as error data (determines that one bit is incorrect) since the number of "1"s is an odd number.In this case, error detection must be performed. For example, parity error detection circuit 4
is considered abnormal.

On the other hand, when the functional operation test of the parity error detection circuit 4 is completed, the test mode setting F/F circuit control program 7 is executed by an external command (work command) to reset the F/F circuit 6. Make it. In this case, F
Since the output signal of the /F circuit 6 is "0", the parity bit data is not inverted, so as long as there is no error in the read data, no error is detected in normal operation.

In the above embodiment, as the inverting circuit, Ex, O
Although the case where the R circuit is used is illustrated, instead of this, Ex,
A NOR circuit may be used to set the test mode when the output of the F/F circuit is at the "L" level.

〔Effect of the invention〕

As described above, according to the present invention, the parity bit data output from the second RAM circuit when read is placed between the second RAM circuit that inputs the parity bit from the parity pit generation circuit and the parity error detection circuit. In addition to interposing an inverting circuit that inverts in a predetermined case,
Since a program-controllable test mode setting F/F circuit is provided at the input stage of this inverting circuit, it is possible to invert the parity bit data according to the F/F output state to generate a parity error. I can do it.

This eliminates the need for hardware settings during testing and allows errors to occur reliably at any address, simplifying work in the inspection process and improving efficiency. It is possible to provide an unprecedented parity check circuit that can improve the reliability of system checks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1... RAM circuit for data bits as a first RAM circuit, 2... Parity pit generation circuit, 3... RAM for parity bits as a second RAM circuit. Circuit, 4... Parity error detection circuit, 5... Inversion circuit, 6... F/F
circuit. Patent applicant: NEC Corporation Representative, Patent attorney: Isamu Takahashi

Claims (1)

[Claims] (1) a first random access memory circuit that inputs write data; a parity bit generation circuit that inputs the write data and generates parity bit data for detecting errors in the write data; a second random access memory circuit that receives parity bit data output from the bit generation circuit; and read data and parity bits that are output from the first and second random access memory circuits when reading the memory. a parity error detection circuit that inputs data and detects the presence or absence of a parity error based on the input data; the second random access memory circuit is provided between the second random access memory circuit and the parity error detection circuit; An inverting circuit is provided to invert the parity bit data output from the circuit when the test mode is set, and a programmable flip-flop circuit for setting the test mode is provided at the input stage of this inverting circuit. A parity check circuit featuring: