JPH03116934A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate an unstable main factor due to the roughness of the surface of an emitter, which is generated at the time of an etching work of a base lead-out electrode, and to contrive the improvement of the element characteristics of an element by a method wherein an SiO2 film on a base-emitter junction is overhung on a base region and is made to overlap with the base lead-out electrode. CONSTITUTION:A first polycrystalline silicon film for base lead-out electrode 7 forma tion use is grown in such a way as to cover the region of a base 5 and an oxide film 6 under a base electrode, an interlayer insulating oxide film 8 is applied in such a way as to cover this first polycrystalline silicon film and this film 8 and the first polycrystalline silicon film for base lead-out electrode 7 formation use are opened in the width of the region of an emitter 11. An emitter sidewall oxide film 9 is applied on the whole surface of a semiconductor substrate 1, a second polycrystalline silicon film for emitter electrode 10 formation use is applied in such a way as to cover the films 6 and 9 and an impurity is diffused in the substrate 1 by a heat treatment to form the emitter 11. Thereby, damage and contamination are hardly generated, the Si substrate is never bored, element characteristics are stabilized and the yield of a product is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device including a bipolar transistor.

The aim is to eliminate the instability of device characteristics caused by the control technology of the base extraction electrode.

In a method of manufacturing a semiconductor device including a bipolar transistor, an oxide film under a base electrode is formed in a base formation region of a bipolar transistor, and impurities are implanted into the base region by ion implantation.

a step of forming a base by heat treatment; a step of selectively patterning the oxide film under the base electrode to a smaller size than the base forming region; 1st for electrode formation
a step of growing a polycrystalline silicon film, and then covering the first polycrystalline silicon film for forming the base extraction electrode with an interlayer insulating oxide film, the interlayer insulating oxide film, and
A process of opening the polycrystalline silicon film for forming the base extraction electrode to the width of the emitter region, coating the entire surface of the substrate with an emitter sidewall oxide film, and anisotropic etching.
A process of forming an emitter sidewall oxide film, covering the oxide film under the base electrode and the emitter sidewall oxide film, covering the second polycrystalline silicon film for forming the emitter electrode, and removing impurities from the semiconductor substrate by heat treatment. The method is configured to include the steps of forming an emitter by diffusing the polycrystalline silicon film inward, and patterning the second polycrystalline silicon film for forming the emitter electrode to form the emitter electrode.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device including a bipolar transistor.

In recent years, with the progress of miniaturization of semiconductor integrated circuit devices including bipolar transistors, higher performance is required.

In particular, it is essential to eliminate instability in device characteristics, and new technology needs to be developed in the process.

[Conventional technology]

FIG. 3 is an explanatory diagram of a conventional example.

In the figure, 15 is an St substrate, 16 is an n buried diffusion layer, 17 is a collector, 18 is an element isolation 5iOz film, and 19
20 is a base extraction electrode, 21 is an interlayer insulating 5iOz film, 22 is an emitter sidewall Si0g film, 23 is an emitter electrode, 24 is an emitter, and 25 is a surface protection 5iOz film.

26 is an emitter external electrode, and 27 is a base external electrode.

Conventionally, polycrystalline silicon films (polyS
When etching the i-film), its opening was exposed to RIH, and since the materials were the same (poly-Si and St), it was difficult to obtain a selectivity of 1.

For this reason, the emitter region is exposed to the RIB, which is likely to cause damage and contamination, which leads to an increase in the base recombination current at the EB junction and a decrease in +11FE.

In addition, since the 1 selection ratio cannot be obtained sufficiently, the S of the emitter section
i is dug, which causes an increase in base resistance and a decrease in collector-emitter breakdown voltage.

[Problem to be solved by the invention]

Therefore, in the conventional process, the device characteristics depend largely on the processing technology of the base-drawn poly-Si electrode, and this processing technology is difficult to control because the etching of the poly-Si must be stopped on the Si. was unstable.

As a result, product yield has decreased and costs have increased.

The present invention is provided for the purpose of eliminating instability in etching control of poly-Si electrodes and stabilizing device characteristics.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, l is a semiconductor substrate, 2 is n' buried diffusion layer, and 3 is a semiconductor substrate.
is a collector, 4 is an element isolation oxide film, 5 is a base, 6 is an oxide film under the base electrode, 7 is a base extraction electrode, 8 is an interlayer insulation oxide film, 9 is an emitter sidewall oxide film, 10
is an emitter electrode, 11 is an emitter, 12 is a surface protective oxide film, 13 is an emitter external electrode, and 14 is a base external electrode.

As shown in FIG. 1, the present invention is a method for manufacturing a semiconductor device including a bipolar element, in which an oxide film 6 under a base electrode is formed in a base 5 formation region of a bipolar transistor, and impurities are implanted into the base by an ion implantation method. a step of implanting into the base 5 region and performing heat treatment to form the base 5; a step of selectively patterning the base electrode lower oxide film 6 to be smaller than the base 5 forming region; A first polycrystalline silicon film for forming the base extraction electrode 7 is grown covering the lower electrode oxide film 6, and then a two-layer interlayer is grown covering the first polycrystalline silicon film for forming the base extraction electrode 7. A step of covering the insulating oxide film 8, and the interlayer insulating oxide film 8.

The step of opening the polycrystalline silicon film for forming the base extraction electrode 7 to the width of the emitter 11 region, coating the entire surface of the substrate with an emitter sidewall oxide film, and forming the emitter sidewall oxide film 9 by anisotropic etching. A second polycrystalline silicon film for forming the emitter electrode 10 is coated over the base electrode lower oxide film 6 and the emitter sidewall oxide film 9, and impurities are diffused into the semiconductor substrate 1 by heat treatment. This is accomplished by including the steps of forming an emitter and forming the emitter electrode 10 by patterning the second polycrystalline silicon film for forming the emitter electrode IO.

The base electrode lower oxide film 6 serves as a stopper during etching of the first poly-Si film for forming the base extraction electrode 7, and at the same time protects the surface of the emitter 11 to prevent digging and roughening of the emitter surface. .

Even in the conventional process, an oxide film is present, and the presence of this oxide film in the base region does not increase the number of steps.

[Effect]

When processing the poly-Si film of the base extraction electrode, there is an oxide film on the surface of the emitter region, so the emitter region is
Not exposed to IE.

Therefore, damage and contamination are less likely to occur (and the Si substrate is not dug. Therefore, the device characteristics are stable.

Product yield is improved.

〔Example〕

FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps.

In the figure, l is a Si substrate, 2 is n' buried diffusion layer, 2'
is the buried diffusion layer p, and 3 is the collector.

3 is an epitaxial b, 5 is a base, 6 is a Sing film under the base electrode, 7 is a base extraction electrode, 8 is an interlayer insulation SiO□ film, 9 is an emitter sidewall S30g film, 1O is an emitter electrode, 11
1 is an emitter, 12 is a surface protection SiO□ film, 13 is an emitter external electrode, and 14 is a base external electrode.

As shown in Figure 2(a), p-type 10ΩcIIl Si
By ion implantation, arsenic ions (As"
) at an accelerating voltage of 70 keV and a dose of 14 x 10”/cm.
2 to form an n buried diffusion layer 2,
Boron ions (
Acceleration voltage 40keV, dose ff15X10''
/cI112 implantation conditions to form a P buried diffusion layer 2'.
form. Thereafter, a thermal oxide film (not shown) was coated with 5 (10 people) and heated at 1,150'C in a nitrogen (N2) atmosphere.
After heat treatment for 90 minutes, the oxide film on one surface is removed by etching.

As shown in FIG. 2(b), 1,1 (10”
51M3' is epitaxially grown using C to a thickness of 1.5 μm.

As shown in FIG. 2(C), phosphorus ions (P) are implanted into the diffusion region of the collector 3 at an accelerating voltage of 18 cm by ion implantation.
It was implanted under the conditions of 0 keV and a dose of 3 x 10"/cm", and also on the p buried diffusion layer.

Boron ions (B゛) are accelerated by ion implantation method.
Implantation is performed under the conditions of 180 keV and a dose of 2 x 10'2/cm''. Thereafter, heat treatment is performed at 1,050°C for 180 minutes.

As shown in Figure 2(d), 8(1
Two 5in2 films (not shown) were heated at 0°C (10 people, Si3
N, the film was heated by 5 (10 people), then selectively patterned and oxidized with hydrochloric acid at 950°C, 5,
(100 element isolation SiO□ films 4 are formed.

From now on, FIG. 2 shows only the portion of the base region directly related to the present invention in an enlarged manner.

As shown in FIG. 2(e), 5i below the base electrode of the present invention
2 (10 people's 5
Form an i02 film. Then, by ion implantation method.

Accelerating boron ions (B) into the diffusion region of the base 5 at a voltage of 2
The implantation is performed under conditions of 5 keV and a dose of 12XIO''/cm2.

As shown in FIG.
is patterned so as to remain in the region of the base 5, larger than the region of the emitter 11. For example, the emitter width is 0.8
In the case of .mu.m, the width of the 5 in 2 film 6 that remains is about 1.6 .mu.m.

Subsequently, by CVD method, a poly-Si film 2, (100 people 9 interlayer insulating Sing film 8) was formed as the base extraction electrode 7.
A Si0g film was formed by sequentially stacking 3 (100) layers.

The formation region of the emitter 11 and other areas are patterned and opened.

As shown in FIG. 2(g), a 5in2 film for forming the emitter sidewall 5iOz film 9 was formed into 8.
(Coat 3, (100 thick at 10"C).

As shown in Fig. 2 (h), the emitter side wall S
An iO□ film 9 is formed on the side wall of the opening window of the emitter 11 by anisotropic etching using RIH.

Next, a poly-Si film for emitter doping and for forming the emitter electrode 10 is formed by CVD to a thickness of 6 (1,5) at 10°C, and patterned except for the emitter 11 region to form the emitter electrode. Form IO.

Further, 9, one arsenic ion (As') is implanted into the opening window of the collector contact (not shown) by an ion implantation method under the conditions of an acceleration voltage of 50 keV and a dose of ff11×10"7 cm".

Next, annealing is performed at 950°C for 10 minutes in +J to form the emitter 10, and also form a P'' layer for base contact in the region of base 5, and also form an N'' layer for collector contact. to form.

Finally, as shown in Figure 1, CV
By method D, a surface protective 5in2 film 12 was formed at 8 (10°C) to a thickness of 2. (100 people), and then a PSG film (not shown) was formed at 4 (10°C) to a thickness of 6. (100 people). A window is opened for each of the emitter, base, and collector electrodes, and an Al film for the external electrode is coated by sputtering to a thickness of 8.5 mm (100 mm), and then patterned to form each external electrode to form the semiconductor device. Completes bipolar transistor device.

[Effects of the Invention] As explained above, according to the present invention, the 5i02 film on the base-emitter junction is extended to the base region.

By overlapping with the base extraction electrode,
It is possible to eliminate instability factors caused by roughness on the emitter surface that occurs during etching of the base extraction electrode, which greatly contributes to improving the characteristics of such semiconductor devices and increasing product yields.

[Brief explanation of drawings]

FIG. 1 is an illustration of the principle of the present invention. FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps. Figure 3 is an explanatory diagram of the conventional example. It is. In the figure 1 is a semiconductor substrate, 2 is an n buried diffusion layer. 2' is a P buried diffusion layer, and 3 is a collector. 3゛ is an epitaxial Si layer. 4 is an element isolation oxide film, and 5 is a base. 6 is the oxide film under the base electrode. 7 is the base extraction electrode. 8 is an interlayer insulating oxide film. 9 is the emitter sidewall oxide film. 10 is an emitter electrode, 11 is an emitter. 12 is a surface protective oxide film, and 13 is an emitter external electrode. 14 is the base external electrode − CLI/’)

Claims (1)

[Claims] In a method of manufacturing a semiconductor device including a bipolar transistor, a base electrode under-oxide film (6) is formed in a base (5) formation region of a bipolar transistor, and impurities are added to the base (5) by ion implantation. ) region and perform heat treatment to form a base (5); a step of selectively patterning an oxide film (6) under the base electrode smaller than the base (5) forming region; A first polycrystalline silicon film for forming a base extraction electrode (7) is grown to cover the base (5) region and the base electrode lower oxide film (6), and then the base extraction electrode (7) is grown.
), covering the first polycrystalline silicon film for formation with an interlayer insulating oxide film (8);
) and the step of opening the polycrystalline silicon film for forming the base lead-out electrode (7) to the width of the emitter (11) region, coating the entire surface of the substrate with an emitter sidewall oxide film, and anisotropically etching the emitter. A step of forming a sidewall oxide film (9), and a second polycrystalline silicon film for forming an emitter electrode (10) covering the base electrode lower oxide film (6) and the emitter sidewall oxide film (9). coating and diffusing impurities into the semiconductor substrate (1) by heat treatment to form an emitter; and patterning the second polycrystalline silicon film for forming the emitter electrode (10) to form the emitter electrode (10). 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.