JPH03113832U - - Google Patents
Info
- Publication number
- JPH03113832U JPH03113832U JP2286890U JP2286890U JPH03113832U JP H03113832 U JPH03113832 U JP H03113832U JP 2286890 U JP2286890 U JP 2286890U JP 2286890 U JP2286890 U JP 2286890U JP H03113832 U JPH03113832 U JP H03113832U
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- chip carrier
- connection terminal
- bump
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007373 indentation Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ〜ｃは本発明の一実施例を基板６に表
面実装する状態を工程順に示す正面図、第２図ａ
およびｂはそれぞれ第１図に示す外部接続端子２
の正面図および底面図、第３図ａ〜ｃは従来のチ
ツプキヤリアを基板６に表面実装する状態を工程
順に示す正面図である。
１，１１……チツプキヤリア、２，１２……外
部接続端子、３……くぼみ、４，１３……予備半
田、５，１４……導体回路、６，１５……基板、
７，１７……半田、１６……位置合わせマーク。
Figures 1a to 1c are front views showing the state in which an embodiment of the present invention is surface mounted on a substrate 6 in the order of steps, and Figure 2a is a
and b are the external connection terminals 2 shown in Fig. 1, respectively.
3A to 3C are front views showing the state in which a conventional chip carrier is surface mounted on a substrate 6 in the order of steps. 1, 11... Chip carrier, 2, 12... External connection terminal, 3... Recess, 4, 13... Preliminary solder, 5, 14... Conductor circuit, 6, 15... Board,
7, 17...Solder, 16...Positioning mark.
Claims (1)
先端に一定のくぼみが設けられていることを特徴
とするチツプキヤリア。 A chip carrier characterized by having a certain indentation at the tip of a bump-shaped external connection terminal formed on the back side of a circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2286890U JPH03113832U (en) | 1990-03-06 | 1990-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2286890U JPH03113832U (en) | 1990-03-06 | 1990-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03113832U true JPH03113832U (en) | 1991-11-21 |
Family
ID=31525874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2286890U Pending JPH03113832U (en) | 1990-03-06 | 1990-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03113832U (en) |
-
1990
- 1990-03-06 JP JP2286890U patent/JPH03113832U/ja active Pending
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