JPH03111027U - - Google Patents
Info
- Publication number
- JPH03111027U JPH03111027U JP1970390U JP1970390U JPH03111027U JP H03111027 U JPH03111027 U JP H03111027U JP 1970390 U JP1970390 U JP 1970390U JP 1970390 U JP1970390 U JP 1970390U JP H03111027 U JPH03111027 U JP H03111027U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock signal
- time constant
- arithmetic
- indicates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図及び第２図は本考案の一実施例を示すブ
ロツク図及び信号タイミング図、第３図及び第４
図は従来の回路のブロツク図及び信号タイミング
図である。
１，５……演算回路、２……データ保持回路、
３……比較回路、４……時定数回路。
1 and 2 are block diagrams and signal timing diagrams showing one embodiment of the present invention, and FIGS.
The figure is a block diagram and signal timing diagram of a conventional circuit. 1, 5... Arithmetic circuit, 2... Data holding circuit,
3... Comparison circuit, 4... Time constant circuit.
Claims (1)
化した入力信号における各チヤンネルでの値変化
を検出する比較回路と、前記入力信号に同期した
タイミングを示す第１のクロツク信号及び時定数
を指示する第２のクロツク信号に応答して時定数
処理のタイミングを示す第３のクロツク信号を発
生する時定数回路と、前記比較回路での検出結果
及び前記第３のクロツク信号に応答して時定数分
の計時演算を行なう演算回路と、該演算回路での
演算結果を一時保持して出力するデータ保持回路
とを備えることを特徴とするデイジタル・モノス
テーブル・マルチバイブレータ回路。 a comparator circuit that detects a value change in each channel of an input signal obtained by time-division multiplexing binary pulse signals of a plurality of channels; a first clock signal that indicates a timing synchronized with the input signal; and a first clock signal that indicates a time constant. a time constant circuit that generates a third clock signal indicating the timing of time constant processing in response to the second clock signal; A digital monostable multivibrator circuit comprising: an arithmetic circuit that performs a timekeeping operation; and a data holding circuit that temporarily holds and outputs the result of the arithmetic operation in the arithmetic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1970390U JPH03111027U (en) | 1990-02-27 | 1990-02-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1970390U JPH03111027U (en) | 1990-02-27 | 1990-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03111027U true JPH03111027U (en) | 1991-11-14 |
Family
ID=31522806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1970390U Pending JPH03111027U (en) | 1990-02-27 | 1990-02-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03111027U (en) |
-
1990
- 1990-02-27 JP JP1970390U patent/JPH03111027U/ja active Pending
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