JPS58178740U - A-D conversion number expansion circuit - Google Patents
A-D conversion number expansion circuitInfo
- Publication number
- JPS58178740U JPS58178740U JP7548182U JP7548182U JPS58178740U JP S58178740 U JPS58178740 U JP S58178740U JP 7548182 U JP7548182 U JP 7548182U JP 7548182 U JP7548182 U JP 7548182U JP S58178740 U JPS58178740 U JP S58178740U
- Authority
- JP
- Japan
- Prior art keywords
- expansion circuit
- conversion number
- number expansion
- interface element
- latch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のＡ−Ｄ変換数拡張回路の一実施例を系
す回路図、第５２図は第１図における各信号のタイミン
グを示すタイミングチャートである。
１・・・プログラマブルインタフェース素子、２・・・
デコーダ、３．４・・・ラッチ回路、５・・・センサ、
６・・・アナログマルチプレクサ、８・・・Ａ−Ｄ変ｔ
Ａ器。FIG. 1 is a circuit diagram of an embodiment of the A/D conversion number expansion circuit of the present invention, and FIG. 52 is a timing chart showing the timing of each signal in FIG. 1. 1... Programmable interface element, 2...
Decoder, 3.4... Latch circuit, 5... Sensor,
6...Analog multiplexer, 8...A-D change t
A device.
Claims (1)
蔵のインタフェース素子と、該インタフェース素子から
の出力値に対してタイミング処理を行うデコーダとラッ
チ回路とからなる機構とを備え、複数個のアナログマル
チプレクサを時分割で選択し、さらに、該選択されたマ
ルチプレクサのチャンネルを選択してＡ、−り変換器で
取り扱えるＡ−Ｄ変換数以上のデータ処理を実行可能の
構成としたことを特徴とするＡ−Ｄ変換数拡張回路。It is equipped with an interface element with a built-in latch circuit that temporarily stores programmed setting values, and a mechanism consisting of a decoder and latch circuit that performs timing processing on the output value from the interface element, and has multiple analog multiplexers. A--A-- characterized in that it is configured to be able to perform time-division selection, and further select a channel of the selected multiplexer to process data in excess of the number of A-D conversions that can be handled by the A--A converter. D conversion number expansion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7548182U JPS58178740U (en) | 1982-05-21 | 1982-05-21 | A-D conversion number expansion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7548182U JPS58178740U (en) | 1982-05-21 | 1982-05-21 | A-D conversion number expansion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58178740U true JPS58178740U (en) | 1983-11-30 |
Family
ID=30084838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7548182U Pending JPS58178740U (en) | 1982-05-21 | 1982-05-21 | A-D conversion number expansion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58178740U (en) |
-
1982
- 1982-05-21 JP JP7548182U patent/JPS58178740U/en active Pending
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