JPH03103830A - Active matrix type liquid crystal display device - Google Patents

Active matrix type liquid crystal display device

Info

Publication number
JPH03103830A
JPH03103830A JP1242762A JP24276289A JPH03103830A JP H03103830 A JPH03103830 A JP H03103830A JP 1242762 A JP1242762 A JP 1242762A JP 24276289 A JP24276289 A JP 24276289A JP H03103830 A JPH03103830 A JP H03103830A
Authority
JP
Japan
Prior art keywords
liquid crystal
pixel electrode
dielectric constant
source wiring
low dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1242762A
Other languages
Japanese (ja)
Inventor
Akihiro Hoshino
昭裕 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP1242762A priority Critical patent/JPH03103830A/en
Publication of JPH03103830A publication Critical patent/JPH03103830A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the voltage fluctuation of a pixel electrode caused by the variation of a signal voltage on a source wiring and the variation of a signal voltage on a data bus line by forming the source wiring, and a low dielectric constant insulating layer on a gap between the pixel electrode and the source wiring. CONSTITUTION:On a transparent insulating substrate 1 on which a pixel electrode 3 and a source wiring 4 are formed, SiO2 being a low dielectric constant insulating material is allowed to film and a low dielectric constant insulating film 12 is generated, a resist pattern 11 is formed thereon, and thereafter, by peeling off the resist pattern 11, a low dielectric constant insulating layer 6 is formed. In this state, the coupling capacity of the gap between the source wiring 4 and the pixel electrode 3 is small, the potential of the pixel electrode 3 is scarcely influenced by a signal voltage on the source wiring 4, and the display of a further multi-gradation can be executed. In such a manner, the voltage fluctuation of the pixel electrode caused by capacity coupling can be suppressed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、液晶ディスプレイ等に用いるアクティブマト
リクス型液晶表示装置(以下、AM−LCDと略称する
。)に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix liquid crystal display device (hereinafter abbreviated as AM-LCD) used for liquid crystal displays and the like.

〔従来の技術] 近年、画像情報の多い高精細の表示素子の開発が活発に
行われている。一画素の領域中に画素電極とアクティブ
デバイスCM膜トランジスタ(TPT)、2端子素子(
MIM等のダイオード、ハリスター等))が形成されて
いるAM−LCDは、高精細化の際に画素電極とアクテ
ィブデバイスの両方の面積を小さくする必要がある。し
かし、アクティブデバイスの小型化は、デバイス特性と
して限界がある。また、明るい表示画面を得るために開
口率を上げる必要があり、画素電極の面積を大きくする
ために画素電極と配線の間隙を狭める。
[Prior Art] In recent years, high-definition display elements containing a large amount of image information have been actively developed. In the area of one pixel, a pixel electrode, an active device CM film transistor (TPT), a two-terminal element (
AM-LCDs in which diodes such as MIM, Hallisters, etc.) are formed need to reduce the area of both the pixel electrode and the active device when achieving higher definition. However, miniaturization of active devices has limits in terms of device characteristics. Furthermore, in order to obtain a bright display screen, it is necessary to increase the aperture ratio, and in order to increase the area of the pixel electrode, the gap between the pixel electrode and the wiring is narrowed.

その結果、画素電極と配線間に液晶層を誘電体層とした
容量結合が大きくなり、非選択時の画素電極の電位がソ
ース配線上の信号電圧の影響を受番ノで変動する。つま
り、電圧の大きによって階調表示を行う場合の電圧のス
テップ幅をその電圧変動幅より大きくする必要があり、
階1+1 ′表示能力が低下する。このため、高階調表
示を行うためには画素電極の電圧変動を抑えることので
きる構造の検討が必要である。
As a result, capacitive coupling between the pixel electrode and the wiring using the liquid crystal layer as a dielectric layer increases, and the potential of the pixel electrode when not selected changes depending on the influence of the signal voltage on the source wiring. In other words, when performing gradation display depending on the voltage, the voltage step width must be larger than the voltage fluctuation width.
Floor 1+1' Display ability decreases. Therefore, in order to perform high gradation display, it is necessary to study a structure that can suppress voltage fluctuations of pixel electrodes.

以下では、AM−LCDのうち薄膜トランジスタ型液晶
表示装置(以下、TPT−LCDと略称する。)及び、
2端子素子型液晶表示装置(以下、2端子−LCDと略
称する。)について説明する。
Below, among AM-LCDs, thin film transistor type liquid crystal display devices (hereinafter abbreviated as TPT-LCDs) and
A two-terminal element type liquid crystal display device (hereinafter abbreviated as two-terminal-LCD) will be described.

第6図(a)は従来のTPT−LCDの構造を示す図で
、第6図(b)は第6図(a)中のA−A’線に沿った
断面図である。図中、1は透明絶縁性基板、2は薄膜ト
ランジスタ、3は画素電極、4はソース配線、5はゲー
ト配線である。同図に示すように、従来のTPTマトリ
クスアレイは、ソース配線4と画素電極3が接近して配
置された構造を有する。
FIG. 6(a) is a diagram showing the structure of a conventional TPT-LCD, and FIG. 6(b) is a sectional view taken along line AA' in FIG. 6(a). In the figure, 1 is a transparent insulating substrate, 2 is a thin film transistor, 3 is a pixel electrode, 4 is a source wiring, and 5 is a gate wiring. As shown in the figure, the conventional TPT matrix array has a structure in which source wiring 4 and pixel electrode 3 are arranged close to each other.

同様に、第7図(a)は従来の2端子−L C Dの構
造を示す図で、第7図(b)は第7図(a)中のA−A
線に沿った断面図である。図中、1は透明絶縁性基板、
10は2端子素子、3は画素電極、9はデータバスライ
ンである。同図に示すように、従来の2 b::1子素
子71・リクスアレイ番上、データハスツイン9と画素
電極3が接近して配置された構造を有する。
Similarly, FIG. 7(a) is a diagram showing the structure of a conventional two-terminal LCD, and FIG. 7(b) is a diagram showing the structure of A-A in FIG. 7(a).
It is a sectional view along the line. In the figure, 1 is a transparent insulating substrate;
10 is a two-terminal element, 3 is a pixel electrode, and 9 is a data bus line. As shown in the figure, it has a structure in which the conventional 2b::1 element 71, the top of the RIX array, the data hash twin 9, and the pixel electrode 3 are arranged close to each other.

したがって、T P T − L C Dに関しては、
ソース配線4と画素電極3との間隙に液晶層を誘電体層
とした前述の容量C,Dが生ずる。また、2端子LCD
に関しては、データバスライン9と画素電極3との間隙
に液晶層を誘電体層とした前述の容I C s nが生
ずる。上記容量CSDを介してソース配vA4と画素電
極3やデータバスライン9と画素電極3とが交流的に容
量で結合し、非選択画素電極3の電圧がソース配線4や
、データバスライン9上の画像信号電圧の変化の影響を
うけ、容易に3 変動する。したがって、電圧の大きさによって、階調表
示を行う通常の方法ではその電圧のステップ幅を電圧変
動幅より大きくすることが必要で多くの階調を表現する
のが難しい。
Therefore, for T P T - L C D,
The above-mentioned capacitances C and D are generated in the gap between the source wiring 4 and the pixel electrode 3 using the liquid crystal layer as a dielectric layer. Also, 2-terminal LCD
Regarding this, the above-mentioned capacity I C s n occurs in the gap between the data bus line 9 and the pixel electrode 3 in which the liquid crystal layer is a dielectric layer. The source wiring vA4 and the pixel electrode 3 and the data bus line 9 and the pixel electrode 3 are coupled in an alternating current capacitive manner via the capacitor CSD, and the voltage of the unselected pixel electrode 3 is applied to the source wiring 4 and the data bus line 9. Easily fluctuates due to the influence of changes in the image signal voltage. Therefore, depending on the magnitude of the voltage, in the normal method of displaying gradations, it is necessary to make the step width of the voltage larger than the voltage fluctuation width, making it difficult to express many gradations.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したように、従来のAM−LCDの構造では、画素
電極3とソース配線4との間隙の容量C■や画素電極3
とデータバスライン9との間隙の容量CSOが画素数の
多い高精細なAM−LCDになるほど大きくなり、その
ため画素電極3の電位が前記容量CSDを介してソース
配線上の信号電圧の変化やデータバスライン上の信号電
圧の変化によって容易に影響されるという問題があり、
高精細で多階調な表示のできるAM−LCDを作製する
ことは難しい。
As mentioned above, in the conventional AM-LCD structure, the capacitance C■ of the gap between the pixel electrode 3 and the source line 4 and the pixel electrode 3
The capacitance CSO of the gap between the data bus line 9 and the data bus line 9 increases as the number of pixels increases and the higher the resolution of the AM-LCD becomes. The problem is that it is easily affected by changes in the signal voltage on the bus line.
It is difficult to produce an AM-LCD capable of high-definition, multi-gradation display.

本発明の目的は、画素電極とソース配線、データバスラ
インと画素電極との間隙の容量を減少させ、ソース配線
上の信号電圧変化やデータバスライン上の信号電圧の変
化による画素電極の電圧変動の防止をすることにある。
An object of the present invention is to reduce the capacitance of the gap between the pixel electrode and the source wiring, and between the data bus line and the pixel electrode, and to prevent voltage fluctuations of the pixel electrode due to changes in the signal voltage on the source wiring or signal voltage on the data bus line. The goal is to prevent

4 〔課題を解決するための手段〕 本発明は、透明絶縁性基板l上に薄膜トランジスタ2及
び画素電極3をマトリクスアレイ状に配置し、前記画素
電極の列方向にソース配線4を、また行方向にゲート配
線5を配置し、前記透明絶縁性基板1と対向透明電極基
板7で液晶層8を挟んだ液晶表示装置において、前記ソ
ース配線と、画素電極とソース配線の間隙の上に低M 
t率絶縁層を形成した構造のアクティブマトリクス型液
晶表示装置、及び透明絶縁性基板1上に2端子素子(M
IM等のダイオードやバリスタ等)10及び画素電極3
をマトリクスアレイ状に配置し、前記画素電極の列方向
にデータバスライン9を配置し、前記透明絶縁性基板1
と対向透明電極基板7で液晶層8を挟んだ液晶表示装置
において、前記データバスライン9と画素電極とデータ
バスラインの間隙の上に低誘電率絶縁層6を形成した構
造のアクティブマトリクス型液品表示装置、及び前記低
誘電率絶縁層6が、液晶表示装置のセルギャップを保つ
スペーサーとなることを特徴とするアクティプマトリク
ス型液晶表示装置である。
4 [Means for Solving the Problems] In the present invention, thin film transistors 2 and pixel electrodes 3 are arranged in a matrix array on a transparent insulating substrate l, and source wirings 4 are arranged in the column direction of the pixel electrodes, and source wirings 4 are arranged in the row direction of the pixel electrodes. In a liquid crystal display device in which a gate wiring 5 is disposed on the substrate and a liquid crystal layer 8 is sandwiched between the transparent insulating substrate 1 and the opposite transparent electrode substrate 7, a low M
An active matrix type liquid crystal display device having a structure in which a t-rate insulating layer is formed, and a two-terminal element (M
IM (diodes, varistors, etc.) 10 and pixel electrodes 3
are arranged in a matrix array, data bus lines 9 are arranged in the column direction of the pixel electrodes, and the transparent insulating substrate 1
In a liquid crystal display device in which a liquid crystal layer 8 is sandwiched between a transparent electrode substrate 7 and a facing transparent electrode substrate 7, an active matrix type liquid crystal display device has a structure in which a low dielectric constant insulating layer 6 is formed on the gap between the data bus line 9, the pixel electrode, and the data bus line. This is an active matrix liquid crystal display device characterized in that the product display device and the low dielectric constant insulating layer 6 serve as spacers for maintaining the cell gap of the liquid crystal display device.

〔作用〕[Effect]

上記低誘電率絶縁層6を形成すれば、誘電率の大きな液
晶を画素電極、ソース電極間や、画素電極、データバス
ライン間から除くことができる。
By forming the low dielectric constant insulating layer 6, liquid crystal having a high dielectric constant can be removed from between the pixel electrodes and the source electrodes, and between the pixel electrodes and the data bus lines.

低誘電率絶縁層6の材料としてSiO2を用いるとする
と比誘電率は4程度である。一方液晶の比誘電率は、l
O〜15程度で約3倍程ある。従って液晶を低誘電率の
材料で置き換えることにより画素3とソース配線4間の
容量や画素3とデータバスライン9間の容量は、置き換
える前の約173に減少する。そのため画素電極3の電
圧は、ソース配線電圧やデータバスライン電圧の影響を
受けにくくなり、電圧の変動は小さくなる。つまり、よ
り小さな電圧きざみで階調表示の電圧を制御することが
可能となる。したがって、多階調の画像表示が可能とな
った。
If SiO2 is used as the material for the low dielectric constant insulating layer 6, the relative dielectric constant is about 4. On the other hand, the dielectric constant of liquid crystal is l
It is about 0 to 15, which is about 3 times as much. Therefore, by replacing the liquid crystal with a material having a low dielectric constant, the capacitance between the pixel 3 and the source line 4 and the capacitance between the pixel 3 and the data bus line 9 are reduced to about 173 before the replacement. Therefore, the voltage of the pixel electrode 3 is less susceptible to the influence of the source line voltage and the data bus line voltage, and voltage fluctuations are reduced. In other words, it becomes possible to control the voltage for gradation display in smaller voltage increments. Therefore, it has become possible to display images with multiple gradations.

〔実施例1〕 以ド第1図(El). (11)および、第3図Ol)
〜(C)ニより本発明のTFT−LCDの一実施例をそ
の製造工程とともに説明する。
[Example 1] Figure 1 below (El). (11) and Fig. 3 Ol)
An embodiment of the TFT-LCD of the present invention will be described from to (C) D along with its manufacturing process.

画素電極3、ソース配線4が形成された透明絶縁性基板
1上(第3図(a))に低誘電率絶縁材料であるSi0
2をプラズマCVD法により4μmの膜厚まで威膜し低
誘電率絶縁膜12を作成した(第3図(b))。つづい
てSiOz上にレジストパターンIIを形成し(第3図
(Cl)、その後、前記基板をRIE法でCF.ガスを
用いてドライエッチングし(第3図(d))、その後レ
ジストを剥離して低誘電率絶縁層6を形成した(第3図
(e))。その後前記透明絶縁性基板1と対向透明電極
基板7間に液晶を注入し液晶セルギャップ5μmのTP
T−LCDを作製した。
On the transparent insulating substrate 1 (FIG. 3(a)) on which the pixel electrode 3 and the source wiring 4 are formed, Si0, which is a low dielectric constant insulating material, is deposited.
2 was deposited to a thickness of 4 μm by plasma CVD to form a low dielectric constant insulating film 12 (FIG. 3(b)). Subsequently, a resist pattern II was formed on the SiOz (Fig. 3 (Cl)), and then the substrate was dry etched by RIE using CF gas (Fig. 3 (d)), and then the resist was peeled off. Then, a low dielectric constant insulating layer 6 was formed (FIG. 3(e)). Thereafter, liquid crystal was injected between the transparent insulating substrate 1 and the counter transparent electrode substrate 7 to form a TP with a liquid crystal cell gap of 5 μm.
A T-LCD was produced.

以上のようにして得られたTPTマトリクスアレイは(
第1図(a), (b)参照)、ソース配線と画素電極
の間隙の結合容量が小さく、画素電極の電位は、ソース
配線上の信号電圧の影響をほとんど受けず、より多階調
の表示が可能となった。
The TPT matrix array obtained as above is (
(see Figures 1(a) and (b)), the coupling capacitance between the source wiring and the pixel electrode is small, and the potential of the pixel electrode is almost unaffected by the signal voltage on the source wiring. It is now possible to display.

〔実施例2〕 以下第2図(a),(b)および、第4図(a) 〜(
d)により7 本発明の2端子−LCDの一実施例をその製造工程とと
もに説明する。
[Example 2] Below, Fig. 2 (a), (b) and Fig. 4 (a) - (
In accordance with d), one embodiment of the two-terminal LCD of the present invention will be described together with its manufacturing process.

画素電極3、データバスライン9が形成された透明絶縁
性基板1上(第4図(a))に低誘電率絶縁材料である
感光性ポリイミド(東レ製、フオトニース)をスピンコ
ートで膜厚3μm塗布し、低誘電率絶縁膜12を作成し
た(第4図(b))。プリヘーク後にマスク13を介し
て低誘電率絶縁層6のパターンを露光(第4図(C))
Lた。その後,現像ボストヘークを行うことにより低誘
電率絶縁層6を形成した(第4図(d))。その後、前
記透明絶縁性基板1と対向透明電極基板7間に液晶を注
入し液晶セルギャップ5μmの2端子−LCDを作製し
た。
On the transparent insulating substrate 1 (FIG. 4(a)) on which the pixel electrodes 3 and data bus lines 9 are formed, photosensitive polyimide (Photonys, manufactured by Toray), which is a low dielectric constant insulating material, is spin-coated to a thickness of 3 μm. A low dielectric constant insulating film 12 was formed (FIG. 4(b)). After pre-hake, the pattern of the low dielectric constant insulating layer 6 is exposed through the mask 13 (FIG. 4(C))
L. Thereafter, a low dielectric constant insulating layer 6 was formed by performing development and post-hake (FIG. 4(d)). Thereafter, liquid crystal was injected between the transparent insulating substrate 1 and the opposing transparent electrode substrate 7 to produce a two-terminal LCD with a liquid crystal cell gap of 5 μm.

以上のようにして得られた2端子素子マトリクスアレイ
(第2図(a), (b)参照)は、データバスライン
と画素電極間の結合容量が小さくなり、画素電極の電位
は、データーバスライン上の信号電圧の影響をほとんど
受けず、より多階調の表示が可能となった。
In the two-terminal element matrix array obtained as described above (see FIGS. 2(a) and (b)), the coupling capacitance between the data bus line and the pixel electrode is small, and the potential of the pixel electrode is lower than that of the data bus line. It is almost unaffected by the signal voltage on the line, making it possible to display more gradations.

8 〔実施例3〕 以下第5図(a). (b)により本発明のT F T
−L CDの一実施例をその製造工程とともに説明する
8 [Example 3] Figure 5 (a) below. According to (b), T F T of the present invention
An example of -LCD will be described along with its manufacturing process.

前記実施例1と同様な透明絶縁性基板1上に低誘電率絶
縁膜12の材料である感光性ポリイミド(東レ製、フォ
トニース)を液晶セルギャップ厚の5μmの膜厚だけス
ビンコートし、前記実施例2と同じ現倣, i?i光エ
捏で抵誘電率絶縁1d 6を形成しTPT−LCDを作
製した。
On the same transparent insulating substrate 1 as in Example 1, photosensitive polyimide (manufactured by Toray Industries, Ltd., Photonice), which is the material of the low dielectric constant insulating film 12, was coated with a film thickness of 5 μm, which is the liquid crystal cell gap thickness. Same imitation as example 2, i? A TPT-LCD was fabricated by forming a resistive dielectric constant insulation layer 1d6 using i-photonic processing.

以上のようにして得られたTFT−マトリクスアレイは
、ソース配線と画素電極間の結合容量が小さくなり、画
素電極の電位は、ソース配線上の信号電圧の影響をほと
んど受けず、より多階調の表示が可能となった。また、
液晶表示装置のセルギャップを保つスペーサーも低誘電
率絶縁層の作製と同時に出来るのでプロセス工程の簡略
化が図れた。
In the TFT-matrix array obtained as described above, the coupling capacitance between the source wiring and the pixel electrode is small, the potential of the pixel electrode is almost unaffected by the signal voltage on the source wiring, and it has more gray levels. It is now possible to display Also,
The spacer that maintains the cell gap of the liquid crystal display device can be made at the same time as the low dielectric constant insulating layer, which simplifies the process steps.

[発明の効果] 以上説明した如く本発明によれば容量結合による画素電
極の電圧変動を抑制することができ、クロストークが一
防一止できる。したがって、画素電圧のより細かな電圧
制御が可能となるため多階調表示が可能となる。
[Effects of the Invention] As described above, according to the present invention, it is possible to suppress the voltage fluctuation of the pixel electrode due to capacitive coupling, and crosstalk can be prevented. Therefore, more fine voltage control of the pixel voltage becomes possible, so that multi-gradation display becomes possible.

また、低誘電率絶縁層の作或と同時に液晶表示装置のセ
ルギャップを保つスペーサーも出来るので、プロセス工
程の簡略化が図れた。
Furthermore, since a spacer for maintaining the cell gap of a liquid crystal display device can be created at the same time as forming a low dielectric constant insulating layer, the process steps can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a), (b)は、本発明の構威のTFT−L
CDの説明図であって、(a)は平面図、(b)は(a
)の図中にA−A’で示した部分の断面図である。第2
図(a)、(b)は、本発明の構或の2端子素子の説明
図であって、(a)は平面図、(b)は(a)の図中に
A−A’ で示した部分の断面図である。第3図(a)
〜(e)および第4図(a)〜(d)は、本発明の低誘
電率絶縁層の製造工程の説明図、第5図(a), (b
)は、本発明の構成のTPT−LCDの説明図であって
、(a)は平面図、(b)は(a)の図中にA−A’で
示した部分の断面図、第6図(a), (b)は、従来
のTPT−LCDの説明図である。第7図(a), (
b)は、従来の2端子−LCDの説明図である。 1・・・透明絶縁性基板 2・・・薄膜トランジスタ 3・・・画素電極 4・・・ソース配線 5・・・ゲート配線 6・・・低誘電率絶縁層 7・・・対向透明電極基板 8・・・液晶層 9・・・データバスライン 10・・・2端子素子 11・・・フォトレジスト 12・・・低誘電率絶縁膜 l3・・・マスク 特  許  出  願  人 凸版印刷株式会社 代表者 鈴木 和夫 一217
FIGS. 1(a) and 1(b) show the TFT-L structure of the present invention.
It is an explanatory view of CD, (a) is a plan view, (b) is (a
) is a cross-sectional view of the portion indicated by AA' in the figure. Second
Figures (a) and (b) are explanatory diagrams of a two-terminal element according to the present invention, in which (a) is a plan view and (b) is indicated by AA' in the figure (a). FIG. Figure 3(a)
-(e) and FIGS. 4(a)-(d) are explanatory diagrams of the manufacturing process of the low dielectric constant insulating layer of the present invention, and FIGS. 5(a), (b)
) are explanatory diagrams of a TPT-LCD configured according to the present invention, in which (a) is a plan view, (b) is a cross-sectional view of the portion indicated by A-A' in the figure of (a), and the sixth Figures (a) and (b) are explanatory diagrams of a conventional TPT-LCD. Figure 7(a), (
b) is an explanatory diagram of a conventional two-terminal LCD. 1... Transparent insulating substrate 2... Thin film transistor 3... Pixel electrode 4... Source wiring 5... Gate wiring 6... Low dielectric constant insulating layer 7... Opposing transparent electrode substrate 8.・Liquid crystal layer 9 ・Data bus line 10 ・2-terminal element 11 ・Photoresist 12 ・Low dielectric constant insulating film 1 3 ・Mask patent application Toppan Printing Co., Ltd. Representative Suzuki Kazuoichi 217

Claims (3)

【特許請求の範囲】[Claims] (1)透明絶縁性基板上に薄膜トランジスタ及び画素電
極をマトリクスアレイ状に配置し、前記画素電極の列方
向にソース配線を、また行方向にゲート配線を配置し、
前記透明絶縁性基板と対向透明電極基板で液晶層を挟ん
だ液晶表示装置において、前記ソース配線と、画素電極
とソース配線の間隙の上に低誘電率絶縁層を形成したこ
とを特徴とするアクティブマトリクス型液晶表示装置。
(1) Thin film transistors and pixel electrodes are arranged in a matrix array on a transparent insulating substrate, source wiring is arranged in the column direction of the pixel electrode, and gate wiring is arranged in the row direction,
In the liquid crystal display device in which a liquid crystal layer is sandwiched between the transparent insulating substrate and the opposing transparent electrode substrate, a low dielectric constant insulating layer is formed on the source wiring and the gap between the pixel electrode and the source wiring. Matrix type liquid crystal display device.
(2)透明絶縁性基板上に2端子素子及び画素電極をマ
トリクスアレイ状に配置し、前記画素電極の列方向にデ
ータバスラインを配置し、前記透明絶縁性基板と対向透
明電極基板で液晶層を挟んだ液晶表示装置において、前
記データバスラインと、画素電極とデータバスラインの
間隙の上に低誘電率絶縁層を形成したことを特徴とする
アクティブマトリクス型液晶表示装置。
(2) Two-terminal elements and pixel electrodes are arranged in a matrix array on a transparent insulating substrate, data bus lines are arranged in the column direction of the pixel electrodes, and a liquid crystal layer is formed between the transparent insulating substrate and the opposing transparent electrode substrate. 1. An active matrix type liquid crystal display device comprising: a low dielectric constant insulating layer formed over the data bus line and the gap between the pixel electrode and the data bus line.
(3)前記低誘電率絶縁層が、液晶表示装置のセルギャ
ップを保つスペーサーとなることを特徴とする請求項(
1)または(2)記載のアクティブマトリクス型液晶表
示装置。
(3) Claim (3) characterized in that the low dielectric constant insulating layer serves as a spacer that maintains a cell gap of a liquid crystal display device.
The active matrix liquid crystal display device according to 1) or (2).
JP1242762A 1989-09-19 1989-09-19 Active matrix type liquid crystal display device Pending JPH03103830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1242762A JPH03103830A (en) 1989-09-19 1989-09-19 Active matrix type liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1242762A JPH03103830A (en) 1989-09-19 1989-09-19 Active matrix type liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH03103830A true JPH03103830A (en) 1991-04-30

Family

ID=17093896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1242762A Pending JPH03103830A (en) 1989-09-19 1989-09-19 Active matrix type liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH03103830A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0809131A2 (en) * 1996-05-24 1997-11-26 Tektronix, Inc. Plasma addressed liquid crystal display panel with reduced data drive electrode capacitance
CN100335955C (en) * 2003-12-24 2007-09-05 友达光电股份有限公司 Transmission reflective liquid crystal display board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6017720A (en) * 1983-07-12 1985-01-29 Canon Inc Liquid crystal display device
JPH01138540A (en) * 1987-08-31 1989-05-31 Seiko Epson Corp Active device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6017720A (en) * 1983-07-12 1985-01-29 Canon Inc Liquid crystal display device
JPH01138540A (en) * 1987-08-31 1989-05-31 Seiko Epson Corp Active device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0809131A2 (en) * 1996-05-24 1997-11-26 Tektronix, Inc. Plasma addressed liquid crystal display panel with reduced data drive electrode capacitance
EP0809131A3 (en) * 1996-05-24 1998-03-04 Tektronix, Inc. Plasma addressed liquid crystal display panel with reduced data drive electrode capacitance
CN100335955C (en) * 2003-12-24 2007-09-05 友达光电股份有限公司 Transmission reflective liquid crystal display board

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