JP2775892B2 - Two-terminal element type liquid crystal display - Google Patents

Two-terminal element type liquid crystal display

Info

Publication number
JP2775892B2
JP2775892B2 JP24276389A JP24276389A JP2775892B2 JP 2775892 B2 JP2775892 B2 JP 2775892B2 JP 24276389 A JP24276389 A JP 24276389A JP 24276389 A JP24276389 A JP 24276389A JP 2775892 B2 JP2775892 B2 JP 2775892B2
Authority
JP
Japan
Prior art keywords
liquid crystal
pixel electrode
data bus
terminal element
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24276389A
Other languages
Japanese (ja)
Other versions
JPH03103832A (en
Inventor
昭裕 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP24276389A priority Critical patent/JP2775892B2/en
Publication of JPH03103832A publication Critical patent/JPH03103832A/en
Application granted granted Critical
Publication of JP2775892B2 publication Critical patent/JP2775892B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、液晶ディスプレイ等に用いる2端子素子型
液晶表示装置(以下、2端子−LCDと略称する。)に関
するものである。
Description: TECHNICAL FIELD The present invention relates to a two-terminal element type liquid crystal display device (hereinafter, abbreviated as “two-terminal LCD”) used for a liquid crystal display or the like.

〔従来の技術〕[Conventional technology]

近年、画像情報の多い高精細の表示素子の開発が活発
に行われている。画素電極と2端子素子(MIM等のダイ
オード、バリスター等)が形成されている2端子−LCD
に関しては、高精細化に際し一画素の領域中の画素電極
と2端子素子の両方の面積を小さくする必要がある。し
かし、2端子素子の占める面積の小型化は、デバイス特
性として限界がある。また、明るい表示画面を得るため
に開口率を上げる必要があり、画素電極の面積を大きく
するために画素電極と配線の間隙を狭める。
In recent years, development of a high-definition display element having a lot of image information has been actively performed. Two-terminal LCD with pixel electrode and two-terminal element (diode such as MIM, varistor, etc.)
With regard to (1), it is necessary to reduce the area of both the pixel electrode and the two-terminal element in the area of one pixel in achieving higher definition. However, miniaturization of the area occupied by the two-terminal element has a limit as device characteristics. Further, it is necessary to increase the aperture ratio in order to obtain a bright display screen, and the gap between the pixel electrode and the wiring is reduced in order to increase the area of the pixel electrode.

その結果、画素電極と配線間に液晶層を誘電体層とし
た容量結合が大きくなり、非選択時の画素電極の電位が
データバスライン上の信号電圧の影響を受けて変動す
る。つまり、電圧の大きによって階調表示を行う場合の
電圧のステップ幅をその電圧変動幅より大きくする必要
があり、階調表示能力が低下する。このため、高階調表
示を行うためには画素電極の電圧変動を抑える構造が必
要である。
As a result, capacitive coupling using the liquid crystal layer as a dielectric layer between the pixel electrode and the wiring is increased, and the potential of the pixel electrode when not selected is changed under the influence of the signal voltage on the data bus line. That is, it is necessary to make the step width of the voltage when gradation display is performed depending on the magnitude of the voltage larger than the voltage fluctuation width, and the gradation display capability is reduced. For this reason, in order to perform high gradation display, a structure for suppressing a voltage fluctuation of the pixel electrode is required.

第3図(a)は従来の2端子−LCDの構造を示す図
で、第3図(b)は第3図(a)中のA−A′線に沿っ
た断面図である。図中、1は透明絶縁性基板、2は2端
子素子、3は画素電極、4はデータバスラインである。
同図に示すように、従来の2端子素子マトリクスアレイ
は、データバスライン4と画素電極3が接近して配置さ
れた構造を有する。したがって、データバスライン4と
画素電極3間に液晶層を誘電体層とした前述の容量CSD
が生ずる。上記容量CSDを介してデータバスライン4を
画素電極3とが交流的に容量で結合し、非選択画素電極
3の電圧がデータバスライン4上の画像信号電圧の変化
の影響をうけ、容易に変動する。したがって、電圧の大
きさによって、階調表示を行う通常の方法ではその電圧
のステップ幅を電圧変動幅より大きくすることが必要で
多くの階調表示を行うのが難しい。また、行方向に隣会
う画素間での結合容量も階調表示のステップ幅を小さく
した、高精細の表示を行う場合には問題となる。
FIG. 3 (a) is a view showing the structure of a conventional two-terminal LCD, and FIG. 3 (b) is a cross-sectional view taken along the line AA 'in FIG. 3 (a). In the figure, 1 is a transparent insulating substrate, 2 is a two-terminal element, 3 is a pixel electrode, and 4 is a data bus line.
As shown in FIG. 1, the conventional two-terminal element matrix array has a structure in which a data bus line 4 and a pixel electrode 3 are arranged close to each other. Therefore, the above-described capacitor C SD having a liquid crystal layer as a dielectric layer between the data bus line 4 and the pixel electrode 3 is used.
Occurs. The data bus line 4 and the pixel electrode 3 are alternately capacitively coupled to each other via the capacitor CSD, and the voltage of the unselected pixel electrode 3 is easily affected by the change in the image signal voltage on the data bus line 4. To fluctuate. Therefore, it is necessary to make the step width of the voltage larger than the voltage fluctuation width according to the normal method of performing gradation display depending on the magnitude of the voltage, and it is difficult to perform many gradation displays. In addition, the coupling capacitance between pixels adjacent in the row direction also poses a problem when performing high-definition display with a reduced step width of gradation display.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述したように、従来の2端子−LCDの構造では、画
素電極とデータバスライン間の容量CSDが画素数の多い
高精細な2端子−LCDになるほど大きくなり、そのため
画素電極3の電位が前記容量CSDを介してデータバスラ
イン上の信号電圧の変化によって容易に影響されるとい
う問題があり、高精細で多階調な表示のできる2端子−
LCDを作製することは難しい。
As described above, in the structure of the conventional two-terminal -LCD, capacitance C SD between the pixel electrodes and the data bus lines increases as becomes high definition two terminals -LCD large number of pixels, the potential of the order pixel electrode 3 the capacitance C via the SD there is a problem that is easily affected by changes in the signal voltage on the data bus line, two terminals that can multi-tone display with high definition -
It is difficult to make LCDs.

本発明の目的は、画素電極とデータバスラインと画素
電極間の容量を減少させ、データバスライン上の信号電
圧の変化による画素電極の電圧変動を防止することにあ
る。
SUMMARY OF THE INVENTION It is an object of the present invention to reduce the capacitance between a pixel electrode, a data bus line, and a pixel electrode, and prevent a voltage change of the pixel electrode due to a change in a signal voltage on the data bus line.

〔課題を解決するための手段〕[Means for solving the problem]

透明絶縁性基板1上に2端子素子2及び画素電極3を
マトリクスアレイ状に配置し、前記画素電極の列方向に
データバスライン4を配置し、前記透明絶縁性基板1と
対向透明電極基板5で液晶層6を挟んだ液晶表示装置に
おいて、前記データバスライン4上に低誘電率層間絶縁
層7を介してアースライン8を設け、さらに前記画素電
極3と行方向に隣合う画素電極3間に画素幅の電極を設
け前記アースラインと接続したことを特徴とする2端子
素子型液晶表示装置。
The two-terminal device 2 and the pixel electrodes 3 are arranged in a matrix array on the transparent insulating substrate 1, the data bus lines 4 are arranged in the column direction of the pixel electrodes, and the transparent insulating substrate 1 and the opposing transparent electrode substrate 5 are arranged. In the liquid crystal display device with the liquid crystal layer 6 interposed therebetween, an earth line 8 is provided on the data bus line 4 with a low dielectric constant interlayer insulating layer 7 interposed between the pixel electrodes 3 and the pixel electrodes 3 adjacent in the row direction. A two-terminal element type liquid crystal display device, wherein an electrode having a pixel width is provided and connected to the ground line.

〔作用〕[Action]

上記アースライン8を接地電位に接続すれば、データ
バスライン4は、シールドされて画素電極間に結合容量
は殆ど生じない。そのため画素電極3の電圧は、データ
バスライン電圧の影響を受ない。また液晶駆動ドライバ
ーの負荷を減らして消費電圧を抑え、さらにデータバス
ラインの容量性負荷による画像信号の波形鈍りを抑える
ために、比誘電率が3〜5の低誘電率材料からなる低誘
電率層間絶縁層7を設けた。その結果、画素電極3の電
圧は、データバスラインの電圧の影響を受けなくなり、
より小さな電圧刻みで階調表示の電圧を制御することが
可能となる。
If the earth line 8 is connected to the ground potential, the data bus line 4 is shielded and almost no coupling capacitance occurs between the pixel electrodes. Therefore, the voltage of the pixel electrode 3 is not affected by the data bus line voltage. In addition, in order to reduce the load on the liquid crystal driving driver to reduce the voltage consumption and to suppress the waveform dulling of the image signal due to the capacitive load on the data bus line, a low dielectric constant made of a low dielectric constant material having a relative dielectric constant of 3 to 5 is used. An interlayer insulating layer 7 was provided. As a result, the voltage of the pixel electrode 3 is not affected by the voltage of the data bus line,
It is possible to control the gradation display voltage in smaller voltage increments.

〔実施例1〕 以下第1図(a),(b)および、第2図(a)〜
(d)により本発明の一実施例をその製造工程とともに
説明する。
Example 1 FIGS. 1 (a) and (b) and FIGS. 2 (a) to 2 (b)
An embodiment of the present invention will be described with reference to FIG.

画素電極3、データバスライン4が形成された透明絶
縁性基板1上(第2図(a))に低誘電率絶縁材料であ
るシリコン酸化膜SiO2をプラズマCVD法で0.5μm成膜
し、フォトリソプロセスでパターニングし、RIE法でCF4
ガスを用いてドライエッチングし低誘電率層間絶縁層7
を形成した(第2図(b))。続いてアルミニウム(A
l)をスパッタで2μm成膜しフォトリソプロセスでパ
ターニングし、エッチングして、アースライン8を形成
した(第2図(c))。次に、保護膜としてスパッタ法
でSiO2を0.5μm成膜し、フォトリソプロセスでパター
ニングした(第2図(d))。その後前記透明絶縁性基
板1と対向透明電極基板5の間隙に液晶を注入し2端子
−LCD(第1図(a),(b)参照)を作製した。
On the transparent insulating substrate 1 on which the pixel electrodes 3 and the data bus lines 4 are formed (FIG. 2A), a silicon oxide film SiO 2 as a low dielectric constant insulating material is formed to a thickness of 0.5 μm by a plasma CVD method. Patterned by photolitho process, CF 4 by RIE
Dry etching using gas to obtain low dielectric constant interlayer insulating layer 7
Was formed (FIG. 2 (b)). Then aluminum (A
1) was formed into a film having a thickness of 2 μm by sputtering, patterned by a photolithography process, and etched to form an earth line 8 (FIG. 2C). Next, 0.5 μm of SiO 2 was formed as a protective film by a sputtering method, and was patterned by a photolithographic process (FIG. 2D). Thereafter, liquid crystal was injected into the gap between the transparent insulating substrate 1 and the opposing transparent electrode substrate 5 to produce a two-terminal LCD (see FIGS. 1A and 1B).

以上のようにして得られた2端子素子マトリクスアレ
イでは、データバスラインと画素電極間の結合容量CSD
は十分小さく、画素電極の電位はデータバスライン上の
信号電圧の影響をほとんど受けず、より多階調の表示が
可能となった。
In the two-terminal element matrix array obtained as described above, the coupling capacitance C SD between the data bus line and the pixel electrode is obtained.
Is sufficiently small, and the potential of the pixel electrode is hardly affected by the signal voltage on the data bus line, so that display with more gradations can be performed.

〔発明の効果〕〔The invention's effect〕

以上説明した如く本発明によれば容量結合による画素
電極の電圧変動を抑制することができ、クロストークが
防止できる。したがって、画素電圧のより細かな電圧制
御が可能となり、多階調表示が可能となる。
As described above, according to the present invention, the voltage fluctuation of the pixel electrode due to the capacitive coupling can be suppressed, and the crosstalk can be prevented. Therefore, finer voltage control of the pixel voltage becomes possible, and multi-gradation display becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)、(b)は、本発明の構成の説明図であっ
て、(a)は平面図、(b)は(a)の図中にA−A′
で示した部分の断面図、第2図(a)〜(d)は、本発
明の一実施例の製造行程の説明図、第3図(a)、
(b)は、従来の2端子−LCDの説明図である。 1……透明絶縁性基板 2……2端子素子 3……画素電極、4……データバスライン 5……対向透明電極基板 6……液晶層 7……低誘電率層間絶縁層 8……アースライン 9……保護膜 10……対向透明電極
1 (a) and 1 (b) are explanatory views of the configuration of the present invention, where (a) is a plan view and (b) is a view taken along line AA 'in (a).
2 (a) to 2 (d) are cross-sectional views of the part shown in FIG.
(B) is an explanatory view of a conventional two-terminal LCD. DESCRIPTION OF SYMBOLS 1 ... Transparent insulating substrate 2 ... 2 terminal element 3 ... Pixel electrode 4 ... Data bus line 5 ... Opposing transparent electrode substrate 6 ... Liquid crystal layer 7 ... Low dielectric constant interlayer insulating layer 8 ... Earth Line 9: Protective film 10: Opposite transparent electrode

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】透明絶縁性基板上に2端子素子及び画素電
極をマトリクスアレイ状に配置し、前記画素電極の列方
向にデータバスラインを配置し、前記透明絶縁性基板と
対向透明電極基板で液晶層を挟んだ液晶表示装置におい
て、前記データバスライン上に低誘電率層間絶縁層を介
してアースラインを設け、さらに前記画素電極と行方向
に隣合う画素電極間に画素幅の電極を設け前記アースラ
インと接続したことを特徴とする2端子素子型液晶表示
装置。
1. A two-terminal element and a pixel electrode are arranged in a matrix array on a transparent insulating substrate, and a data bus line is arranged in a column direction of the pixel electrode. In a liquid crystal display device sandwiching a liquid crystal layer, an earth line is provided on the data bus line via a low dielectric constant interlayer insulating layer, and further, an electrode having a pixel width is provided between pixel electrodes adjacent to the pixel electrode in a row direction. A two-terminal element type liquid crystal display device connected to the earth line.
JP24276389A 1989-09-19 1989-09-19 Two-terminal element type liquid crystal display Expired - Lifetime JP2775892B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24276389A JP2775892B2 (en) 1989-09-19 1989-09-19 Two-terminal element type liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24276389A JP2775892B2 (en) 1989-09-19 1989-09-19 Two-terminal element type liquid crystal display

Publications (2)

Publication Number Publication Date
JPH03103832A JPH03103832A (en) 1991-04-30
JP2775892B2 true JP2775892B2 (en) 1998-07-16

Family

ID=17093913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24276389A Expired - Lifetime JP2775892B2 (en) 1989-09-19 1989-09-19 Two-terminal element type liquid crystal display

Country Status (1)

Country Link
JP (1) JP2775892B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103376604B (en) * 2012-04-12 2016-03-30 群康科技(深圳)有限公司 Dot structure and apply its liquid crystal display structure

Also Published As

Publication number Publication date
JPH03103832A (en) 1991-04-30

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