JPH0290658A - Densely packaged circuit device - Google Patents
Densely packaged circuit deviceInfo
- Publication number
- JPH0290658A JPH0290658A JP24356888A JP24356888A JPH0290658A JP H0290658 A JPH0290658 A JP H0290658A JP 24356888 A JP24356888 A JP 24356888A JP 24356888 A JP24356888 A JP 24356888A JP H0290658 A JPH0290658 A JP H0290658A
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- packaged
- circuit
- component
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 19
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000005011 phenolic resin Substances 0.000 claims abstract description 11
- 229920001568 phenolic resin Polymers 0.000 claims abstract description 11
- 238000000465 moulding Methods 0.000 claims abstract description 6
- 238000004806 packaging method and process Methods 0.000 claims abstract description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000011247 coating layer Substances 0.000 abstract description 6
- 229920001721 polyimide Polymers 0.000 abstract description 6
- 239000009719 polyimide resin Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 230000002378 acidificating effect Effects 0.000 abstract description 3
- 238000011990 functional testing Methods 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011889 copper foil Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000005022 packaging material Substances 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000006071 cream Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、高密度実装回路装置に係り、特にベアチップ
部品を含む面実装部品を実装して成る高密度実装回路装
置の改良に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a high-density mounting circuit device, and particularly to a high-density mounting circuit device in which surface-mounted components including bare chip components are mounted. Regarding improvements.
（従来の技術）
電子部品の小型化、あるいは回路の高密度化を目的に、
例えば回路基板の所定領域にベアチップ部品、フラット
パッケージ型ＩＣ素子等の面実鰺部品及びチップ抵抗体
等を表面実装し、これらを、例えばエポキシ系樹脂や、
ポリイミド系樹脂等で、モールド封止した構成の高密度
実装回路装置が知られており、また、実用に供されてい
る。(Conventional technology) For the purpose of miniaturizing electronic components or increasing the density of circuits,
For example, bare chip components, flat packaged IC devices, chip resistors, etc. are surface-mounted on a predetermined area of a circuit board, and these are mounted using, for example, epoxy resin,
2. Description of the Related Art High-density packaging circuit devices having a mold-sealed configuration using polyimide resin or the like are known and are in practical use.
（発明が解決しようとする課題）
しかしながら、上記実装回路基板については、次のよう
な不都合がある。即ち、ベースを成すセラミック基板が
比較的高価でコストアップになるばかりでなく、例えば
、前記モールド樹脂層を化学的に処理し、溶解除去する
と、前記セラミック基板に実装しであるベアチップ部品
の回路パターンや、結線状態等はそのまま残存する。こ
のベアチップ部品の回路パターン残存は、回路構成の機
密性の保持の上で往々問題になる。つまり、この種の高
密度実装回路基板を電子機器類、メモリーカード、ＩＣ
カード類に用いた際、セキュリティの点で実用上問題に
なる。(Problems to be Solved by the Invention) However, the above-mentioned mounted circuit board has the following disadvantages. That is, not only is the base ceramic substrate relatively expensive and increases the cost, but also, for example, if the mold resin layer is chemically treated and dissolved and removed, the circuit pattern of the bare chip component mounted on the ceramic substrate will be damaged. , wiring status, etc. remain as they are. This residual circuit pattern of bare chip components often poses a problem in maintaining the confidentiality of the circuit configuration. In other words, this type of high-density mounting circuit board can be used for electronic devices, memory cards, and ICs.
When used in cards, it poses a practical problem in terms of security.
［発明の構成］
（課題を解決するための手段）
本発明は、ベース基板として有機系樹脂の多層板を用い
、この多層板に実装したベアチップ部品、あるいはベア
チップ部品と他の面実装部品を樹脂モールドした構成に
おいて、前記ベアチップ部品面にフェノール系樹脂層を
下地層乃至予備層として介在させたことを特徴とする。[Structure of the Invention] (Means for Solving the Problems) The present invention uses a multilayer board made of organic resin as a base substrate, and bare chip components mounted on the multilayer board, or bare chip components and other surface-mounted components are mounted on the resin. In the molded structure, a phenolic resin layer is interposed on the surface of the bare chip component as a base layer or preliminary layer.
（作 用）
上記の如く、本発明に係る高密度実装回路装置において
は、実装されたベアチップ部品は、フェノール系樹脂層
で予備的に被覆され、樹脂モールドされている。しかし
て、前記フェノール系樹脂層は、酸性の処理液でないと
溶解除去しえない。(Function) As described above, in the high-density packaging circuit device according to the present invention, the mounted bare chip components are preliminarily coated with a phenolic resin layer and resin-molded. However, the phenolic resin layer cannot be dissolved and removed without an acidic treatment solution.
つまり、前記モールド樹脂層を、全体的に溶解除去する
ためには、最終的に酸性の処理液を用いざるを得ず、こ
の酸性処理液の使用により、面実装部品のボンディング
ワイヤ（Ａｕ線）や、ベース基板の回路パターン（銅箔
層）も溶解除去され、回路内容のセキュリティを容易に
保持しうる。In other words, in order to completely dissolve and remove the molding resin layer, it is necessary to use an acidic processing solution. In addition, the circuit pattern (copper foil layer) on the base board is also dissolved and removed, making it possible to easily maintain the security of the circuit contents.
（実施例）
以下本発明の詳細な説明する。第１図は、本発明の高密
度実装回路装置の構成例を示す断面図であり、１は有機
系樹脂多層基板、２は前記有機系樹脂多層基板１の所定
領域面に実装された表面実装型（ＱＦＰ、５ＯＰ）のＬ
ＳＩ素子である。(Example) The present invention will be described in detail below. FIG. 1 is a cross-sectional view showing a configuration example of a high-density packaging circuit device of the present invention, in which 1 is an organic resin multilayer substrate, and 2 is a surface mount mounted on a predetermined area surface of the organic resin multilayer substrate 1. Type (QFP, 5OP) L
It is an SI element.
また、３はチップコンデンサもしくは抵抗、４はベアチ
ップ部品で、これらチップコンデンサもしくは抵抗３及
びベアチップ部品４も、前記有機系樹脂多層基板１の所
定領域面に実装されている。Further, 3 is a chip capacitor or a resistor, and 4 is a bare chip component. These chip capacitors or resistors 3 and the bare chip component 4 are also mounted on a predetermined area surface of the organic resin multilayer substrate 1.
更に５は前記ベアチップ部品４の領域を被覆したフェノ
ール系樹脂から成る予備被覆層、６は前記予備被覆層５
や実装されている他の電子部品２゜３を含め、有機系樹
脂多層基板１全体を被覆モールドした樹脂層、例えば、
ポリイミド系樹脂層である。なお、図において、７は外
部リード線である。Furthermore, 5 is a pre-coating layer made of phenolic resin that covers the area of the bare chip component 4, and 6 is the pre-coating layer 5.
A resin layer that is molded to cover the entire organic resin multilayer board 1, including the electronic components 2.3 and other mounted electronic components, for example,
This is a polyimide resin layer. In addition, in the figure, 7 is an external lead wire.
次に上記構成の実装回路装置の製造方法の一例に就いて
説明する。所要の回路パターンを有する例えば、ポリイ
ミド樹脂系の多層基板を先ず用意する。上記用意した多
層基板面の所定・領域にクリーム半田を印刷法で被着し
ておき、表面実装型素子１、例えば５−ＲＡＭ素子２や
コンデンサもしくは抵抗３等の面実装部品をマウントし
、そのマウントした部分（領域）の半田をリフローさせ
て所要の半田付、実装を行う。しかる後、前記多層基板
の所定領域面にベアチップ部品４、例えばＭ−ＲＯＭを
グイボンドし、所要のワイヤボンデングを行った後に、
機能テストをする。かくして、所要の電子部品の実装及
び機能テスト後、前記ベアチップ部品４及びその周辺を
フェノール系樹脂で被覆処理して予備被覆層５を形成す
る。次いで、上記表面実装され、露出している５−ＲＡ
Ｍ素子２、チップコンデンサもしくは抵抗３及び前記予
備被覆層５で被覆されているベアチップ部品４を例えば
、ポリイミド系樹脂６で、一体的にコーテング乃至モー
ルドして封止し、最終的なテストを行うことにより、所
望の実装回路装置が得られる。Next, an example of a method for manufacturing the mounted circuit device having the above configuration will be explained. First, a multilayer board made of, for example, polyimide resin and having a required circuit pattern is prepared. Cream solder is applied to a predetermined area of the multilayer board surface prepared above by a printing method, and surface mount components such as a surface mount element 1, such as a 5-RAM element 2, a capacitor or a resistor 3, are mounted. Reflow the solder on the mounted part (area) and perform the required soldering and mounting. After that, a bare chip component 4, for example, an M-ROM, is bonded to a predetermined area surface of the multilayer board, and after performing necessary wire bonding,
Do a functional test. After mounting the required electronic components and testing their functionality, the bare chip component 4 and its surroundings are coated with a phenolic resin to form a preliminary coating layer 5. Then the surface-mounted exposed 5-RA
The M element 2, the chip capacitor or resistor 3, and the bare chip component 4 covered with the preliminary coating layer 5 are integrally coated or molded and sealed with, for example, a polyimide resin 6, and a final test is performed. As a result, a desired mounted circuit device can be obtained.
なお、上記実施例では、表面実装型素子として、５−Ｒ
ＡＭを、ベアチップ部品としてＭ−ＲＯＭを各々実装し
た例を示したが、他のＬＳＩ素子等でも勿論良いし、ま
た、実装する素子の数も各々−環数であってもよい。更
に、実装した各電子部品をコーテング乃至モールディン
グにより封止する樹脂はポリイミド系に限らず、例えば
エポキシ系樹脂等他の封止用の樹脂であってもよい。In the above embodiment, 5-R is used as a surface mount type element.
Although an example has been shown in which the AM and the M-ROM are each mounted as bare chip components, other LSI elements or the like may of course be used, and the number of mounted elements may also be a ring number. Further, the resin for sealing each mounted electronic component by coating or molding is not limited to polyimide resin, and may be other sealing resin such as epoxy resin.
［発明の効果］
上記本発明によれば、ベース基板に有機系樹脂の多層基
板を用いているため、製造面でのコスト低減を計れるば
かりでなく、その実装回路装置の回路内容に就いて、セ
キュリティを十分保持しうる。即ち、実装したベアチッ
プ部品を封止する樹脂層（コーティング乃至モールディ
ング層）を溶解除去して回路内容を調査しようとしても
、ベアチップ部品を被覆する予備層の溶解除去過程で、
ボンディングワイヤ、回路パターン等も共に溶解除去さ
れるので、回路内容に就いてのセキュリティは容易に保
持される。[Effects of the Invention] According to the present invention, since a multilayer board made of organic resin is used as the base board, not only can manufacturing cost be reduced, but also the circuit content of the mounted circuit device can be improved. Security can be maintained sufficiently. In other words, even if you attempt to investigate the circuit content by dissolving and removing the resin layer (coating or molding layer) that seals the bare chip component that has been mounted, the process of dissolving and removing the preliminary layer that covers the bare chip component,
Since the bonding wires, circuit patterns, etc. are also melted and removed, the security of the circuit contents is easily maintained.
第１図は、本発明に係る高密度実装回路装置の一構成例
を示す断面図である。
１・・・有機系樹脂多層基板
２・・・而実装部品
３・・・チップコンデンサもしく
４・・・ベアチップ部品
５・・・フェノール系樹脂層
６・・・モールド樹脂層
は抵抗FIG. 1 is a sectional view showing a configuration example of a high-density packaging circuit device according to the present invention. 1... Organic resin multilayer board 2... Mounted component 3... Chip capacitor or 4... Bare chip component 5... Phenolic resin layer 6... Molded resin layer is a resistor
Claims (1)
領域に実装されたベアチップ部品を含む面実装部品と、
前記ベアチップ部品を被覆するフェノール系樹脂の被膜
と、前記フェノール系樹脂の被膜及び他の面実装部品を
モールドするモールド樹脂層とを具備してなる高密度実
装回路装置。an organic resin multilayer board; a surface mount component including a bare chip component mounted in a predetermined area of the organic resin multilayer board;
A high-density packaging circuit device comprising: a phenolic resin coating that covers the bare chip component; and a molding resin layer that molds the phenolic resin coating and other surface-mounted components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24356888A JPH0290658A (en) | 1988-09-28 | 1988-09-28 | Densely packaged circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24356888A JPH0290658A (en) | 1988-09-28 | 1988-09-28 | Densely packaged circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0290658A true JPH0290658A (en) | 1990-03-30 |
Family
ID=17105773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24356888A Pending JPH0290658A (en) | 1988-09-28 | 1988-09-28 | Densely packaged circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0290658A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075476A (en) * | 1989-06-07 | 1991-12-24 | Mitsubishi Gas Chemical Company, Inc. | Process for production of sulfonium compounds and novel methylthiphenol derivatives |
| US5187311A (en) * | 1989-06-07 | 1993-02-16 | Mitsubishi Gas Chemical Company, Inc. | Methylthiophenol derivatives and p-methylthiophenyl chloroformates and processes for producing these derivatives |
| US6313521B1 (en) * | 1998-11-04 | 2001-11-06 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| JP2017023275A (en) * | 2015-07-17 | 2017-02-02 | 株式会社大一商会 | Game machine |
| JP2017023276A (en) * | 2015-07-17 | 2017-02-02 | 株式会社大一商会 | Game machine |
| JP2017035357A (en) * | 2015-08-11 | 2017-02-16 | 株式会社大一商会 | Game machine |
| JP2017035356A (en) * | 2015-08-11 | 2017-02-16 | 株式会社大一商会 | Game machine |
| JP2022002260A (en) * | 2020-06-22 | 2022-01-06 | 株式会社村田製作所 | Surface-mounted passive component |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6027438B2 (en) * | 1982-11-12 | 1985-06-28 | 株式会社東芝 | Banknote identification device |
| JPS60199446A (en) * | 1983-03-20 | 1985-10-08 | ザ、プロクタ−、エンド、ギヤンブル、カンパニ− | Sanitary napkin having flap |
| JPS6054365B2 (en) * | 1979-03-29 | 1985-11-29 | 日本鋼管株式会社 | How to operate a blast furnace blower |
| JPS61125344A (en) * | 1984-11-21 | 1986-06-13 | 糸川 正男 | Sanitary napkin and its production |
-
1988
- 1988-09-28 JP JP24356888A patent/JPH0290658A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054365B2 (en) * | 1979-03-29 | 1985-11-29 | 日本鋼管株式会社 | How to operate a blast furnace blower |
| JPS6027438B2 (en) * | 1982-11-12 | 1985-06-28 | 株式会社東芝 | Banknote identification device |
| JPS60199446A (en) * | 1983-03-20 | 1985-10-08 | ザ、プロクタ−、エンド、ギヤンブル、カンパニ− | Sanitary napkin having flap |
| JPS61125344A (en) * | 1984-11-21 | 1986-06-13 | 糸川 正男 | Sanitary napkin and its production |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075476A (en) * | 1989-06-07 | 1991-12-24 | Mitsubishi Gas Chemical Company, Inc. | Process for production of sulfonium compounds and novel methylthiphenol derivatives |
| US5187311A (en) * | 1989-06-07 | 1993-02-16 | Mitsubishi Gas Chemical Company, Inc. | Methylthiophenol derivatives and p-methylthiophenyl chloroformates and processes for producing these derivatives |
| US6313521B1 (en) * | 1998-11-04 | 2001-11-06 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| JP2017023275A (en) * | 2015-07-17 | 2017-02-02 | 株式会社大一商会 | Game machine |
| JP2017023276A (en) * | 2015-07-17 | 2017-02-02 | 株式会社大一商会 | Game machine |
| JP2017035357A (en) * | 2015-08-11 | 2017-02-16 | 株式会社大一商会 | Game machine |
| JP2017035356A (en) * | 2015-08-11 | 2017-02-16 | 株式会社大一商会 | Game machine |
| JP2022002260A (en) * | 2020-06-22 | 2022-01-06 | 株式会社村田製作所 | Surface-mounted passive component |
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