JPH04137657A - Hybrid integrated circuit board - Google Patents
Hybrid integrated circuit boardInfo
- Publication number
- JPH04137657A JPH04137657A JP25913990A JP25913990A JPH04137657A JP H04137657 A JPH04137657 A JP H04137657A JP 25913990 A JP25913990 A JP 25913990A JP 25913990 A JP25913990 A JP 25913990A JP H04137657 A JPH04137657 A JP H04137657A
- Authority
- JP
- Japan
- Prior art keywords
- board
- resin
- circuit board
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000465 moulding Methods 0.000 abstract description 9
- 239000007788 liquid Substances 0.000 abstract description 7
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 150000002989 phenols Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は、絶縁性基板に予め貫通穴を設けた混成集積回
路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to a hybrid integrated circuit board in which an insulating substrate is provided with through holes in advance.
（従来の技術）
周知の如く、混成集積回路基板の信頼性を上げる方法と
して、一般的に樹脂封止器による外装が用いられている
。例えば、特に技術的に難しいＤＩＰ型構造の混成集積
回路基板を樹脂モールドするには、第２図（Ａ）、（Ｂ
）に示すような方法を採用していた。ここで、第２図（
Ａ）は樹脂封止前、第２図（Ｂ）は樹脂封止後を示す。(Prior Art) As is well known, as a method of increasing the reliability of hybrid integrated circuit boards, packaging with a resin sealer is generally used. For example, in order to resin mold a hybrid integrated circuit board with a DIP type structure, which is particularly technically difficult, it is necessary to
) was adopted. Here, Figure 2 (
A) shows the state before resin sealing, and FIG. 2(B) shows the state after resin sealing.
第２図（Ａ）において、１は絶縁性基板である。In FIG. 2(A), 1 is an insulating substrate.
この基板１の両面には、導体パターン２が形成されてい
る。この基板１には、ＦＰ型ＩＣ３やチップ部品４が搭
載されている。前記基板の対向する両端部には、複数の
リード端子５が前記基板を把持するように２列設けられ
ている。Conductor patterns 2 are formed on both sides of this substrate 1. On this board 1, an FP type IC 3 and chip components 4 are mounted. A plurality of lead terminals 5 are provided in two rows at opposite ends of the substrate so as to grip the substrate.
こうした樹脂封止器を形成する前の基板を、リード端子
５の先端を上部に向けて例えばエポキシ変性フェノール
樹脂等のモールド樹脂液中に所定の時間浸漬した後、引
き上げることにより、基板１、ＩＣ３，チップ部品４を
囲むような樹脂層を被覆する。この後、前記基板を加熱
、処理して樹脂層を硬化し、第２図（Ｂ）に示す如く樹
脂封止器６を形成する。The substrate before forming such a resin sealer is immersed in a molding resin liquid such as epoxy-modified phenol resin for a predetermined time with the tips of the lead terminals 5 facing upward, and then pulled up. , a resin layer surrounding the chip component 4 is coated. Thereafter, the substrate is heated and treated to harden the resin layer, forming a resin sealer 6 as shown in FIG. 2(B).
ところで、従来の混成集積回路基板においては、基板１
にＦＰ型ＩＣ３等のように大型の電子部品を実装した場
合には、これらの部品と基板１間に大きな空隙が存在す
る。従って、前記基板１をモールド樹脂液中に浸漬する
際、モールド樹脂が空隙まで浸漬せず、空気が基板上に
残留した状態となり、基板１を引き上げる際その空気が
被覆された樹脂層を通して逃げる。その結果、第２図（
Ｂに示す如く外囲器６にピンホール７が生じ、この混成
集積回路基板の信頼性が低下するという問題点を有する
。By the way, in the conventional hybrid integrated circuit board, the board 1
When large electronic components such as the FP type IC 3 are mounted on the substrate 1, a large gap exists between these components and the substrate 1. Therefore, when the substrate 1 is immersed in the molding resin liquid, the molding resin is not immersed up to the gap, and air remains on the substrate, and when the substrate 1 is pulled up, the air escapes through the coated resin layer. As a result, Figure 2 (
As shown in B, a pinhole 7 is formed in the envelope 6, which poses a problem in that the reliability of this hybrid integrated circuit board is reduced.
また、樹脂層６が硬化する際、部品３．４と基板１間に
空気が残留していると、空気か熱膨張した際に、同様に
ピンホールが生しる。Furthermore, if air remains between the component 3.4 and the substrate 1 when the resin layer 6 is cured, pinholes will similarly occur when the air thermally expands.
なお、前記ピンホールは基板を再度浸漬することにより
埋めることが技術的に可能であるか、樹脂層の厚みが増
大するため、現実的な解決策ではない。Note that this is not a practical solution because it is technically possible to fill the pinhole by dipping the substrate again, or the thickness of the resin layer increases.
（発明が解決しようとする課題）
本発明は上記事情に鑑みてなされたもので、絶縁性基板
に該基板と電子部品間に残留する空気を流すための貫通
穴を設けることにより、ピンホールのない樹脂封止器が
得られ、信頼性の高い混成集積回路基板を提供すること
を目的とする。(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and by providing a through hole in an insulating substrate for flowing air remaining between the substrate and electronic components, pinholes can be eliminated. It is an object of the present invention to provide a highly reliable hybrid integrated circuit board in which a plastic sealer can be obtained without using a plastic mold.
［発明の構成］
（課題を解決するための手段）
本発明は、絶縁性基板及びこの絶縁性基板上に実装され
る電子部品とを有する回路基板と、前記回路基板を外包
する樹脂外囲器とを備えた混成集積回路基板において、
前記電子部品の直下の絶縁性基板に貫通穴が形成されて
いることを特徴とする混成集積回路基板である。[Structure of the Invention] (Means for Solving the Problems) The present invention provides a circuit board having an insulating substrate and an electronic component mounted on the insulating substrate, and a resin envelope enclosing the circuit board. In a hybrid integrated circuit board having
The hybrid integrated circuit board is characterized in that a through hole is formed in the insulating substrate directly below the electronic component.
本発明において、貫通穴の大きさは空気が通過できる程
度であればよい。また、その位置はＦＰ型ＩＣ，ＤＩＰ
型ＩＣ，ＳＩＰ型ＩＣ，抵抗体等の電子部品の裏面側の
基板部分（特に中心部が良い）が良い。更に、貫通穴の
数は特に限定されない。In the present invention, the size of the through hole may be just large enough to allow air to pass through. Also, its position is FP type IC, DIP
Parts of the substrate on the back side of electronic components such as type ICs, SIP type ICs, and resistors (particularly the center part are good) are suitable. Furthermore, the number of through holes is not particularly limited.
（作用）
本発明においては、電子部品が位置する絶縁性基板部分
に貫通穴を設けた状態で浸漬処理をすることにより、絶
縁性基板が浸漬状態にある時には空気にとって天井とな
る為空気が残留するが、電子部品の裏側の基板部分には
貫通穴が形成されているため、基板を下降させてモール
ド樹脂液中に浸漬する際、残留した空気か貫通穴を通っ
て上方に排気され、ＦＰ型ＩＣの裏側にもモールド樹脂
が完全に充填される。従って、従来のようにピンホール
などのない信頼性の高い混成集積回路基板を得ることが
できる。(Function) In the present invention, by performing immersion treatment with through holes provided in the insulating substrate portion where electronic components are located, when the insulating substrate is immersed, it becomes a ceiling for air, so air remains. However, since a through-hole is formed in the board part on the back side of the electronic component, when the board is lowered and immersed in the molding resin liquid, the remaining air is exhausted upward through the through-hole, and the FP The back side of the molded IC is also completely filled with molding resin. Therefore, it is possible to obtain a highly reliable hybrid integrated circuit board that is free from pinholes and the like as in the prior art.
（実施例）
以下、本発明の一実施例を製造工程順に第１図（Ａ）、
（Ｂ）を参照して説明する。(Example) Hereinafter, an example of the present invention will be explained in the order of manufacturing steps as shown in FIG.
This will be explained with reference to (B).
まず、絶縁性基板１１の後記ＦＰ型ＩＣの中心部に対応
する直下に例えばφ０．５ｍｍの貫通穴１２を形成した
後、前記基板１１の両面に導体パターン１３を形成する
。次に、前記基板１１にＦＰ型ＩＣ１４やチップ部品等
の電子部品１５をリフロー半田付は等により前記導体パ
ターンに１３に接続させて実装する。つづいて、前記基
板１１の対向する両端部に、複数個のリード端子１６を
前記基板を把持するように取り付ける（第１図（Ａ）図
示）。First, a through hole 12 having a diameter of 0.5 mm, for example, is formed directly under the insulating substrate 11 corresponding to the center of the FP type IC described later, and then conductive patterns 13 are formed on both surfaces of the substrate 11. Next, electronic components 15 such as FP type ICs 14 and chip components are mounted on the substrate 11 by being connected to the conductive patterns 13 by reflow soldering or the like. Subsequently, a plurality of lead terminals 16 are attached to opposite ends of the substrate 11 so as to grip the substrate (as shown in FIG. 1(A)).
前記絶縁性基板１１を、リード端子１Ｂの先端を上部に
向けて例えばエポキシ変性フェノール樹脂等のモールド
樹脂液中に徐々に降下し、浸漬する。The insulating substrate 11 is gradually lowered into a molding resin solution such as epoxy-modified phenol resin, with the tips of the lead terminals 1B facing upward, and immersed.
次に、基板１１を引き上げることにより、絶縁性基板１
１．ＩＣ１４，電子部品１５を囲むような樹脂層を被覆
する。この後、前記基板を加熱１処理して樹脂層を硬化
し、樹脂封止器１７を形成する（第１図（Ｂ）図示）。Next, by pulling up the substrate 11, the insulating substrate 1
1. A resin layer surrounding the IC 14 and electronic components 15 is coated. Thereafter, the substrate is heated to cure the resin layer to form a resin sealer 17 (as shown in FIG. 1B).
しかして、上記実施例に係る混成集積回路基板の外装方
法によれば、予め絶縁性基板１１の所定の位置に樹脂通
過用の貫通穴１２を設けて基板１１をモールド樹脂液中
に浸漬し、引上げ、加熱処理することにより、絶縁性基
板１１に搭載されたＦＰ型ＩＣ１４，チップ部品等の電
子部品１５や導体パターン１３を気密に樹脂封止する樹
脂封止器１７を形成することができる。つまり、絶縁性
基板１１が浸漬状態にある時には空気にとって天井とな
る為空気が残留する。しかし、ＦＰ型ＩＣＪ４の裏側の
基板１１部分には貫通穴１２が形成されているため、基
板１１を下降させてモールド樹脂液中に浸漬する際、残
留した空気が貫通穴１２を通って上方に排気され、ＦＰ
型ＩＣ１４の裏側にもモールド樹脂が完全に充填される
。従って、従来のようにピンホールなどのない信頼性の
高い混成集積回路基板を得ることができる。According to the method for packaging a hybrid integrated circuit board according to the above embodiment, a through hole 12 for resin passage is provided in advance at a predetermined position of the insulating substrate 11, and the substrate 11 is immersed in a molding resin liquid. By pulling up and heat-treating, it is possible to form a resin sealer 17 that hermetically seals the FP type IC 14 mounted on the insulating substrate 11, the electronic components 15 such as chip components, and the conductive pattern 13 with resin. That is, when the insulating substrate 11 is in an immersed state, it acts as a ceiling for air, so air remains. However, since a through hole 12 is formed in the substrate 11 portion on the back side of the FP type ICJ4, when the substrate 11 is lowered and immersed in the molding resin liquid, the remaining air passes through the through hole 12 and flows upward. Exhausted, FP
The back side of the mold IC 14 is also completely filled with mold resin. Therefore, it is possible to obtain a highly reliable hybrid integrated circuit board that is free from pinholes and the like as in the prior art.
［発明の効果］
以上詳述した如く本発明によれば、絶縁性基板に樹脂封
止画形成用の樹脂の一部を流すための貫通穴を設けるこ
とにより、ピンホールのない外囲器が得られ、生産性が
向上でき信頼性の高い混成集積回路基板を提供できる。[Effects of the Invention] As detailed above, according to the present invention, by providing a through hole in an insulating substrate through which a part of the resin for forming a resin-sealed image flows, an envelope without pinholes can be obtained. This makes it possible to improve productivity and provide a highly reliable hybrid integrated circuit board.
第１図は本発明の一実施例に係る混成集積回路基板を製
造工程順に示す断面図、第２図は従来の混成集積回路基
板を製造工程順に示す断面図である。
１１・・・絶縁性基板、１２・・・貫通穴、１３・−・
導体パターン、１４・・・チップ部品、１５・・・電子
部品、１６・・・リード端子、１７・・・樹脂封止器。
出願人代理人 弁理士 鈴江武彦
第
図FIG. 1 is a sectional view showing a hybrid integrated circuit board according to an embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is a sectional view showing a conventional hybrid integrated circuit board in the order of manufacturing steps. 11... Insulating substrate, 12... Through hole, 13...
Conductor pattern, 14... Chip component, 15... Electronic component, 16... Lead terminal, 17... Resin sealer. Applicant's agent Patent attorney Takehiko Suzue
Claims (1)
とを有する回路基板と、前記回路基板を外包する樹脂封
止器とを備えた混成集積回路基板において、前記電子部
品の直下の絶縁性基板に貫通穴が形成されていることを
特徴とする混成集積回路基板。In a hybrid integrated circuit board comprising a circuit board having an insulating substrate and an electronic component mounted on the insulating substrate, and a resin sealer enclosing the circuit board, the insulating property immediately below the electronic component A hybrid integrated circuit board characterized by having a through hole formed in the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25913990A JPH04137657A (en) | 1990-09-28 | 1990-09-28 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25913990A JPH04137657A (en) | 1990-09-28 | 1990-09-28 | Hybrid integrated circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04137657A true JPH04137657A (en) | 1992-05-12 |
Family
ID=17329870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25913990A Pending JPH04137657A (en) | 1990-09-28 | 1990-09-28 | Hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04137657A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013069942A (en) * | 2011-09-24 | 2013-04-18 | Denso Corp | Semiconductor device and manufacturing method of the same |
| JP2014203870A (en) * | 2013-04-02 | 2014-10-27 | 三菱電機株式会社 | Method for manufacturing semiconductor device and semiconductor device |
-
1990
- 1990-09-28 JP JP25913990A patent/JPH04137657A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013069942A (en) * | 2011-09-24 | 2013-04-18 | Denso Corp | Semiconductor device and manufacturing method of the same |
| JP2014203870A (en) * | 2013-04-02 | 2014-10-27 | 三菱電機株式会社 | Method for manufacturing semiconductor device and semiconductor device |
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