JPH0288335U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 shows an analog
FIG. 2 is a circuit diagram of a digital converter, FIG. 2 is a signal waveform diagram of each part of the circuit of FIG. 1, and FIG. 3 is an explanatory diagram showing the configuration and input/output characteristics of a correction data memory. 1 is an input signal source, 3 is an operational amplifier, 4 is an integrator capacitor, 6 is a comparator, 7 is an AND gate, 8 is a first counter, 9 is a correction data memory, 10 is an AND gate, 12 is a second counter .

Claims (1)

[Claims for Utility Model Registration] (1) An integrator that integrates a reference signal, a comparator that compares the output of this integrator with an input signal voltage input from the outside, and an output of the integrator that is connected to the input signal A first counter that counts clock pulses generated within a period until the voltage reaches the voltage, and a correction data memory that uses the output of the first counter as an address input and serially outputs pre-stored nonlinear correction data bit by bit. , a second counter that outputs an output signal linearly corrected according to the nonlinear correction data when the output of the integrator reaches the input signal voltage.
Digital converter. (2) The analog-to-digital converter according to claim (1), wherein the correction data memory is an electrically rewritable memory (PROM).