JPS589093U

JPS589093U - Pulse width modulation inverter

Info

Publication number: JPS589093U
Application number: JP10216881U
Authority: JP
Inventors: 鬼頭　恭民
Original assignee: 株式会社明電舎
Priority date: 1981-07-09
Filing date: 1981-07-09
Publication date: 1983-01-20

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１甲は本考案の一実施例を示すパルス幅変調方式イン
バータの要部回路図、第２図は第１図における正弦波変
換回路２と正弦波変換指令回路４の一実施例を示す回路
図、第３図及び第４図は第２図の各部動作を説明するた
めの波形図である。　　−１・・・周波数設定器、２・
・・正弦波変換回路、４・・・正弦波変換指令回路、５
・・・搬送波発生回路、６Ｕ。６ｖ、６ｗ・・・コンパレータ、７・・・カウンタ、８
・・・リード第２ンリーメモリ、９・・・デコーダ、１
０・・・補助アンプ。1A is a circuit diagram of a main part of a pulse width modulation type inverter showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the sine wave conversion circuit 2 and the sine wave conversion command circuit 4 in FIG. 3, and 4 are waveform diagrams for explaining the operation of each part in FIG. 2. -1...Frequency setter, 2.
... Sine wave conversion circuit, 4... Sine wave conversion command circuit, 5
...Carrier wave generation circuit, 6U. 6v, 6w...Comparator, 7...Counter, 8
...Read 2nd memory, 9...Decoder, 1
0... Auxiliary amplifier.

Claims

[Scope of utility model registration request]

a counter that receives a frequency signal proportional to the inverter output frequency setting value as a counting input; a memory that sequentially outputs sine wave sample value data and phase sequence data including each phase polarity using the count value of this counter as an address signal; A digital-to-analog conversion circuit that uses sine wave sample value data as a digital-to-analog conversion input and outputs an address signal proportional to the inverter output frequency setting value, and the analog output of this digital-to-analog conversion circuit and its inverted signal are common. A pulse width modulated pulse signal is obtained by comparing a sine wave output of each phase obtained in the sample and hold circuit and a carrier wave, comprising a sample and hold circuit that memorizes the level of each phase using the above-mentioned phase sequence data as an input. Width modulation inverter.