JPS6045535U

JPS6045535U - Analog/digital conversion circuit

Info

Publication number: JPS6045535U
Application number: JP13726283U
Authority: JP
Inventors: 三樹阿部; 幸也田中
Original assignee: ソニー株式会社
Priority date: 1983-09-06
Filing date: 1983-09-06
Publication date: 1985-03-30
Also published as: JPH0212755Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案が適用される積分型のアナログ／デジタ
ル変換回路の構成を示す回路図、第２図は上記アナログ
／デジタル変換回路の動作を示すタイムチャート、第３
図は所定の入力電圧を越えるアナログ信号が入力された
場合の復元波形を示す模式図である。第４図は、米考案
に係るアナログ／デジタル変換回路の一実施例における
カウンタ部の基本構成を示す論理回路図である。１・・・信号入力端子、２，４・・・抵抗、３・・・第
１のスイッチ、５・・・コンデンサ、６・・・演算増幅
器、７・・・第２のスイン≠、８・・・定電流源、９・
・・比較器、１０・・・電源、１１・・・タイミングコ
ントロール回路、１４・・・信号出力端子、２０・・・
サンプルホールド回路、３１〜３８・・・データ用カウ
ンタ、３９・・・アンダーフロー処理用カウンタ、４０
・・・オーバーフロー処理用カウンタ、４１〜４８・・
・アンダーフロー処理用ＡＮＤゲート、５１〜５８・・
・オーバーフロー処理用ＯＲゲート。FIG. 1 is a circuit diagram showing the configuration of an integral type analog/digital conversion circuit to which the present invention is applied, FIG. 2 is a time chart showing the operation of the analog/digital conversion circuit, and FIG.
The figure is a schematic diagram showing a restored waveform when an analog signal exceeding a predetermined input voltage is input. FIG. 4 is a logic circuit diagram showing the basic configuration of a counter section in an embodiment of the analog/digital conversion circuit according to the American invention. DESCRIPTION OF SYMBOLS 1... Signal input terminal, 2, 4... Resistor, 3... First switch, 5... Capacitor, 6... Operational amplifier, 7... Second switch ≠, 8...・・Constant current source, 9・
... Comparator, 10... Power supply, 11... Timing control circuit, 14... Signal output terminal, 20...
Sample hold circuit, 31-38... Data counter, 39... Underflow processing counter, 40
...Overflow processing counter, 41 to 48...
・AND gate for underflow processing, 51 to 58...
・OR gate for overflow processing.

Claims

[Scope of utility model registration request]

A feedback sample-and-hold circuit samples and holds an input analog signal connected to a signal input terminal and forms a sample-and-hold output with a pulse width corresponding to the signal level, and the counting period is controlled by the sample-and-hold output. A data counter that forms n-bit data indicating the pulse width, a 2-bit counter that counts the output of the most significant digit of this data counter, and gate-controlled data from the data counter that is gate-controlled by the counting output of this 2-bit counter. and a gate circuit for supplying n-bit data to a signal output terminal, and supplying offset data to the data counter corresponding to a transition period of a sample and hold operation in the feedback sample and hold 1 circuit to the data counter. The above sample 1 for each sampling period.
An analog/digital conversion circuit characterized in that it performs a counting operation according to the hold output.