JPH0287645A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0287645A
JPH0287645A JP24143188A JP24143188A JPH0287645A JP H0287645 A JPH0287645 A JP H0287645A JP 24143188 A JP24143188 A JP 24143188A JP 24143188 A JP24143188 A JP 24143188A JP H0287645 A JPH0287645 A JP H0287645A
Authority
JP
Japan
Prior art keywords
evaluation
dry etching
measured
etching operation
damage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24143188A
Other languages
Japanese (ja)
Inventor
Tomoaki Hirokawa
廣川 友明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24143188A priority Critical patent/JPH0287645A/en
Publication of JPH0287645A publication Critical patent/JPH0287645A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To accurately evaluate an influence of damage caused to an actual device by a method wherein a hole measurement is used when the damage of a dry etching operation is evaluated. CONSTITUTION:An evaluation element is constituted of an electrode part 1 composed of an Au/Ge/Ni metal and an active-layer part 2; when a substrate 3 is formed of GaAs, the active layer 2 is formed by an annealing operation after Si ions have been implanted. An evaluation operation is executed by the following procedure. The evaluation element is measured before a dry etching operation is executed; a reference data is obtained. Then, the evaluation element is dry-etched as it is. This dry etching operation is usually executed for about five minutes. The element is measured as it is without post-treatment. After the element has been measured, it is heat treated properly. The element is measured again. A ratio of this data to an initially measured result is used as an evaluation value of damage caused by the dry etching operation.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造評価法に関し、特にGaA
s等化合物半導体装置でのドライエツチングのタメージ
評価に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing and evaluating semiconductor devices, particularly for GaA
This paper relates to damage evaluation of dry etching in compound semiconductor devices such as S.

〔従来の技術〕[Conventional technology]

従来、この種の評価では、ドライエツチング面への金属
ショットキー特性やフォトルミネッセンスによる結晶評
価を行なっていた。
Conventionally, in this type of evaluation, crystal evaluation was performed based on metal Schottky characteristics or photoluminescence on a dry etched surface.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の評価では、金属ショットキー特性評価で
は活性層濃度が低い場合に正確な評価を行なうのが困難
であり、またフォトルミネッセンスの評価では定量的評
価が困難であるという欠点がある。
The conventional evaluation described above has drawbacks in that it is difficult to perform accurate evaluation when the active layer concentration is low in metal Schottky characteristic evaluation, and it is difficult to perform quantitative evaluation in photoluminescence evaluation.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は特に化合物半導体装置の製造でのドライエツチ
ングのダメージの評価において、ホール測定を行うこと
を特徴として有している。
The present invention is particularly characterized in that hole measurements are performed in evaluating damage caused by dry etching in the manufacture of compound semiconductor devices.

〔実施例〕〔Example〕

次に、本発明を図面を参照してより詳細に説明する。 Next, the present invention will be explained in more detail with reference to the drawings.

第1図に本発明の一実施例の図を示した。評価素子は、
A u / G e / N i金属から成る電極部1
と活性層部2から構成されており、活性層2は、基板3
がGaAsである場合、Siイオン注入を40 k e
v〜50 k eVの注入エネルギー4〜5X 10 
”/cntのドースで行なった後、800℃のアニール
を行い形成する。評価は次の手順に従う。
FIG. 1 shows a diagram of an embodiment of the present invention. The evaluation element is
Electrode part 1 made of A u / G e / Ni metal
and an active layer part 2, and the active layer 2 is composed of a substrate 3 and an active layer part 2.
is GaAs, Si ion implantation is performed at 40 k e
Injection energy 4-5X 10 of v~50 k eV
After conducting at a dose of "/cnt", annealing is performed at 800° C. to form the film.Evaluation is performed according to the following procedure.

■評価素子をドライエツチング前に測定し基準データー
とする。■次に評価素子をそのままドライエツチングを
行う。ドライエツチングは通常約5分間行う。■そのま
ま後処理なしで測定を行う。
■Measure the evaluation element before dry etching and use it as reference data. ■Next, dry etching is performed on the evaluation element as it is. Dry etching usually takes about 5 minutes. ■Measurements can be made without any post-processing.

■、■の測定径適当な熱処理(〜400℃)を行う。■
再度測定を行う。通常■の測定では測定不可能であるが
■の熱処理によりダメージが熱回復し、■の測定で測定
が可能となる。■のデーターの■の測定結果に対する比
をドライエツチングダメージの評価値とする。
Measurement diameters (1) and (2) Appropriate heat treatment (~400°C) is performed. ■
Measure again. Normally, it is impossible to measure by the measurement of (■), but the damage is thermally recovered by the heat treatment (■), and measurement is possible by the measurement of (■). The ratio of the data in (2) to the measurement result in (2) is taken as the evaluation value of dry etching damage.

この実施例の代表的評価データーを第2図に示した。同
図中N s/ N soは■で測定したデーター値の■
の測定結果に対する比(=ダメージ回復率)であり、こ
の値のプロセスパラメーター(例えばrf power
)依存性を調べることにより、素子へ与える影響を定量
的かつ正確に推定することが可能となる。
Representative evaluation data for this example is shown in FIG. In the same figure, N s / N so is the data value measured in ■■
is the ratio of the measured value (=damage recovery rate) to the measurement result of the process parameter (e.g.
) By investigating the dependence, it becomes possible to quantitatively and accurately estimate the influence on the element.

第3図は本発明の他の実施例で本評価素子は半絶縁性G
aAs基板5に活性層4のみのホールパターンを形成し
たものである。この実施例ではオーミック電極部を有し
ないため、ドライエツチング後のダメージ回復アニール
が400℃以上の高温とすることができ、800℃前後
のアニールでの回復率を評価することができる。オーミ
ック電極はダメージ回復アニール後In金属によりコン
タクトを取る。ドライエツチング面にオーミックコンタ
クトを取る場合コンタクト抵抗が著しく増加する場合が
あり、このためコンタクト電極部にはドライエツチング
前にフォト・レジスト等による保護膜を付けることが必
要である。
Figure 3 shows another embodiment of the present invention, in which the evaluation element is a semi-insulating G
A hole pattern of only the active layer 4 is formed on the aAs substrate 5. Since this example does not have an ohmic electrode portion, damage recovery annealing after dry etching can be performed at a high temperature of 400°C or higher, and the recovery rate at annealing at around 800°C can be evaluated. The ohmic electrode is contacted with In metal after damage recovery annealing. When making an ohmic contact on the dry-etched surface, the contact resistance may increase significantly, so it is necessary to apply a protective film such as photoresist to the contact electrode portion before dry-etching.

〔発明の効果〕〔Effect of the invention〕

本発明は、従来の評価方法とは異なり、ドライエツチン
グのダメージ評価においてホール測定を用いることによ
り正確かつ定量的に評価を行うことができる効果があり
、実デバイスへ与えるダメージの影響を正確に評価する
ことが可能である。
Unlike conventional evaluation methods, the present invention has the advantage of being able to accurately and quantitatively evaluate damage caused by dry etching by using Hall measurement, thereby accurately evaluating the effects of damage on actual devices. It is possible to do so.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第3図はそれぞれ本発明の実施例を示す平
面図であり、第2図は第1図の実施例の評価データ例を
示すグラフである。 1・・・・・・A u / G e / N iから成
るオーミック電極部、2・・・・・・活性層部、3・・
・・・・半絶縁性G a A s基板、4・・・・・・
活性層部、5・・・・・・半絶縁性G a A s基板
。 代理人 弁理士  内 原   晋 、61m 第3図
1 and 3 are plan views each showing an embodiment of the present invention, and FIG. 2 is a graph showing an example of evaluation data for the embodiment of FIG. 1. 1... Ohmic electrode part consisting of A u / G e / Ni, 2... Active layer part, 3...
...Semi-insulating GaAs substrate, 4...
Active layer portion, 5...Semi-insulating GaAs substrate. Agent: Susumu Uchihara, 61m Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の製造でのドライエッチングのダメージをホ
ール測定を利用して評価することを特徴とする半導体装
置の製造方法。
A method for manufacturing a semiconductor device, characterized in that damage caused by dry etching in manufacturing the semiconductor device is evaluated using Hall measurement.
JP24143188A 1988-09-26 1988-09-26 Manufacture of semiconductor device Pending JPH0287645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24143188A JPH0287645A (en) 1988-09-26 1988-09-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24143188A JPH0287645A (en) 1988-09-26 1988-09-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0287645A true JPH0287645A (en) 1990-03-28

Family

ID=17074198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24143188A Pending JPH0287645A (en) 1988-09-26 1988-09-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0287645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786360A (en) * 1993-09-17 1995-03-31 Nec Corp Evaluating method for etching damage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786360A (en) * 1993-09-17 1995-03-31 Nec Corp Evaluating method for etching damage

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