JPS6049674A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To estimate the characteristics of FETs with high accuracy in a manufacturing process for a semiconductor by mutually forming channel regions for the FET as a circuit element and the FET as a monitor element equally onto a semiconductor base body. CONSTITUTION:A resist film is formed onto a semi-insulating GaAs substrate 21, and Si ions are implanted to regions 23a, 23b. A resist film 24 is formed and openings are shaped onto a source region 25 and a drain region 26 for a monitor element, and Se ions are implanted. A Schottky junction is formed between the N type regions 23a and 23b. Gate electrodes 28a and 28b in the same size for a circuit element and the monitor element and a source electrode 29 and a drain electrode 30 for the monitor element are formed. The characteristics of the monitor element can be measured under the state. Si<+> ions are implanted into a source region 32 and a drain region 33 for the circuit element and a region 34 and a region 35 for the monitor element to activate them. The characteristics can be measured again at the point of time.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, particularly a semiconductor device that can be effectively monitored during the manufacturing process of a semiconductor device including a gallium arsenide Schottky junction field effect transistor. The present invention relates to the structure and manufacturing method of the device.

(b) Background of the technology Semiconductor devices are becoming faster with the aim of further improving the performance and cost performance of electronic computers.

2. Description of the Related Art Lower power consumption and higher integration are being promoted, and many semiconductor devices have been proposed that use compound semiconductors, particularly gallium arsenide (G a A a), which have much higher carrier mobility than silicon (St).

Due to the short lifetime of minority carriers in compound semiconductors, field effect transistors (hereinafter abbreviated as F'ET) are currently the main target of development. Utilizing the advantage that stray capacitance can be reduced by using FETs, 115' Toki junction type or PN junction type FETs have become mainstream, and integrated circuit devices (hereinafter abbreviated as IC) using these FETs as elements have become mainstream. ) is expected to be put into practical use as soon as possible.

(c) Conventional technology and problems Gallium arsenide Schottky junction FET (hereinafter referred to as GaAs
The MES FET (abbreviated as MES FET) has already been put into practical use as a single transistor, for example, for amplification in the microwave band, but as mentioned earlier, it is considered to be the mainstream transistor element for forming compound semiconductor ICs. ing.

High speed for GaAs MES FET used as IC element.

Although a high degree of integration is naturally required, it is especially important that the transconductance is large and the variation in gate threshold voltage is small.

In order to realize such characteristics, GaAs ICs have conventionally been manufactured in the following manner.

Referring to FIG. 1(a), a photoresist film 2 is provided on a semi-insulating GaAs substrate 1, and an opening is formed in the F'ET formation region.
Sl) ions at a dose of 2 x 1 at 60 (KeV)
0''[i is implanted into region 3.

Refer to FIG. 1(b), the photoresist film 2 is peeled off and silicon dioxide (Si) is removed.
For example, a film 4 made of
l: ] Heat treatment is performed for 15 to 20 minutes to reduce the carrier concentration of the region 3 to 1×10'7 [crf3
] to an n-type region.

Note that this heat treatment may not be performed and the Si + ions in the region 3 may be activated by a heat treatment in a later step.

After removing the slow film 4 (see FIG. 1(c)), a gate material such as tungsten silicide (WSi) is deposited on the GaAa substrate 1 by magnetron sputtering or the like, and the gate electrode 5 is formed by reactive ion etching or the like. Form.

FIG. 1 (dl reference field region is covered with a mask 6 made of photoresist or stow, etc., and Si + ions are
[KeV] is implanted into the region 7 at a dose of about 2×10” [m→].

FIG. 1 (see el) After removing the mask 6, a stow film 8 is provided, and heat treatment is performed at a temperature of, for example, 800 [° C.] for about 9 hours and 10 to 15 minutes, so that the region 7 has a carrier concentration of 1-4=×10111 CI. An n-type region of about -F31 is used.This region 7 is a source and drain region.

Refer to FIG. 1(f), the StO film 8 is removed and the thickness is increased to 0.4 μm, for example.
m] of about 810. A membrane 9 is provided. Next, openings for forming source and drain electrodes are formed in the SIO film 9 using a resist mask 10.

Refer to FIG. 1(g). Ohmic contact metal materials with the n-type GaAs semiconductor, such as gold/germanium (Aura) and gold (Au), are used at 0.000.
After about 4 [μm] of vapor deposition, the resist mask 10 is peeled off. Next, culmification is performed at a temperature of 400[° C.] for one time to form a source electrode 11 and a drain electrode 12.

Figure 1 Ch) A stow film 9' with a thickness of 0.4 [μm] is used as a reference interlayer insulating film.
Openings for wiring connections such as a source electrode 11, a drain electrode 12, and a gate connection region (not shown) are provided.

Referring to FIG. 1(i), for example, titanium (Ti)-platinum (pt)-gold (Au) is deposited and patterned to form the required wiring 13.

In the conventional manufacturing method of an IC using GaAs MES FET as an element as explained above, GaAs MESFET
It is possible to monitor whether the characteristics of the ET element satisfy the specifications only after the opening shown in FIG. 1(h) is provided. That is, at an appropriate position on the GaAs substrate 1, a monitor element with a contact area of, for example, about 100 [μm] for each electrode is formed at the same time as the original FET element, and its characteristics are measured after the aforementioned point in time. ing.

However, GaAs ICs still have a high defect rate due to variations in the GaAs substrate 1, and many defects are detected at one point in the monitor. At this point in time, most of the IC manufacturing process has already been completed, resulting in a significant loss of time and materials, and there is a need for a manufacturing method that monitors the process at an earlier point in time.

(d) Purpose of the Invention The present invention provides a structure and manufacturing method that enables monitoring to estimate the characteristics obtained at an early stage in the manufacturing process of an IC using a GaAs MKS FET, special number ζ as a circuit element. With the goal.

(e) Structure of the Invention The object of the present invention is to provide a circuit element and a monitor element of a Schottky junction field effect transistor on a compound semiconductor substrate, wherein the monitor element is connected to the source and drain regions of the circuit element. This is achieved by a semiconductor device comprising source and drain regions having a carrier concentration equal to or higher than , and source and drain electrodes made of the same material as the gate electrodes of the circuit element and monitor element.

Furthermore, the object of the present invention is to provide a gallium arsenide semiconductor substrate with:
The channel regions of the field effect transistor as a circuit element and the field effect transistor as a monitor element are formed to be equal to each other, and the source and drain regions of the monitor element 7- are equal to the source and drain regions to be formed in the circuit element. By using a material that is formed to have a carrier concentration of the above level and forms a silicon junction with the channel region, a mutually equivalent gate electrode is formed on the channel region of the circuit element and the monitor element. A semiconductor device, wherein a source electrode is disposed on the source region of the monitor element, and a drain electrode is disposed on the drain region, and a measurement probe is applied to a contact area of each electrode of the monitor element to measure the characteristics of the monitor element. This is achieved by the manufacturing method.

Note that the characteristics of the monitor element according to the manufacturing method of the present invention are measured by forming the source and drain regions of the circuit element by aligning the positions with the gate electrode, and forming the source and drain regions of the circuit element by aligning the positions with the gate electrode in the monitor element. The characteristics of a field effect transistor used as a circuit element are improved by forming a region in contact with each of the channel region, the source region, and the drain region and having a carrier concentration equivalent to that of the source and drain regions of the circuit element. 8- can be estimated with high probability.

Furthermore, by measuring the characteristics of the monitor element prior to forming the source and drain regions of the circuit element,
The characteristics of a field effect transistor used as a circuit element can be estimated at the earliest point in time.

However, the monitor element is, for example, within the chip,
EMBODIMENTS OF THE INVENTION The present invention will be specifically explained below using examples with reference to the drawings.

FIG. 2(a) is a plan view showing an example of a field effect transistor used as a monitor element in an embodiment of the present invention, and FIG. 2(b) is a sectional view showing an X-Y cross section thereof. In the figure, 21
is a semi-insulating GaAs substrate, 23b is an n-type channel region,
25 is an n+ type source region, 26 is an n+ type drain region,
28b is a gate electrode, 29 is a source electrode, 30 is a drain electrode, and 34 and 35 are n medium-sized regions formed to be equivalent to the source and drain regions of the circuit element. Each electrode 28b, 29 and 30 has a side length of about 100 [μRaku].
There is a contact area of approximately

Further, FIGS. 3(&) to (f) are cross-sectional views showing characteristic parts of the embodiment of the present invention, in which area A is a circuit element F.
ET, area B indicates the FET used as a monitor element, and parts of the pixel element that are formed at the same time under the same conditions and have the same function are designated by the same numerals, with the suffix a for the former and the suffix for the latter. do.

Refer to FIG. 3(a). A 7-hole photoresist film 22 is provided on a semi-insulating GaAs substrate 21, an opening is formed in the pixel formation region, and, for example, SL+ ions are applied at 60 (KeV) at a dose of 2 OI! [-] It is implanted into regions 23a and 23b to a certain extent.

Refer to FIG. 3(b), a photoresist film 24 is provided, openings are formed on the source region 25 and drain region 26 of the monitor element, and selenium (Se) ions are irradiated with, for example, selenium (Se) ions at a dose of 5 at 100 CKeV).
X 10''Cenr'3. However, the distance between the source region 25 and the drain region 26 is made larger than the gate length of the circuit element, and in this embodiment, this distance is approximately 3 [μm].

Referring to FIG. 3(c), the stow film 27 is removed by peeling off the stow film 27, and heat treatment is performed at, for example, a temperature of 850 (°C) for 15 to 20 minutes, and the source region 25 and drain region 26 of the monitor element are heated. Carrier concentration 5 x 10” [tmrs]
The region 23b and the circuit element region 23& which are not included in this are made of n type with a carrier concentration of 1×10 17 (
cIrr'! It is of n-type.

After removing the 5102 film 27 (see FIG. 3(d)), a Schottky junction is formed between the n-type regions 23a and 23b, and this characteristic is maintained even after the heat treatment described later. A gate material such as WSl is deposited by magnetron sputtering or the like, and gate electrodes 28a and 28b of the same size are formed on the circuit element and the monitor element, and source electrodes 29 and 28b of the monitor element are formed by reactive ion etching or the like. A drain electrode 30 is formed. However, the source electrode 29 and the drain 30 are formed with the exposed portions of the source region 25 and drain region 26 remaining on the gate electrode 28b side. In this embodiment, the gate length of the gate electrodes 28a and 28b is approximately 1 [μm], and the length of the source electrode 29 and the drain electrode 3 is approximately 1 [μm].
The distance from 0 is approximately 7 [μm].

In this state, the gate electrode 28b, the source electrode 29
The characteristics of the monitor element can be measured by applying a measurement probe to each contact area of the drain electrode 30 (see FIG. 2(a)). This characteristic will be explained in detail later.

Referring to FIG. 3(e), a mask 31 made of photoresist or sio, etc. and covering the field area is provided to remove, for example, 2 ions of Sl ions.
00 [KeV] with a dose of 2 x 1013 [6n-
The source region 32 of the circuit element is approximately ○. drain region 3
3. It is implanted into a region 34 between the gate electrode 28b and the source electrode 12-29 and a region 35 between the gate electrode 28b and the drain electrode 30 of the monitor element.

Refer to FIG. 3(f). After removing the mask 31, a 5ift film (not shown) is provided, for example, at a temperature of s o o (°C) for a time of 1.
The implanted Sl ions are activated by heat treatment for about 0 to 15 minutes, and the source region 3 of the circuit element is heated.
2. Drain region 33. and said area 3 of the monitor element.
4 and 35 n+ type source region 25 and drain region 2
The portion not included in 6 is the carrier concentration I x 10''
[N-type with about cni5.

After that, the stow film is removed. At this point, the characteristics of the monitor element can be measured again. At this point, a channel structure equivalent to that of the completed circuit element is formed in the monitor element, so that a more accurate judgment can be made than at the monitor point. The work-in-process product that has been processed based on this judgment is then subjected to the manufacturing process using the conventional technology, for example, as described in the prior art example with reference to FIGS. 1(f) to (1).

It is also possible to use a manufacturing method carried out by In this case, the characteristics of the monitor element are measured at the time of the second measurement in the above embodiment.

An example of comparison between the characteristics of the monitor element in the above embodiment and the characteristics of an equivalent circuit element on the same board after completion is shown in FIG. 4(a).
Shown in to (c).

FIG. 4(a) shows the time of measuring the characteristics of the first monitor element, that is, n+ which is equivalent to the source and drain regions of the circuit element.
Monitor element before forming mold regions 34 and 35, (b) shows the second
(c) is the drain voltage V at the time of measurement of the monitor element, that is, after the formation of the n+ type regions 4 and 35, and (c) is the same circuit element at the time of completion.
An example will be shown in which the DS-drain current ID characteristics were measured using the gate voltage VG as a parameter. However, drain current ID
are converted per gate width and displayed as mutual relative values.

Note that the gate length of the monitor element and the circuit element is the same f
It is approximately 1 [μ course].

First, the characteristics of the monitor element shown in Fig. 4(b) ((+)
Compared to the characteristics of the circuit element shown in Figure 3, since Schittke junction material is used for the source electrode 29 and drain electrode 30 of the monitor element, the n+ type regions 25 and 26 in contact with these have an extremely high carrier concentration. The drain voltage VD is higher than that of the circuit element which is the original FET, although it has been increased.
Even if S is applied, the saturated drain current ID8B is still 3/4
It can be seen that although the shapes of the characteristic curves are quite different in the range where the drain voltage Vns is extremely low and the drain voltage Vns is very low, the two exhibit similar transfer characteristics for the drain voltage VD8 higher than this voltage range. In particular, the values of both gate threshold voltages are in good agreement.

Furthermore, the characteristics of the monitor element shown in FIG. 4(a) have a larger difference from those of the circuit element than those shown in FIG. 4(b), and the saturated drain current ID8S is about 1/2, The threshold voltages are matched.

Therefore, it is possible to know the gate threshold voltage vth of the target circuit element in advance from the characteristics of these monitor elements, and by determining the correlation between the characteristics of the monitor element and the circuit element in advance, the drain current ID58. ,)
Characteristics such as lance conductance gm and pinch-off voltage Vp can be estimated with high accuracy.

By estimating the characteristics of circuit elements at an early stage according to the present invention, (a) they are classified according to their characteristics, and subsequent manufacturing steps are selectively performed according to the purpose. (b) At the time of the first monitoring, the conditions for forming the source and drain regions of the circuit element, that is, the dose of impurities.

Adjust either the magnitude of acceleration energy, heat treatment temperature, or time. (c) At any monitoring point, the previous activation heat treatment is kept to a minimum, and the heat treatment is selectively performed again. By adopting methods such as
The characteristics of a semiconductor device including an aAs MES FET, particularly its variation and productivity, can be improved.

In the above embodiment, n+ with the highest carrier concentration
Although it is formed only in the type region monitoring element, when forming this n-type region, this high carrier concentration is applied to the source and drain regions of the circuit element only to the extent that it does not affect the gate region. By providing the n+ type region, it is possible to reduce the ohmic contact resistance and improve the characteristics.

(g) According to the present invention, as described in the detailed description of the invention, a GaAa MESFET
early in the manufacturing process of semiconductor devices including
It becomes possible to estimate the characteristics of the element with high accuracy, and the characteristics of the semiconductor device are improved.

This can have the effect of promoting improvements in productivity and process stability.

[Brief explanation of drawings]

FIGS. 1(a) to (1) are cross-sectional views showing an example of a method for manufacturing a GaAsMES FET, and FIGS. 2(a) and (b) are a plan view and a cross-sectional view showing an example of a monitor element in an embodiment of the present invention. 3(a) to 3(f) are cross-sectional views showing an embodiment of the characteristic portion of the present invention, and FIGS. 4(a) and 4(b) are sectional views of the monitor element of the above embodiment. (c
) is a diagram showing an example of the characteristics of a completed circuit element. In the figure, 21 is a semi-insulating GaAs substrate, 23& and 23b are nu channel regions, and 25 is an n+ monitor element.
26 is an n+ type drain region of the monitor element, 28a and 28b are gate electrodes, 29 is a source electrode of the monitor element, 30 is a drain electrode of the monitor element, and 32 is an n+ type source region of the circuit element. 33 is an n-type train region of the circuit element, and 34 and 35 are n-type train regions formed similarly to the source and drain regions of the circuit element.
Indicates type area. 19- 348- Kali

Claims (3)

[Claims] (1) A circuit element and a monitor element of a junction field effect transistor are provided on a compound semiconductor substrate, and the monitor element has a source and drain region having a carrier concentration equal to or higher than that of the source and drain regions of the circuit element. 1. A semiconductor device comprising: a drain region; and source and drain electrodes made of the same material as the gate electrodes of the circuit element and monitor element. (2) Channel regions of a field effect transistor as a circuit element and a field effect transistor as a monitor element are formed in a gallium arsenide semiconductor substrate to be equivalent to each other, and source and drain regions of the monitor element are formed in the circuit element. The channel regions of the circuit element and the monitor element are formed using a material having a carrier concentration equal to or higher than that of the source and drain regions, and a Schottky junction is formed between the source and drain regions. A source electrode is disposed on the gate electrode and the source region of the monitor element, and a drain electrode is disposed on the drain region, and a measurement probe is applied to the contact area of each electrode of the monitor element to measure the characteristics of the monitor element. 1. A method of manufacturing a semiconductor device, characterized in that: (3) The source and drain regions of the circuit element are formed in alignment with the gate electrode, and in the monitor element, the source and drain regions are aligned in alignment with the gate electrode and the gate electrode, and the channel region and the source region are formed in alignment with the gate electrode. Claim 2, characterized in that a region is formed in contact with each drain region and has a carrier concentration equivalent to that of the source and drain regions of the circuit element, and then the characteristic measurement is performed on the monitor element. A method for manufacturing a semiconductor device.