JPS60154674A - Manufacture of electronic device - Google Patents

Abstract

PURPOSE:To accurately form the width of a patterning layer like a gate electrode of a GaAs BGFET by containing the step of forming a desired patterning layer on a region including a recess by etching the rear portion formed with a film on the entire main surface of a substrate. CONSTITUTION:The first SiO2 film 5 extended between a source electrode 11 and a drain electrode 12 on the main surface of a GaAs substrate 1 is opened in width (d) by a fluoric acid etchant with a photoresist film 13 as a mask. The width (d) is longer than the gate length Lg of the formed gate electrode. Then, with the film 5 as a mask an ohmically contacting layer 3 and a channel layer 2 are etched by an etchant made of NH4OH:H2O2:H2O to form a recess 14. Thereafter, after the film 13 is removed, the substrate 1 is treated by a CVD method, and an insulating film 15 is formed on the main surface. Subsequently, the substrate 1 is anisotropically dry etched to selectively remove the film 15 of the main surface.

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to manufacturing technology for electronic manufacturing, and in particular to technology for manufacturing patterning layers such as wiring layers and electrodes with high dimensional accuracy and dimensional modification.
A Schottky barrier gate type gallium arsenide field effect transistor (hereinafter simply GaAs F
Also called ET. ) relates to effective technology that can be applied to the production of [Background Art] The electron mobility in a GaAs crystal is extremely high compared to the electron mobility in a silicon crystal due to the difference in its crystal structure. For this reason, GaAs FETs have much higher mutual conductance gm than silicon FETs of the same size, and the maximum oscillation frequency (fmax)
r Noise figure (NF) Power charge te (PG) Cutoff frequency (f
Excellent high frequency characteristics such as For this reason, conventionally, GaAs FETs mainly have 1. It is used in amplifiers at extremely high frequencies of GHz or higher. but,
In recent years, demands for higher performance and higher speed have been increasing. High performance and high speed of Schottky barrier G1~ type GaAsFET (hereinafter also referred to as GaAs5 BGFET) can be achieved by improving mutual conductance and reducing capacitance between G1 and source. This is generally known, for example, as described in the August 1975 issue of Electronic Materials, pages 57-6o. For this reason, as introduced in the above-mentioned literature, a short one with a length of 1 to 5 μrn has been developed. In addition, as a structure for reducing the parasitic resistance between the gate and the source, for example, electronic material April 1980 issue 74-7
As described on page 8, the n-GaAs channel layer formed on the main surface of the semi-insulating GaAs substrate is
- A so-called recessed structure has been developed in which only the electrode forming portion is made thinner. Also, source
In order to reduce the contact resistance of the drain electrode, the active layer portion where the source/drain electrodes are provided has a structure in which the impurity concentration is higher than that in the region that becomes the channel of the FET. 'Material t
) It has been developed as described in the April 1975 issue, page 83. On the other hand, the present applicant has also developed a GaAs S B G FET with an extremely short length of 0.5 pm. That is, this Goo 1-forming technique is applicable to semi-insulating GaAs
After sequentially depositing molybdenum (Mo) and gold (Au) as electrode materials on the Day 1 to electrode formation regions of the active layer provided on the main surface of the substrate, the Au layer and Ivlo Jvi were partially etched. Next, using this 1 μrn wide Au layer as a mask, side etching the Mo layer, which is the material of the lower layer 0,511
This is a technique to achieve a Goo length of m. However, the inventors have found that such a gate forming technique has the problem that it is difficult to control the amount of side etching of the Mo layer, and it is difficult to form a desired GooI length with high precision. Nisa Panta. In addition, in such a goo 1 formation technique, the goo 1 electrode made of Mo is covered with an Au layer and the amount of Mo side etching can be observed. It is not possible to determine whether it is present or not. As a result, with this Goo 1~ formation technique, measures such as gate length correction cannot be performed at the Goo 1~ formation stage, resulting in problems such as a decrease in yield and an increase in -J2 to product cost 1. has been clarified by the inventor. [Object of the Invention] An object of the present invention is to provide a technique for forming the width of a patterning layer such as an electrode in GaAs S 1'30 FET with high accuracy. Another object of the present invention is to provide a technique for forming a fine patterning layer. Another object of the present invention is to provide a technique in which the dimensions of the patterned layer can be modified during its manufacture. Furthermore, another object of the present invention is to apply the present invention to GaAs5BG.
It is an object of the present invention to provide a technology that can be applied to the formation of electrodes of FETs and provide GaAs S B G F E-r with excellent high frequency characteristics and high speed operation at a high yield. The above and other objects of the present invention and novel 4, +f
The features will become clear from the description in this specification and the accompanying drawings. [Summary of the Invention] A summary of representative inventions disclosed in this application is provided in fIfI95. The explanation is as follows. That is, GaAs5BGFET according to the present invention
-The electrode is formed by the following steps. (1) n'- provided on the main surface of an insulating GaAs substrate
The active layer of GaAs consisting of n is an active layer with an opening having a width (d) longer than the length of the active layer, and an O7 film (the first S).
A recess is formed by etching using the film (jO, , film) as a mask. At this time, the sides of the recess are connected to the active layer and the first S
It has an eave-like structure with the j0□ film. (2) GaAs by chemical vapor deposition (CVD),! ,
%, a second 5i02 film with good step coverage is formed over the entire main surface. (3) The GaAs substrate is subjected to anisotropic etching (dry etching) on its main surface side, and a second SiO
□The membrane is removed. At this time, due to anisotropic etching,
The second Sj and O2 film portions extending in the shape of an eave act as a mask during etching, and the second Si
02 film is removed. In other words, the distance between the pair of eave-like portions formed by the second 5in2 film in the recessed portion. When it is closed, the second S i at the bottom of the seam at the position corresponding to the distance difference Q
02 film and] SjO,! Second St on the membrane, 02
The film is removed, and the second SiO□ film on the side surfaces of the recess remains. (4) Thereafter, a goo 1-electrode is formed in the recessed portion on the main surface side of the GaAs substrate. The gate length becomes the opening width (etching width) of the second Sj, 02 opened at the bottom of the recess. That is, the distance between the pair of eave-shaped SjO,, films (
It almost matches Q). In such gate electrode formation technology, the groove length is the etching width (ω) of the second SiO film at the bottom of the recess.
Determined by The etching width (Ω) is 5i02 on the active layer provided when forming the source/drain electrodes.
It is determined by the width d of the (first S, +02 film) and the thickness of the second Si02 film.
The thickness control of the 5Jo2 film is achieved by the already established vapor phase growth method (
CVD) technology is expensive. Therefore, according to the technique of the present invention, a GaAs5BGFET with high gate length accuracy can be manufactured. Further, according to the technology of the present invention, the thickness of the second 5i (12 film) can be controlled with precision, and the second SiO2
The step coverage shape of the film grows to a 4'll-like shape, and the distance (+2) between the pair of eaves formed by the second SiO□ film is the second
The dimension of Q can be made even smaller than 5 μm by being proportional to the SjO□ film growth processing time. As a result, the length can be made even shorter than 0.5 μm, improving the characteristics of the GaAs5BGFET, such as high frequency characteristics and high speed. Furthermore, according to the technology of the present invention, GaAs5 B G F
When manufacturing the ET, the opening width d of the first Si02 film can be confirmed from the outside. For this reason, the first
5j02 membrane opening width was measured, and the second S,
By setting the forming processing conditions for the +02 film, even if the opening dimension of the first 5j02 film becomes wider than the standard, it becomes possible to manufacture the desired goo length, which improves the production yield. Improvements can be achieved. [Example 1] Figures 1 to 11 show GaAs according to an example of the present invention.
Cross-sectional view showing the manufacturing method of S B G F E T, 1st
Figure 2 is also an enlarged cross-sectional view of the source/drain electrode, the first
FIG. 3 is a plan view of the same <GaAs5 B G F E T chip. The GaAs5BGFET chip (hereinafter simply referred to as a chip or element) in this embodiment is manufactured through the manufacturing steps shown in FIGS. 1 to 11. Next, manufacturing of the chip will be explained with reference to the same figure. First, as shown in FIG. 1, a G
A substrate 1 is prepared and removed. This GaAs substrate 1 has been subjected to epitaxial treatment, and its main surface (lOO) is crystal plane 1.
:, 0.11 μm thick made of 1-type GaAs
A channel layer 2 and a 0.3 μm thick ohmic contact layer 3 made of n+ type GaAs are successively formed. The impurity concentration of the channel layer 2 is 2×101
7L:m-3, so that a desired shock resistance voltage can be obtained between the electrode and the electrode of AQ, which will be described later. In addition, the impurity concentration of the ohmic contact 1 and layer 3 is different from that of the channel layer 2 so that the resistance of the contact 1 of the source/drain electrode is small.
The impurity concentration is as high as L O"cm-3.Next, as shown in FIG. Fi1 is etched far away.As a result, an active layer consisting of a rl-n+ layer with a desired pattern isolated by etching is formed.Next, as shown in FIG. CVl
A 0.5 μm thick insulating film (
For example, the S''O□ film and this S,+02 film are also referred to as the first SjO□ film for convenience of explanation. ) is formed. Next, as shown in FIG. 4, the G3As-based FiJ is coated with the film 6 from the resist I to the entire main surface thereof. This photoresist film 6 is photo-developed into a desired pattern. That is, this pattern is also related to the extending direction of the Ga I electrode, which will be described later, and in the case of the same figure, the cross section is Ga A s
It is a plane along the [0], 1) axial direction of the crystal. . In this case, using the main surface of the (1,00) plane, [011,
Although it is referred to as the axial direction, if the element is formed using the back side of the (1,00) plane, the figure becomes a cross-sectional view along the [01,1] axial direction. In addition, the first S10. The film 5 is etched using a hydrofluoric acid etching solution using the photoresist film 6 as a mask. As a result, a source/drain electrode formation region is formed. 5 As shown in FIG. 51, the GaAs substrate 1 is subjected to a vapor deposition process of source/drain electrode (Φi material), and a 7M2 layer 7 is formed over the entire main surface.The vapor deposition N7 is shown in FIG. As shown, the highest FM AuGe layer 8. The middle Ni layer lO
It consists of The A u G e layer 8 is a layer for establishing ohmic contact with the ohmic contacts 1 to 3. Ni layer 9 is Ga in GaAs.
This is a layer to prevent the Au layer from entering the Au layer. Furthermore, ΔU
The layer 10 is a layer formed in consideration of corrosion resistance against external atmosphere and bonding. Next, as shown in FIG. 6, the resist films 1 to 6 are removed, and the source electrodes (S) II and 1 are deposited directly on the ohmic contact layer 3-I-. The vapor deposited layer 7 other than the electrode (D) 1.2 is removed (Ref 1
off method). Next, a gate electrode is formed. The formation of the gate electrode will be explained using an enlarged view of the portion surrounded by a broken line circle in FIG. 6. That is, as shown in FIG. 7, the first SjO film 5 extending between the source electrode 11 and the drain electrode 12 on the main surface of the GaAs substrate 1 is etched by conventional photoetching. Photoresist film 13
Using this as a mask, an opening with a width of d is made using hydrofluoric acid-based elastomers 1 to 1. This opening width d is longer than the lengths t and g of the formed goo electrode. In this embodiment, since Goo 1 to Lg is targeted to be 0.3 μm, it is set to about .mu.nl, for example. In addition, the width is 300μ stroke 1
It will be about. Next, using this first 5in2 film 5 as a mask, NH4
, OH: II202: II, , 0, etc., the ohmic contact layer 3 and the channel layer 2 are etched to form a recess ]4. The ohmic contact layer 3 is removed over its entire thickness, but the surface layer of the channel layer 2 is etched;
The thickness of the channel layer 2 at the bottom of the recess is approximately 0.17 zm, resulting in a structure suitable for high frequencies. During this etching, 7G is added to the gate length of the Goo I-electrode.
Since the direction of recess 14 is along the (01,1) axis direction of the (l a As crystal), the side surface of the recess 14 has an eave-like inverted mesa structure.In addition, when etching the active layer,
Since the active layer is etched (side-etched) all the way to the inside of the first S02 film 5 serving as a mask, the recessed side surface portion becomes a deeper eaves structure. As a result, GaAs
A depression (groove) is formed in the surface layer of the substrate, the edge of which forms an eaves structure, and the bottom surface of which exposes the substrate material. Next, as shown in FIG. 8, after the photoresist film 13 is removed, the GaAs substrate 1 is treated by a chemical vapor deposition (CVD) method to form an insulating film (for example, an S10□ film; a second S10□ film;
In, , a film) 15 is formed on its main surface. CV D-
Since the 5 in 2 film has good step coverage, the eaves portion has an overhang structure (eaves structure). At this time, what should be noted is that the first SiO2 film 5
The flat thickness t, ) of the second 5in2 film 15 deposited on the second 5in2 film 15) and the overhang thickness t2 of the second Sj0゜1@15 formed to overhang from the tip of the eaves are approximately the same. - In addition, the GaAs substrate 1 at the protruding tip
The thickness t, 3 in the thickness direction is equal to or longer than the flat thickness 1.1. And the second S
j Distance between a pair of eave-like protrusions formed by the O2 film 15 (Q)
is given by the following equation. Q=d-2t2...(1) Also, as will be described later, since the distance a corresponds to the gate length, for example, in order to set Q to 0.3 μm, if d is 1 μm, then , second Sj, 0□ film 15
The actual film thickness is considered to be approximately the same size as t2, so t
2=1 寥=0.35μ■1. Note that the thickness of the second SiO□ film 15 deposited on the bottom of the recess is 5.
t tends to be thinner than the flat thickness t because the reactant gas does not flow sufficiently into the narrow recessed portion. Next, as shown in FIG. 9, the GaAs substrate 1 is subjected to an anisotropic dry etching process such as active ion etching, and the 25 in 2 holes 15 on the main surface are etched.
7'J' selectively removed. That is, the first 5in
2 membranes 5 years old and source drain electrode II. The second 5j02 film j5 of No. 12, , l: is completely removed since it poses no problem. Furthermore, the second 5j02 film 15 at the bottom of the recess is completely removed except under the overhanging portion of the second Si02 film 15, so that the channel layer 2 is exposed. But the second 5i()
The region covered by the overhanging portion of the second film 15 remains unetched because the ions do not reach it directly. At this time, L' of the overhang part of the second 5j02 film 15
The surface layer in the longitudinal direction (tl, ↑3 direction) is gradually etched. However, since the thickness t3 of the overhang portion of the second S]02 film 15 is equal to or 1. thicker than the flat thickness tl, the contact 1-flower 1 for the gate electrode is
6 is provided at the bottom of the recess, the interval ρ between the eave-like protrusions does not change. As a result, the widths of the contacts 1 to 16 become the same dimension as the interval Q. Next, as shown in FIG. 10, the main surface of the CnA 94% plate 1 is coated with low-resistance aluminum (a gate electrode material).
AQ) is deposited. Also, this AQ is a commonly used
- Patterned by etching, gate electrode (
G) 17 (patterning layer) is formed in the recessed portion. Δα is formed in a row over the entire recess bottom. As a result, the gate length L g of the gate electrode 17 is the same as the width 1- of the hole 160 to the contact hole 1 = 1 method, and the width I of the contact hole I6 is the same dimension as the pitch Q of the eave-like protrusions. . In other words, Goo 1 - Goo I ~ length of electrode 17

[, Bi will be determined by the interval Q of the eave-like protrusions. Next, as shown in FIG. 11, the main surface of the aAs substrate 1 is passivated! A (for example, Tee 1 Helide) is covered by 18. 1: The passivation film 18 is partially removed to form bonding pads 19 for each of the source, goo 1 to drain electrodes. GaAs S B G F produced in this way
The ET chip (deep) 20 is used with a desired package applied thereto. Note that the source electrode (S) Il, the gate electrode (G) 17. The pattern of the double electrode (L) 1.2 is as shown in FIG. The regions framed by two-dot chain lines shown in the figure are regions where the bonding pads 19 are provided, respectively. [Effects] (1) According to this embodiment, since the gate length can be formed by self-alignment, it can be formed with high precision and good reproducibility. (2) According to this embodiment, the J' method for the gate electrode is CVD.
CVD 5j-
By controlling the thickness of the 02 film, it is possible to control the dimensions of the 02 electrode with high accuracy, and a fine gate length can be formed. (3) According to this embodiment, prior to the formation of the CV I)-3in2 film, judicial measurement of the open part (d) of the recess can be carried out, and by this dimension measurement, the CV I)-5i(1
The thickness of two films can be controlled. For this reason, it is possible to always form a goo electrode having a desired goo length in 1-1 steps, thereby achieving improved quality and yield. (4) From (2) above, since the Goo 1 length can be shortened, the gate area can be reduced and the capacitance between Goo 1 and the source can be reduced. (5) From (4) above, the direction of the mutual conductance of FET can be determined. (6) From (4) and (5) above, the gate-source capacitance can be reduced and the mutual conductance direction 1; can be achieved, so that the frequency characteristics can be improved. (7) Part 2 From (4) and (5), it is possible to reduce the gate-source capacitance and improve the mutual conductance.
Noise figure (NF) can be kept low. (8) From (4) and (5) above, it is possible to reduce the gate-source capacitance and improve mutual conductance.
The power gain can be improved. [Example 2] Figures /I to 24 are G according to other embodiments of the present invention.
FIG. 3 is a cross-sectional view showing a method of manufacturing an aAs5BGFET chip. In this embodiment, members having the same functions and effects as those in the first embodiment will be described using the same reference numerals and names. In this embodiment, as shown in FIG.
a A 5 substrate 1 is prepared. And this (ia
A 5in2 film 21 is selectively formed on the main surface of the As substrate 1, and silicon (Si) ions are implanted using this SiO□ film 21 as a mask to form an n+ source region 2.
2 and a drain region 23 are formed. Next, the SiO□ film 21 is removed. After that, G
A 3502 film 24 is selectively provided on the main surface of the aAs substrate 1. The source/drain regions 22 and 23 and the GaAs surfaces therebetween are exposed. Therefore, the GaAs substrate I is again subjected to Si ion implantation treatment, and the GaAs substrate I is implanted between the source and drain regions 22 and 23.
An n-type channel layer 2 is formed in the s surface layer portion. Next, as shown in FIG. 16, after removing the Sj, O, film 24 on the main surface of the GaAs substrate 1, the photoresist film 25 is again used to remove the SiO film provided on the main surface of the GaAs substrate 1.
□ Film 26 is selectively removed to expose source region 22 and train region 23. Next, as shown in FIG. 17, A
uGe/N i , /A u are sequentially formed on the GaAs substrate 1
is deposited on the main surface of the Thereafter, the photoresist film 26 is removed as shown in FIG. As a result, the deposited layer 7 on the photoresist film 26 is removed (lifted off), and the source electrode (S) 11 is formed on the surfaces of the source region 22 and drain region 23. A drain electrode (D) 12 is formed. Next, a gate electrode is formed. Formation of the gate electrode will be explained with reference to an enlarged view of the portion surrounded by a broken circle in FIG. 18. That is, as shown in FIG. 19, a nitride film 27 is formed over the entire surface of the GaAs substrate. Next, as shown in FIG. 20, the nitride film 27 corresponding to the goo 1 electrode formation region is etched with hot phosphoric acid so that it has an opening width d of about 1 μm as in the previous embodiment. Also, SjO is exposed using this nitride film 27 as a mask.
□The film 26 is etched with hydrofluoric acid. At this time, since the SiO□ film 26 is side-etched, the edge of the mask has an eave structure as in the previous embodiment. The subsequent steps are similar to those in the previous embodiment. That is, as shown in FIG. 21, the entire main surface of the GaAs substrate 1 is covered with a film 15 of t, C V D-5]O, and the interval Q between the openings is given by the equation (1) above. It will be given to you. Note that the overhang JT7 [2] of the overhang of the film 15 is approximately the same dimension as the flat thickness 1=CVI)-5 inches. Moreover, the thickness is greater than the thickness t3 of the overhang tip. Therefore, the main surface of the GaAs substrate 1 is subjected to an anisotropic etching process. As a result, as shown in FIG. 22, the overhanging portion of the 5jO2 film j5 at the bottom of the recess serves as a mask, so that contacts 1 to hole 1G having a width L are formed. This hole width is 1. is the same as Q above and has 1 method. Next, AQ is deposited on the main surface of the GaAs substrate 1 and patterned, thereby forming a gate electrode (G)+7 having a gate length I-g, as shown in FIG. Note that by leaving the T1-ride film 27 as a passivation film, it serves to protect the element from the external atmosphere. Also, take out the source/drain electrodes using the goo 1
- Before depositing the electrode material 24, the T1 to Ride films 2 are placed at desired positions on the - side of the source/drain electrodes.
7 may be selectively removed, and the electrodes may be taken out at the same time as the electrodes 1 to 1 are formed. In this embodiment, the SRG FET can be formed on a part of the GaAs substrate by using ion injection technology, and the wiring can be routed to take out the source/drain electrodes when forming the electrodes on the groove 1. It becomes possible to connect with GaAs FETs, GaAs diodes, etc. formed in other regions of the substrate, and it is possible to form logic circuits, integrated circuits (ICs), etc. [Effects] (+) According to this embodiment, since the gate length can be formed by self-alignment, it can be formed with high precision and good reproducibility. (2) According to this embodiment, the dimensions of the gate electrode are CV D
-5in2 Since it is determined by the thickness of the film, one C■ -51
By controlling the thickness of the 02 film, it is possible to control the dimensions of the gate electrode with high precision, and it is possible to form a fine goo 1 in length. (3) According to this embodiment, the dimensions of the opening (d) of the recess can be measured prior to the formation of the CVD-3jO7 film,
CVD-5in by measuring this dimension. Film thickness can be controlled. Therefore, it is possible to always form a goo 1 to electrode having a desired goo 1 to length, and improvement in quality and yield can be achieved. (4)” 1 (2)
Since the gate length can be made shorter, the gate area can be reduced, and the human capacitance can be reduced. From (5) and (4), the direction of the mutual conductance of the FET can be determined. (6) From (4) and (5) above, it is possible to reduce the capacitance between the two and to improve the mutual conductance, so that the frequency characteristics can be improved. (7) From (4) and (5), it is possible to reduce the human capacitance and improve the mutual conductance, so the noise figure (N17) can be kept low. From 4) and (5), it is possible to reduce the human capacitance and improve the mutual conductance.
Power gain can be improved. (9) This embodiment is suitable for IC implementation because the S B G FET can be easily formed by isolation on a single GaAs substrate. The above inventions made by the present inventor are actually J No. 1! ! Although the present invention has been specifically explained based on the above example, it goes without saying that the present invention is not limited to the example described in 1 and can be modified in various ways without departing from the gist thereof.For example, , as an example of forming the eave structure, FIG.
The structure shown in Figure 25 is a great idea.
: That is, in FIG. 24, a photoresist 29 is formed on the 5j02 film 28.
FIG. 25 shows a structure in which two layers of photoresist film 30.3+ are layered in stages to form an eave structure. The former uses side etching to create an eave shape, and the latter creates an eave shape by changing the photosensitive pattern. Furthermore, regarding the eave structure in the recessed GaAs5 BGFET, in addition to this embodiment 1, as shown in FIG.
If the back side of the 100) surface is used, it may be formed in the [o11] axial direction. In this case, the mutual conductance can be further improved than in this embodiment I, and the element characteristics based on it can be improved, for example, the frequency characteristics are improved, the noise figure is reduced,
Power gain can be improved. Suna A? When comparing the distances from the gate end to the ohmic contacts 1 to 1 to the source/drain electrodes of elements with the same eave structure having the same length, the eave structure shown in FIG. When using 41., the distance can be made shorter, so the source resistance can be reduced and the mutual conductance can be further improved than in the first embodiment. Ru. In this case, the wiring for taking out the Goo 1-F 1 pole to the bonding pad is arranged in the Goo 1-long direction at the end of the gate width to prevent the wiring from breaking, and then connected to the bonding pad. Connection [Field of Application] In the following explanation, the invention made by the present inventor will be mainly explained in terms of the field of application which is its background.
Although the case where it is applied to the 5SBGFET manufacturing technology has been described, it is not limited thereto.For example, GaAs FETs of other structures, GaAs 1. G.
The present invention can be similarly applied to semiconductor devices made of materials such as silicon high-frequency transistors and silicon (III).

[Brief explanation of the drawing]

FIG. 1 shows a method for manufacturing GaAs according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the substrate. FIG. 2 is a cross-sectional view showing the substrate etched for isolation. FIG. 3 is a cross-sectional view showing a state in which a 5j-0□ film is also formed on the same substrate. FIG. 4 is a cross-sectional view showing a state in which the S i (12 film) north of the source/drain region of the substrate has been removed. FIG. FIG. 6 is a cross-sectional view showing a state in which source/drain electrodes have been formed. FIG. 7 is a cross-sectional view showing a state in which recess etching has been performed. FIG. FIG. 9 is a cross-sectional view showing a state in which a CV D-SiO□ film (second S'02 film) is formed on top of the film. FIG. FIG. 10 is a cross-sectional view showing a state in which the electrodes are similarly formed. FIG. 11 is a cross-sectional view showing a state in which the bonding pad portion on which a passivation film is similarly formed is opened. Fig. 12 is an enlarged sectional view of the source/drain electrodes, Fig. 13 is a plan view of the same <GaAs5 B G F E T chip, and Fig. 14 is an enlarged cross-sectional view of the same <GaAs5 B G F E T chip. ,
FIG. 3 is a cross-sectional view showing a state in which ohmic contact layers are formed in source/drain regions. FIG. 15 is a cross-sectional view showing a state in which a channel layer is similarly formed. FIG. 16 also shows 510 in the source/drain region.
FIG. 2 is a cross-sectional view showing a state where two membranes are opened. FIG. 17 is a cross-sectional view showing a state in which the source/train electrode material is similarly deposited. FIG. 18 is a cross-sectional view showing a state in which source and drain electrodes are similarly formed. FIG. 19 is an enlarged cross-sectional view of the gate portion with a nitride film formed on the substrate. FIG. 20 is a sectional view showing a state in which an eave structure is similarly formed. . Figure 21 shows a CVD-5jO□ film (second
FIG. 3 is a cross-sectional view showing a state in which a SiO□ film) is formed. FIG. 22 is a cross-sectional view showing a state in which the CV D-5iO7 film at the gate portion has been removed by anisotropic dry etching. Figure 23 shows a GaAsFE film with a gate electrode formed thereon.
It is a sectional view of T. FIG. 24 is a partially enlarged sectional view, not showing the eave structure, according to another embodiment of the present invention. FIG. 25 is an enlarged sectional view showing an eave structure according to still another embodiment of the present invention. FIG. 26 is a partially enlarged sectional view showing an eave structure according to still another embodiment of the present invention. I...GaAs substrate, 2...Channel layer, 3...
- Ohmic contact layer, 4... Hol-resist film, 5... Insulating film (first 5in2 film), 6... Photoresist film, 7... Vapor deposition layer, 8... AuGe layer, 9・
...Ni layer, 10...Au layer, 11...source electrode (S), +2...drain electrode (D), 13...film to photoresist 1, 14...recess -15... - Insulating film (second Si02 film) 16... contact hole, 17.
...Gate electrode (G) 18...passivation film,
19... Bondingo (Rado, 20-GaAsS
B G F E T chip (chip), 21...5
iO7 film, 22...source region, 23...1z rain region, 24...SiO□ film, 25...ho 1-resist I
-I+ arrow, 26...Si02 film, 27...T1 helidell order 28-3102 m, 29-31...photoresist film. Figure 1 Figure 4? Figure 6 Figure 7/4 Figure 8 Figure 9 Figure 10 Figure 12 Figure 13/,! ' / y7. , po Figure 14 22 X2. Figure 15 Figure 16 Figure 17 Figure 18 Figure 20 Figure 21 Figure 22

Claims (1)

[Claims] 1. A step of forming a recess on the main surface of the substrate with an edge having an eave structure and exposing the base moon on the bottom surface, a step of forming a masking film on the main surface side of the substrate and on the metal area of the recess surface, and an anisotropic process. a step of removing the masking film on at least the bottom of the recess corresponding to the narrowest opening of the recess by chemical etching; A method for manufacturing an electronic device, comprising: forming a desired patterning layer in a region including a recessed portion.