JPH0810698B2 - Manufacturing method of lateral junction field effect transistor - Google Patents
Manufacturing method of lateral junction field effect transistorInfo
- Publication number
- JPH0810698B2 JPH0810698B2 JP58213872A JP21387283A JPH0810698B2 JP H0810698 B2 JPH0810698 B2 JP H0810698B2 JP 58213872 A JP58213872 A JP 58213872A JP 21387283 A JP21387283 A JP 21387283A JP H0810698 B2 JPH0810698 B2 JP H0810698B2
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- field effect
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Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 title claims description 6
- 238000001514 detection method Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 10
- 239000000523 sample Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 238000005259 measurement Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- -1 GaAs compound Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、例えばGaAs化合物半導体の接合型電界効果
トランジスタを得る場合に適用して好適な横型接合型電
界効果トランジスタの製法に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a lateral junction field effect transistor suitable for application in the case of obtaining a junction field effect transistor of, for example, a GaAs compound semiconductor.
背景技術とその問題点 化合物半導体、例えばGaAsによる接合型電界効果トラ
ンジスタ（FET）は、高速素子として注目を浴びている
ものの、大規模な集積回路としては、実用化に難点があ
る。Background Art and Its Problems Compound semiconductors, such as junction type field effect transistors (FETs) made of GaAs, have attracted attention as high-speed devices, but they are difficult to put into practical use as large-scale integrated circuits.
その最も大きな難点は、FETのピンチオフ電圧Vp（す
なわち、FETのドレイン電流が流れ始めるゲート電圧の
大きさ）を再現性良く制御することである。The biggest difficulty is to control the pinch-off voltage Vp of the FET (that is, the magnitude of the gate voltage at which the drain current of the FET starts to flow) with good reproducibility.
通常、GaAsによるFETの集積回路を作るには、半絶縁
性GaAs基体にドナー不純物のSi,Seなどをイオン注入
し、熱処理によってＮ型層を形成し、これにショットキ
ー接合ゲート電極を被着してショットキー接合型のFET
を作製するという方法がとられる。この場合、そのピン
チオフ電圧Vpの変動を、0.1V以内に収めるには、チャン
ネル層となるＮ型層の厚さは、50Å以内の変動に抑えね
ばらない。Usually, to make an FET integrated circuit using GaAs, donor impurities such as Si and Se are ion-implanted into a semi-insulating GaAs substrate, an N-type layer is formed by heat treatment, and a Schottky junction gate electrode is deposited thereon. And Schottky junction type FET
Is used. In this case, in order to keep the fluctuation of the pinch-off voltage Vp within 0.1V, the thickness of the N-type layer serving as the channel layer must be suppressed within 50Å.
また現状のGaAs結晶基板は、そのウェファー毎に残留
不純物濃度、転位密度などが異なり、更に熱処理工程に
よっても変化する。このため、一定のVpを有するFETを
各ウェファーについて得ることが難しく、各ウェファー
毎にそのＮ型層を形成する不純物イオンの注入条件を、
選定する必要がある。In the current GaAs crystal substrate, the residual impurity concentration, dislocation density, etc. are different for each wafer, and are also changed by the heat treatment process. For this reason, it is difficult to obtain an FET having a constant Vp for each wafer, and the impurity ion implantation conditions for forming the N-type layer for each wafer are
It is necessary to select it.
これに比し、接合型FETは、上述したＮ型層の形成後
にＰ型のゲート領域をイオン注入法、拡散法等によって
形成するものであり、このＰ型領域の深さによって、ピ
ンチオフ電圧Vpを制御することができるので、化合物半
導体のFETにおいて接合型構成とすることに有利性はあ
るが、この場合においても、Ｐ型領域の形成工程でその
深さを決定する上で、例えばその中間過程でのVpの測定
が行われることが望まれる。On the other hand, in the junction type FET, the P-type gate region is formed by the ion implantation method, the diffusion method or the like after the formation of the N-type layer described above, and the pinch-off voltage Vp is determined by the depth of the P-type region. Since it is possible to control the temperature, it is advantageous to use a junction type structure in the FET of the compound semiconductor. However, even in this case, in determining the depth in the step of forming the P type region, for example, the intermediate It is desired that Vp be measured during the process.
発明の目的 本発明は、上述した例えば接合型FETの製造工程にお
いて、ピンチオフ電圧Vp値の推定を適宜正確に行うこと
ができるようにして、所定のVp値を有する接合型FETを
確実に得ることのできるようにした半導体装置の製法を
提供するものである。An object of the present invention is to reliably obtain a junction type FET having a predetermined Vp value by appropriately and accurately estimating the pinch-off voltage Vp value in the above-mentioned manufacturing process of the junction type FET, for example. A method of manufacturing a semiconductor device is provided.
発明の概要 すなわち、本発明においては、GaAs等の化合物半導体
における、比較的高濃度（1018cm-3）のＰ型領域に対
しては、金属針の接触によってオーミックコンタクトを
とり得ることを利用して、ピンチオフ電圧Vpの云わばモ
ニター領域を形成し、これの特性を測定して、所望のVp
を有するFETを得るものである。SUMMARY OF THE INVENTION That is, according to the present invention, it is possible to make ohmic contact with a P-type region having a relatively high concentration (10 18 cm −3 ) in a compound semiconductor such as GaAs by contact with a metal needle. Then, a pinch-off voltage Vp, which is called a monitor region, is formed, and its characteristic is measured to obtain a desired Vp.
To obtain a FET having
すなわち、本発明においては、化合物半導体に対する
Ｐ型のゲート領域の形成と同時に、少なくとも対の特性
検出用のＰ型の領域を形成し、この対の特性検出用の領
域に、特性検出用探針を接触させ、その探針間のインピ
ーダンスのバイアス電圧特性を測定して、直列抵抗成分
のピークを与える電圧をもってＰ型領域のピンチオフ電
圧を推定して、所要のピンチオフ電圧を得るＰ型領域を
形成する。That is, in the present invention, at the same time as the formation of the P-type gate region for the compound semiconductor, at least a pair of P-type regions for characteristic detection are formed, and the characteristic detection probe is provided in the pair of characteristic detection regions. And the bias voltage characteristics of the impedance between the probes are measured, the pinch-off voltage of the P-type region is estimated by the voltage that gives the peak of the series resistance component, and the P-type region that obtains the required pinch-off voltage is formed. To do.
実施例 本発明においては、例えば第１図に示すように、半絶
縁性GaAsのウェファー、すなわち基板（１）を設け、そ
の一主面（1a）上に図示しないがフォトレジスト膜を例
えば１μｍの厚さに塗布し、露光現像処理を施して、最
終的に回路素子としてのFETを形成すべき部分（図にお
いては１個のみを示す）と、他の位置とに、夫々不純物
注入用の窓を形成する。そして、このフォトレジスト膜
をマスクとして、130keVで４×1012cm-2のドース量をも
ってその窓を通じて基板（１）の表面に選択的にSiをイ
オン注入し、その後レジスト膜を除去して例えば、3Tor
rのAsH3を含むH2ガス中で850℃10分間の熱処理を行っ
て、最終的に回路素子としてのFETを形成すべき部分
と、他の部分とに夫々Ｎ型領域（２）及び（３）を形成
する。EXAMPLE In the present invention, for example, as shown in FIG. 1, a semi-insulating GaAs wafer, that is, a substrate (1) is provided, and a photoresist film (not shown) having a thickness of, for example, 1 μm is formed on one main surface (1a) thereof. A window for impurity implantation is formed at a portion (only one is shown in the figure) where a FET as a circuit element is finally formed by applying a thickness, exposing and developing, and at other positions. To form. Then, using this photoresist film as a mask, Si is selectively ion-implanted into the surface of the substrate (1) through the window with a dose amount of 4 × 10 12 cm -2 at 130 keV, and then the resist film is removed, for example. , 3Tor
The heat treatment is performed at 850 ° C. for 10 minutes in H 2 gas containing r AsH 3 to finally form a FET as a circuit element, and the other portions in the N-type regions (2) and ( 3) is formed.
その後、第２図に示すように、基板（１）の面（1a）
に、絶縁層（４）、例えばSi3N4を、SiH4とN2とによる
気体種を用いて350℃でのプラズマCVD（Chemical Vapou
r Deposition）によって形成する。そして、このSi3N4
層（４）に、領域（２）上の最終的に回路素子としての
FETのゲート領域となる部分に窓（５）を穿設すると共
に、領域（３）上に対の窓（6a）及び（6b）を穿設し、
これら窓（５），（6a），（6b）を通じて各領域（２）
と（３）との上に、Ｐ型の不純物、例えばZnを拡散して
夫々Ｐ型のゲート領域（５）と、特性検出用の対の領域
（8a）及び（8b）をその少なくとも表面の濃度が1018
cm-3をもって形成する。Then, as shown in FIG. 2, the surface (1a) of the substrate (1)
In addition, an insulating layer (4), for example, Si 3 N 4 is plasma CVD (Chemical Vapou) at 350 ° C. by using a gas species of SiH 4 and N 2.
r Deposition). And this Si 3 N 4
Layer (4), finally as a circuit element on the area (2)
A window (5) is formed in a portion which becomes a gate region of the FET, and a pair of windows (6a) and (6b) are formed in the region (3).
Each area (2) through these windows (5), (6a), (6b)
And (3), a P-type impurity, for example, Zn is diffused to form a P-type gate region (5) and a pair of regions (8a) and (8b) for characteristic detection on at least the surface thereof. Concentration 10 18
Form with cm -3 .
そして、このゲート領域（５）による特性を間接的に
推定検出する。この検出は、特性検出用の領域（8a）及
び（8b）に夫々Cu,Au,Pt等より成る電極針、すなわち探
針（9a）及び（9b）接触植立し、両探針間のインピーダ
ンスを測定する。この測定は、容量Ｃと並列コンダクタ
ンスＧを測るか、容量C2と直列抵抗Ｒとを測るインピー
ダンスメータを用い得る。そして、この測定によって後
述するところから明らかになるように回路素子としての
FETのVpを知り、これによって目的のVp値を得ることが
できる深さに領域（７）及び（8a）（8b）の追加拡散を
必要に応じて行ってその深さを所要の深さに設定し、第
３図に示すように、領域（７）にゲート電極（10G）を
オーミックに被着すると共に、領域（７）を挟んでその
両側の領域（２）上にソース及びドレイン各電極（10
s）及び（10D）をオーミックに被着して領域（２）の領
域（７）下をチャンネル（10）とする接合型FET（13）
を形成する。Then, the characteristics of the gate region (5) are indirectly estimated and detected. In this detection, electrode needles made of Cu, Au, Pt, etc., that is, the probes (9a) and (9b) are set up in the characteristic detection regions (8a) and (8b), respectively, and the impedance between the two probes is set. To measure. For this measurement, a capacitance C and a parallel conductance G can be measured, or an impedance meter that measures a capacitance C 2 and a series resistance R can be used. Then, as will be apparent from the later-mentioned measurement by this measurement,
Know the Vp of the FET and perform additional diffusion of regions (7) and (8a) and (8b) as necessary to obtain the desired Vp value, and adjust the depth to the required depth. As shown in FIG. 3, the gate electrode (10G) is ohmically deposited on the region (7), and the source and drain electrodes are formed on the regions (2) on both sides of the region (7). (Ten
s) and (10 D ) are ohmic-deposited to form a junction type FET (13) with a channel (10) under the region (7) of the region (2).
To form.
次に、上述したVpの間接的検出方法について説明する
に、上述したように、本発明においては、少なくとも１
対の検出用領域（8a）及び（8b）を設け、これに夫々C
u,Au等より成る金属電極針、すなわち探針（9a）及び
（9b）を接触させて両領域（ａ）及び（8b）間のインピ
ーダンスの測定を行うこの場合、化合物半導体GaAsのＰ
型の高濃度領域（1018cm-3）に対しては、これに電極
金属層を被着せずとも金属探針（9a）及び（9b）を接触
させるのみでオーミックのコンタクトをなし得るもので
あり、本発明においては、このような特性を利用するも
のである。Next, the indirect detection method of Vp described above will be described. As described above, in the present invention, at least 1
A pair of detection areas (8a) and (8b) are provided, and C is provided in each of these areas.
In this case, the metal electrode needle made of u, Au, etc., that is, the probes (9a) and (9b) are contacted to measure the impedance between the regions (a) and (8b).
With respect to the high-concentration region (10 18 cm -3 ) of the mold, ohmic contact can be achieved only by contacting the metal probes (9a) and (9b) without depositing an electrode metal layer on it. Therefore, the present invention utilizes such characteristics.
このインピーダンスの測定は、容量と並列コンダクタ
ンスの測定によるか容量と直列抵抗が測れるインピーダ
ンスメータを用いることによって行い得る。This impedance can be measured by measuring capacitance and parallel conductance, or by using an impedance meter capable of measuring capacitance and series resistance.
今、第４図に示すように、検出用領域（8a）及び（8
b）に検出用探針（9a）及び（9b）を立て、両者間の電
圧Ｖを変化させて両領域（8a）及び（8b）間の容量Ｃを
測定して、第５図に示すようにＣ−Ｖ特性を測定する。
この場合、第４図に破線をもって示すように、今、例え
ば一方の領域（8a）側を正極側として電圧Ｖを与える
と、この領域（8a）に関するPN接合Jaは順方向バイアス
となるので、この印加電圧の大部分は、他方の領域（8
b）によるPN接合Jbに加わる。すなわち、両領域（8a）
及び（8b）によるPN接合Ja及びJbから空乏層の拡がり
は、第４図に破線で示すように接合Jb側において大で、
電圧Ｖを上げて行くことによってこの空乏層が基板領域
に到達するとき、全体の容量Ｃは急激に低下する。すな
わち、この時の電圧によってこれら領域（8a）及び（8
b）と同時に、すなわち、同条件下で形成したゲート領
域（５）のピンチオフ電圧Vpを推定できる。しかしなが
ら、このＣ−Ｖ特性による場合、容量Ｃが或る電圧で急
激に低下するとは云うものの、実際上は或る程度のゆる
やかな勾配をもって低下するのでVpの推定に稍々正確性
を欠く。Now, as shown in FIG. 4, detection areas (8a) and (8a)
The detection probes (9a) and (9b) are set up in b), the voltage V between them is changed, and the capacitance C between both regions (8a) and (8b) is measured, as shown in FIG. Then, the C-V characteristic is measured.
In this case, as shown by the broken line in FIG. 4, when the voltage V is applied with one region (8a) side as the positive electrode side, the PN junction Ja for this region (8a) is forward biased. Most of this applied voltage is in the other region (8
Join PN junction Jb according to b). That is, both areas (8a)
The spread of the depletion layer from the PN junctions Ja and Jb by (8b) and (8b) is large on the junction Jb side as shown by the broken line in FIG.
When this depletion layer reaches the substrate region by increasing the voltage V, the total capacitance C drops sharply. That is, depending on the voltage at this time, these areas (8a) and (8
At the same time as b), that is, the pinch-off voltage Vp of the gate region (5) formed under the same condition can be estimated. However, according to this C-V characteristic, although the capacitance C drops sharply at a certain voltage, it actually drops with a certain gentle slope, so that the accuracy of Vp estimation is somewhat inaccurate.
一方、このＣ−Ｖ測定において、直列抵抗成分Ｒをみ
ると、これは第６図に示すようにVpの極く近傍で急峻な
ピークを示す。本発明においては、この特性に着目して
Vpの推定をする。On the other hand, in this C-V measurement, when looking at the series resistance component R, this shows a steep peak in the very vicinity of Vp as shown in FIG. In the present invention, focusing on this characteristic
Estimate Vp.
このようにＲ−Ｖ特性がVp近傍で急峻なピークを示す
のは、次の現象に基づくものと思われる。すなわち、今
第７〜９図に示すように、PN接合に逆バイアス電圧Ｖが
与えられた状態についてみる。図において、破線は空乏
層の拡がりを模式的に示したもので、R0はＮ型層の抵
抗、C0はPN接合の側壁における接合容量R1は空乏層下の
抵抗、C1はRN接合の底面における接合容量を示す。第７
図は|V|《Vpの状態を示し、この場合、空乏層下には未
だキャリアが多く存在するので、R1は充分小さくＲ＝R1
＋R0も充分に小さい。第８図は|V|Vpの状態を示し、
この状態では、キャリアの数が減少して来て、R1は大き
くなり、Ｒも大になってくる。第９図は、|V|＞Vpの状
態を示し、空乏層下には電流は流れず抵抗値ＲはR0だけ
で決まり、Ｒが減少する。このようにして第６図で示し
たようなＲ−Ｖ特性がVp近傍でピークを持つ特性を示す
ことになる。The reason why the R-V characteristic exhibits a steep peak in the vicinity of Vp is considered to be based on the following phenomenon. That is, the state where the reverse bias voltage V is applied to the PN junction is now examined as shown in FIGS. In the figure, the broken line schematically shows the spread of the depletion layer, where R 0 is the resistance of the N-type layer, C 0 is the junction capacitance on the sidewall of the PN junction, R 1 is the resistance below the depletion layer, and C 1 is RN. The junction capacitance at the bottom of the junction is shown. Seventh
The figure shows the state of | V | << Vp. In this case, since many carriers still exist under the depletion layer, R 1 is sufficiently small and R = R 1
+ R 0 is also small enough. Fig. 8 shows the state of | V | Vp,
In this state, the number of carriers decreases, R 1 increases, and R also increases. FIG. 9 shows a state of | V |> Vp. No current flows under the depletion layer, and the resistance value R is determined only by R 0 , and R decreases. In this way, the R-V characteristic as shown in FIG. 6 has a peak near Vp.
次にこのモデルを数値的に計算してみる。先ず第７〜
９図に示したモデルにおける等価回路として第10図に示
す回路を考える。この時のインピーダンスＺを、 とすると、 より、 ここで、R1,C1が電圧Ｖの関数である。Next, let's calculate this model numerically. First 7th
Consider the circuit shown in FIG. 10 as an equivalent circuit in the model shown in FIG. The impedance Z at this time is Then Than, Here, R 1 and C 1 are functions of the voltage V.
次に、R,Cを電圧の関数で表わす。今、第11図に示す
ようにＮ型層の厚さをｄとし、空乏層の厚さをｘとし、
Ｐ型領域の底面積をｌ×2lとすると、 （ここにεは空乏層の比誘電率、ｎはキャリア（電子）
の濃度、ｅは電子の電荷量、μは電子の移動度であ
る。）となる。一方、ｘと逆バイアス電圧Ｖとは次の関
係が成り立つことが知られている。Next, R and C are expressed as a function of voltage. Now, as shown in FIG. 11, the thickness of the N-type layer is d, the thickness of the depletion layer is x,
If the bottom area of the P-type region is l × 2l, (Where ε is the relative permittivity of the depletion layer, and n is the carrier (electron).
, E is the electron charge amount, and μ is the electron mobility. ). On the other hand, it is known that the following relationship holds between x and the reverse bias voltage V.
但し、V,VpにはφＢ（接合電位差）が含まれている。 However, V and Vp include φ B (junction potential difference).
（１）〜（６）式よりＲ及びＣがＶの関数として得ら
れる。From the expressions (1) to (6), R and C are obtained as a function of V.
但し、 （Cm及びRmは、夫々（３）式及び（４）式におけるC1及
びR1の最小値） として数値計算した。この結果を第12図に示す。第13図
は、その一部を拡大した図で、第14図は、Ｒのピークの
Vpからのずれの割合をみた図で、 では、0.1％以下のずれとなり、この程度のずれは無視
できる。 However, (Cm and Rm are the minimum values of C 1 and R 1 in equations (3) and (4), respectively) Was calculated numerically. The results are shown in FIG. FIG. 13 is an enlarged view of a part of it, and FIG. 14 shows the R peak.
It is a diagram showing the ratio of deviation from Vp, Then, the deviation is less than 0.1%, and such deviation can be ignored.
上述したところから明らかなようにＲ−Ｖ曲線によれ
ば、そのピークを示す電圧ＶをもってVpを正確に知るこ
とができる。As is apparent from the above description, according to the R-V curve, Vp can be accurately known from the voltage V showing the peak.
このようにして検出用Ｐ型領域、例えば第３図及び第
４図における領域（8b）のVpを知ることができ、これに
よって、この領域（8b）と同時に形成された半導体素
子、すなわち接合型FETのゲート領域（７）による素子
としてVpを間接的に推定することができる。したがって
その製造工程中においてVpを確認しながら領域（７）及
び（8b）への不純物の拡散を追加し、Vpを目的の値とす
ることができる。In this way, it is possible to know the Vp of the detection P-type region, for example, the region (8b) in FIGS. 3 and 4, so that the semiconductor element formed at the same time as this region (8b), that is, the junction type Vp can be indirectly estimated as an element by the gate region (7) of the FET. Therefore, while confirming Vp in the manufacturing process, diffusion of impurities into regions (7) and (8b) can be added to make Vp a target value.
そして、この場合、実際の接合は、理想的接合でない
ためにＲ−Ｖ曲線のピークを示すＶ値とVp値とに、差が
生じるが、これは予めこれを考慮してそのVp値の推定を
なせばよいものである。In this case, since the actual joining is not an ideal joining, there is a difference between the V value and the Vp value showing the peak of the R-V curve, but this is taken into consideration in advance in estimating the Vp value. What you have to do is.
第15図は、第３図における領域（8a）−（３）−（8
b）によるモニター用のＰ−Ｎ−Ｐトランジスタによる
Ｃ−V,R−Ｖ各曲線の測定結果を示すもので、この場合
両領域（8a）及び（8b）は夫々の一辺が200μｍ、他の
辺が150μｍの長方形パターンとし、その各深さを0.15
μｍとした場合である。FIG. 15 shows the area (8a)-(3)-(8 in FIG.
The measurement results of C-V and R-V curves by the P-N-P transistor for monitoring in b) are shown. In this case, both regions (8a) and (8b) are 200 μm on each side and Rectangular pattern with sides of 150 μm, each depth of 0.15
This is the case when μm is set.
発明の効果 上述したように本発明においては、高濃度Ｐ型GaAs系
化合物半導体に対して針を接触させるのみで充分オーミ
ックなコンタクトを行い得ることを利用して、検出用の
領域によって目的とする横型接合型FETのＰ型ゲート領
域によるピンチオフ電圧を推定することができるので、
その製造過程でこのVpを推定し、これに基づいてその目
的とするＰ型領域の拡散法の不純物導入を追加調整して
目的とする素子を得ることができるので、特性がウェフ
ァー毎にばらつく不都合を確実に回避できるものであ
る。EFFECTS OF THE INVENTION As described above, in the present invention, it is possible to achieve a sufficiently ohmic contact only by bringing a needle into contact with a high-concentration P-type GaAs-based compound semiconductor. Since the pinch-off voltage due to the P-type gate region of the lateral junction FET can be estimated,
This Vp is estimated during the manufacturing process, and based on this, the target element can be obtained by additionally adjusting the impurity introduction by the diffusion method of the target P-type region, so that the characteristics vary from wafer to wafer. Can be reliably avoided.
第１図〜第３図は本発明製法の一例の工程図、第４図は
本発明におけるピンチオフ電圧測定の説明図、第５図及
び第６図はそのＣ−Ｖ及びＲ−Ｖ特性曲線図、第７図〜
第９図はその現象説明図、第10図は等価回路図、第11図
は各部の寸法表示の説明図、第12図〜第15図はその特性
曲線図である。 （１）は基板、（７）はゲート領域、（8a）及び（8b）
は検出用領域、（9a）及び（9b）は探針、（11）は接合
型FET。1 to 3 are process diagrams of an example of the production method of the present invention, FIG. 4 is an explanatory diagram of pinch-off voltage measurement in the present invention, and FIGS. 5 and 6 are C-V and R-V characteristic curve diagrams thereof. , Fig. 7 ~
FIG. 9 is an explanatory diagram of the phenomenon, FIG. 10 is an equivalent circuit diagram, FIG. 11 is an explanatory diagram of the dimension display of each part, and FIGS. 12 to 15 are characteristic curve diagrams thereof. (1) is the substrate, (7) is the gate region, (8a) and (8b)
Is a detection area, (9a) and (9b) are tips, and (11) is a junction FET.
Claims (1)
果トランジスタのチャンネル層となる第1n型ウエル領域
と、ピンチオフ電圧検出用の第2n型ウエル領域とを同時
に不純物を導入する第１の工程と、 上記第1n型ウエル領域中にゲートとなるＰ型領域と、上
記第2n型ウエル領域中に少なくとも２つの特性検出用の
Ｐ型領域とを同時に不純物を導入する第２の工程とを含
み、 少なくとも一回、上記２つの特性検出用のＰ型領域に、
特性検出用探針を接触させ、該探針間のインピーダンス
のバイアス電圧特性を測定して、直列成分のピークを与
える電圧をもって上記Ｐ型ゲート領域のピンチオフ電圧
を推定した後、上記第1n型ウエル領域中にゲートとなる
Ｐ型領域と、上記第2n型ウエル領域中に少なくとも２つ
の特性検出用のＰ型領域とを同時に不純物を導入する第
３の工程を追加することにより所要のピンチオフ電圧を
設定することを特徴とする横型接合型電界効果トランジ
スタの製法。1. A first step of introducing an impurity into a compound semiconductor substrate at the same time as a first n-type well region serving as a channel layer of a lateral junction field effect transistor and a second n-type well region for detecting a pinch-off voltage. And a second step of simultaneously introducing impurities into the first n-type well region to serve as a gate and at least two P-type regions for detecting characteristics in the second n-type well region. , At least once in the P-type region for detecting the above two characteristics,
The characteristic detection probe is brought into contact, the bias voltage characteristic of the impedance between the probes is measured, and the pinch-off voltage of the P-type gate region is estimated by the voltage that gives the peak of the series component. A required pinch-off voltage is obtained by adding a third step of simultaneously introducing impurities into the P-type region serving as a gate in the region and at least two P-type regions for detecting characteristics in the second n-type well region. A method of manufacturing a lateral junction field effect transistor characterized by setting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58213872A JPH0810698B2 (en) | 1983-11-14 | 1983-11-14 | Manufacturing method of lateral junction field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58213872A JPH0810698B2 (en) | 1983-11-14 | 1983-11-14 | Manufacturing method of lateral junction field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60106177A JPS60106177A (en) | 1985-06-11 |
| JPH0810698B2 true JPH0810698B2 (en) | 1996-01-31 |
Family
ID=16646411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58213872A Expired - Lifetime JPH0810698B2 (en) | 1983-11-14 | 1983-11-14 | Manufacturing method of lateral junction field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810698B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4608717B2 (en) * | 1999-12-28 | 2011-01-12 | ソニー株式会社 | Pinch-off voltage measuring circuit for transistor, manufacturing method thereof, and manufacturing method of field effect transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5931074A (en) * | 1982-08-13 | 1984-02-18 | Mitsubishi Electric Corp | Manufacture of electrostatic induction transistor |
| JPS5972180A (en) * | 1982-10-18 | 1984-04-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1983
- 1983-11-14 JP JP58213872A patent/JPH0810698B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5931074A (en) * | 1982-08-13 | 1984-02-18 | Mitsubishi Electric Corp | Manufacture of electrostatic induction transistor |
| JPS5972180A (en) * | 1982-10-18 | 1984-04-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60106177A (en) | 1985-06-11 |
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