JPH06244257A - Decision of impurity concentration in semiconductor substrate - Google Patents

Abstract

PURPOSE:To make it possible to lessen a decision error of an impurity concentration in a semiconductor substrate and to make it possible to lessen also an irregulatity in the imprity concentration by a method wherein an impurity concentration distribution in the depth direction in the substrate is found using a C-V method the arithmetic mean value of an impurity concentration in the extent of a certain depth is decided as the impurity connection in the substrate. CONSTITUTION:In the case where an impurity concentration in a semiconductor substrate is decided utilizing a capacity-voltage method (a C-V method), an impurity concentration distribution in the depth direction in the substrate is found using the C-V method, the arithmetic means value of an impurity concentration in the extent of a certain depth is computed to the impurity concentration distribution and the mean value is decided as the impurity concentration in the substrate. For example, a MOS capacitor, which corresponds to a channel part 10 of a surface channel n-MOS transistor and has an impurity concentration distribution, is formed on a P-type Si substrate. With respect to the impurity concentration distribution of the MOS capacitor a measurement is taken using a C-V method, and after an impurity concentration distribution in the depth direction as shown in the diagram is obtained on the basis of the result measured using the C-V method, the arithmetic mean value of an impurity concentration distribution in the extent of A in the diagram is found and the mean value is decided as an impurity concentration in the substrate.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention is a non-destructive and simple method for obtaining an impurity concentration distribution in a depth direction in a semiconductor substrate by using a CV method, and using the result, a method for determining a substrate impurity concentration. It is about.

[0002]

2. Description of the Related Art In conventional LSI process development, generally, a method for obtaining an impurity concentration distribution is a method such as SIMS, SR method (spread resistance method) + chemical etching, in which a sample must be destroyed, and a sample such as CV method. Is divided into methods that can be measured without destroying
The former cannot measure in a wafer state, and the latter can. In determining the impurity concentration of the semiconductor substrate which influences the device characteristics of the transistor, which is the heart of the LSI, especially the threshold voltage (Vth), the impurity concentration distribution in the depth direction in the semiconductor substrate is obtained by the CV method. In this method, the impurity concentration at the position corresponding to 90% of the maximum depletion layer width is used as the substrate impurity concentration. In this method, the accuracy of the impurity concentration distribution in the depth direction in the semiconductor substrate is important. Become. Generally, when the measurement capacitance becomes small, the error due to disturbance becomes large and the accuracy of the obtained impurity concentration distribution deteriorates.As a result, if the impurity concentration at one point in the depth direction as described above is taken as the substrate impurity concentration, the variation in the value will occur. , May grow. In the LSI process development, the reliability of the process is important and a large number of measurements are required. As a result, it is not possible to identify the variation due to the process unless the variation in the measurement is minimized. Process development becomes less efficient.

[0003]

An object of the present invention is to provide a method of determining the impurity concentration of a semiconductor substrate which can reduce the determination error of the impurity concentration of the substrate and has a small variation.

[0004]

[Structure] In LSI process development, it is important how to stably create the device characteristics of the transistor at the heart of the process. In particular, it is important to control the impurity concentration distribution in the channel portion that determines the threshold voltage (Vth), which is one of the device characteristics of the transistor. However, in the case of an LSI using a MOS structure, as shown in FIG. In the portion, the same conductivity type impurity as that forming the well is made higher than the well concentration so that the threshold voltage (Vt
h) is controlled. On the other hand, the MOS structure that constitutes the channel portion of many transistors is C-
The V characteristic can be measured. From the C-V characteristic, the impurity concentration in the depth direction below the MOS interface can be obtained as shown in FIG. In the present invention, C
When obtaining the impurity concentration distribution in the semiconductor substrate in the depth direction using the -V method to determine the impurity concentration of the semiconductor substrate, the impurity concentration at one point in the depth direction is determined as in the prior art as described above. Instead of this, the arithmetic mean value of the impurity concentration in a certain range in the depth direction below the MOS interface is taken as the substrate impurity concentration. The range in the depth direction is preferably in the range of several tens to several hundreds nm from the semiconductor surface because the depletion width required until the transistor is turned on, that is, the semiconductor surface undergoes strong inversion, is sufficient. . Generally, from the principle of measurement of MOS CV characteristics, majority carriers accumulate at the interface within the Debye length (LD) from the surface, and it is impossible to accurately reflect the impurity concentration within that range (within the Debye length) to the CV characteristics. Therefore, in order to accurately determine the impurity concentration, it is desirable to obtain the impurity concentration deeper than LD, that is, within the range in which the impurity concentration is accurately reflected in the CV characteristics. The range is from the flat band state through the depletion state to immediately before the weak inversion state. As described above, if the impurity concentration distribution is obtained using the CV method which is non-destructive and simple, and the impurity concentration of the channel portion is determined by the method of the present invention with less variation, measurement on a 6-inch wafer is possible. In addition, if a pattern that enables accurate CV measurement is placed in the pattern of the mass-produced semiconductor substrate (wafer), it can be used as a process monitor of the impurity concentration of the channel part, and unexpected problems such as abnormal device characteristics can occur. It is possible to promptly respond to the occurrence.

[0005]

EXAMPLES The present invention will be described below based on examples. Example 1 A MOS capacitor having an impurity concentration distribution corresponding to the channel portion of a surface channel type nMOS transistor was manufactured on a P type Si substrate through the following process steps.・ P well formation (boron ion implantation, 5 × 10 ¹³ / c
m ² , 40 keV) ・ Boron ion activation ・ Channel formation (boron ion implantation, 4 × 10 ¹² /
cm ^2, 30 keV), a thermal oxide film formed (150Å) · n + Poly- Si gate formation (3000Å) · n + Poly- Si gate patterning (gate area: 1 mm ^2), etc., an interlayer insulating film formed without the same temperature history as the actual process. C-V measurement is performed on the MOS capacitor,
From the CV results, the impurity concentration distribution in the depth direction as shown in FIG. 2 was obtained. The point B in FIG. 2 is the value of the impurity concentration according to the conventional method, while the method according to the present invention obtains the arithmetic mean value of the impurity concentration distribution in the range A of FIG. 2 and sets it as the substrate impurity concentration. As a result, it was possible to obtain the substrate impurity concentration with good reproducibility no matter how many times the same MOS capacitor was measured.

In the method of determining the substrate impurity concentration by using the CV method, the impurity concentration distribution in the depth direction in the semiconductor substrate is obtained by using the CV method, and a certain depth with respect to the impurity concentration distribution is obtained. If the arithmetic mean value of the impurity concentrations in the range is defined as the substrate impurity concentration, the error and the variation can be reduced, and the substrate impurity concentration can be detected. Further, by providing a range in the depth direction for obtaining the arithmetic mean value of the impurity concentration in a region deeper than the Debye length from the substrate surface, the principle error of the CV method can be eliminated.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing the structure of a surface channel type CMOS transistor.

FIG. 2 is a diagram showing an impurity concentration distribution obtained from CV characteristics.

FIG. 3 is a diagram showing a comparison of impurity concentration calculation results of the present invention and a conventional method.

[Explanation of symbols]

1 gate electrode (excess N-type poly Si gate) 1'gate electrode (excess P-type poly Si gate) 2 gate oxide film 3 source 4 drain 5 excess P-type layer 6 excess N-type layer 7 P-type well 8 N-type well 9 Si substrate 10 channel part A The range of the depth direction used for calculation of the arithmetic mean value of the impurity concentration adopted in the example is shown. B In Example, the value of the substrate impurity concentration obtained by the conventional method is shown.

Claims (5)

[Claims] 1. A method for determining an impurity concentration of a semiconductor substrate by using a capacitance-voltage method (hereinafter, CV method), wherein C-
The impurity concentration distribution in the depth direction in the semiconductor substrate is obtained by using the V method, the arithmetic average value of the impurity concentration in a certain depth range with respect to the impurity concentration distribution is calculated, and the average value is taken as the substrate impurity concentration. A method for determining the impurity concentration of a semiconductor substrate, which is characterized by the above. 2. The semiconductor substrate impurity concentration determination according to claim 1, wherein the range in the depth direction for obtaining the arithmetic mean value of the impurity concentration is provided in a region deeper than the Debye length from the substrate surface. Method. 3. The method of determining the impurity concentration of a semiconductor substrate, wherein the impurities are impurities that form a channel portion and a well portion and have the same conductivity type. 4. A method for determining the impurity concentration of the channel portion of the transistor, wherein the impurity concentration of the channel portion of the MOS structure transistor is determined by the method according to claim 1, 2 or 3. 5. A semiconductor substrate, wherein an impurity concentration pattern that can be accurately measured by the CV method according to claim 1, 3 or 4 is formed in the semiconductor substrate.