JP2002289534A - Method for fabricating semiconductor device and method for sorting solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect an abnormal variation of concentration caused by so called N contamination in the vicinity of an interface at the time of epitaxial growth and to make it useful in the subsequent processing or in the sorting of characteristics. SOLUTION: The method for fabricating a semiconductor device comprises a step for forming a second conductivity type semiconductor region 12 in a part of the surface layer of a first conductivity type semiconductor 11 and growing an epitaxial growth layer 13 of a first conductivity type, second conductivity type or intrinsic semiconductor thereon. In the epitaxial growth process, a sheet of wafer from a production lot is epitaxially grown in advance, and the concentration (C1) of peak carrier in the second conductivity type semiconductor region 12 and the concentration (C2) of peak carrier having an abnormal variation in the vicinity of the boundary between the epitaxial growth layer 13 and the first conductivity type semiconductor 11 are actually measured for a preceding wafer. When the ratio of concentration (C2/C1) is not higher than a specified value, other wafer in the same production lot is subjected to expitaxial growth under the same conditions as those of the preceding wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for growing a first or second conductivity type or intrinsic impurity region on an impurity region of the second conductivity type. The present invention relates to a method of manufacturing a semiconductor device including a step of effectively detecting crystallinity and promoting crystal growth, and a method of selecting a solid-state imaging device using the detected value as a reference for characteristic selection.

[0002]

2. Description of the Related Art An element formation region of a semiconductor device is sometimes formed by crystal growth. For example, in the invention disclosed by the present applicant in Japanese Patent Application Laid-Open No. 9-331058, the first type of solid-state imaging device of the vertical overflow drain type is disclosed.
A conductive semiconductor substrate, a second conductive semiconductor region formed on the first conductive semiconductor substrate, and infrared light having a lower concentration than the second conductive semiconductor region formed on the second conductive semiconductor region. A first conductivity type, a second conductivity type, or an intrinsic region of the invention having a thickness that can be sufficiently absorbed, and a light receiving portion is formed on a surface of the first conductivity type, the second conductivity type, or the intrinsic semiconductor region; . Preferably, the first conductivity type, the second conductivity type or the intrinsic semiconductor region is formed by an epitaxial layer, the second conductivity type semiconductor region is formed by ion implantation, and the concentration is about 10 ¹⁴ to 10 ¹⁶ cm ^-3. Has become.

According to the solid-state imaging device described in this publication, a semiconductor substrate having a second conductivity type semiconductor region formed thereon has a lower concentration than the second conductivity type semiconductor region and a thickness sufficient to absorb infrared rays. A semiconductor region is formed. This makes it possible to form a so-called overflow barrier region (second conductivity type impurity region) at a depth where it is difficult to maintain good productivity when high-energy ion implantation is used. As a result, even when the vertical overflow drain structure is formed, an incident light component having a long wavelength such as infrared light contributes to the improvement of sensitivity. With the miniaturization of the solid-state imaging device and the reduction of the light receiving area, the sensitivity of the device has become an important issue, and it is expected that the above-mentioned invention will greatly advance the integration and sensitivity of the solid-state imaging device. Is done.

[0004]

However, when a semiconductor having a lower concentration is grown on a semiconductor region having a lower concentration than before, the semiconductor is affected by contamination and the like in various semiconductor forming steps performed so far. There is a problem of N-type that the conductivity type is likely to be n-type near the interface when performing crystal growth. If the degree of N-formation of the crystal growth layer is large, it becomes difficult to form a crystal growth layer having a desired impurity profile, and the influence on the device characteristics also increases.

[0005] For example, in the solid-state imaging device described in the above publication, the impurity concentration of the second conductivity type semiconductor region is 10 ¹⁴
As low as to 10 ¹⁶ cm ^-3, thereon which is lower than the concentration first conductivity type, the second conductivity type or intrinsic semiconductor region grown (hereinafter, the semiconductor region of the epitaxial layer). Before the crystal growth, cleaning, oxidation, photolithography,
In each of the steps of ion implantation and oxide film stripping, and the cleaning step before crystal growth, the dopant impurities in the second conductivity type impurity region may be contaminated. Specifically, the contamination may be that the surface of the second conductivity type impurity region is N-type. Thereafter, the impurity due to the N-contamination mixes into the interface of the lower-concentration semiconductor region, which grows on the second conductivity type impurity region, and the overflow barrier concentration fluctuates. This is a factor that greatly varies the substrate voltage Vsub for obtaining the height. In addition, the fluctuation of the overflow barrier density causes a color mixing defect between pixels in the solid-state imaging device.

Various devices have been managed to prevent this N-nitrification, but it is difficult at present to control contamination at an extremely low concentration of 10 ¹⁴ cm ^-3, and measures to prevent N-nitration are not possible. That's enough. Furthermore, under the present circumstances, it is not possible to confirm in advance the above N ^- level of 10 ¹⁴ cm ⁻³ . That is, unless the solid-state imaging device is actually formed after the epitaxial layer is actually formed, the fluctuation of the overflow barrier density and the degree of color mixing between pixels based on the fluctuation cannot be known. As a result, there has been a problem that it is not possible to prevent a situation in which the substrate voltage Vsub for obtaining a predetermined change in the height of the overflow barrier varies greatly or a large amount of color mixing failure between pixels occurs.

A first object of the present invention is to effectively detect contamination near an interface when growing a first, second conductivity type or intrinsic impurity region on a second conductivity type impurity region,
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can suppress the occurrence rate of defects by reflecting the detection result in subsequent steps. A second object of the present invention is to provide a method of selecting a solid-state imaging device using the above detection result as one of the criteria for determining the quality of a solid-state imaging device after completion.

[0008]

In order to achieve the first object, a method of manufacturing a semiconductor device according to a first aspect of the present invention includes a method of manufacturing a semiconductor device according to a first aspect of the present invention. Forming a semiconductor region of the first type, and crystal-growing a crystal growth layer made of a first, second, or intrinsic semiconductor on the second conductivity type semiconductor region and on the surrounding first conductivity type semiconductor. Wherein the step of crystal growth comprises the following steps, that is, one of a plurality of wafers constituting a production lot of the semiconductor device is first crystal-grown, and The peak carrier concentration (C1) of the semiconductor region of the conductivity type and the peak carrier concentration (C2) of the abnormal concentration change formed near the boundary between the crystal growth layer and the semiconductor of the first conductivity type are calculated in advance. Measured on a wafer with crystal growth, The ratio of the peak carrier concentration (C2 /
When C1) is equal to or less than a predetermined value, the method includes the steps of crystal growing another wafer in the production lot under the same conditions as the preceding wafer. The peak carrier concentration ratio (C2
When / C1) is larger than a predetermined value, it is preferable to change at least one of the conditions related to crystal growth including the pretreatment from the time of the preceding wafer crystal growth according to the value. Another wafer in the production lot is crystal-grown. In addition, the impurity concentration of the crystal growth layer is equal to the second impurity concentration.
The concentration is lower than the concentration of the second conductivity type impurity in the semiconductor region of the conductivity type.

This method of manufacturing a semiconductor device is suitable for a method of manufacturing a solid-state imaging device. That is, the semiconductor device is a solid-state imaging device, the first conductivity-type semiconductor is a first conductivity-type semiconductor substrate of the solid-state imaging device, or a first conductivity-type semiconductor layer formed on the semiconductor substrate. The method comprises the following steps:
Ion implantation into the conductive semiconductor to form the second conductive semiconductor region functioning as an overflow barrier layer,
The steps of crystal growth including crystal growth of the preceding wafer, measurement of the two peak carrier concentrations, and crystal growth of another wafer are performed to form a solid-state imaging device on the crystal growth layer. An impurity concentration of the crystal growth layer is lower than a concentration of the second conductivity type impurity in the second conductivity type semiconductor region.
Further, the crystal growth layer is grown to a predetermined thickness in a range where infrared light incident from the upper surface is sufficiently absorbed. In a solid-state imaging device satisfying these requirements, the value of the ratio (C2 / C1) of the peak carrier concentration used as a criterion for determining the quality of the crystal growth is preferably 0.2.

In this method of manufacturing a semiconductor device, the degree of surface contamination of the impurity region of the second conductivity type strongly correlates with the ratio of the peak carrier concentration (C2 / C1). Therefore, when this concentration ratio is equal to or less than a certain value, for example, 0.2 or less, subsequent wafers in the same lot grow under the same conditions. When this concentration ratio is larger than a certain value, for example, 0.2, crystal growth can be continued by changing at least one of the conditions related to crystal growth including pretreatment. As a result, quality degradation of the crystal growth layer due to surface contamination of the impurity region of the second conductivity type is effectively avoided. If the above concentration ratio greatly exceeds the reference value, for example, the lot is discarded.

In order to achieve the above-mentioned second object of the present invention, a method for selecting a solid-state imaging device according to a second aspect of the present invention comprises the steps of: Forming a semiconductor region of the first type, and crystal-growing a crystal growth layer made of a first, second, or intrinsic semiconductor on the second conductivity type semiconductor region and on the surrounding first conductivity type semiconductor. A method for selecting a solid-state imaging device manufactured through a process including the following, wherein the crystal growth step is performed using the same manufacturing apparatus under the same conditions, comprising a manufacturing lot of a semiconductor device. One of a plurality of wafers is first crystal-grown, and the peak carrier concentration (C1) of the second conductivity type semiconductor region and the vicinity of the boundary between the crystal growth layer and the first conductivity type semiconductor are determined. Abnormal concentration change in the crystal growth layer And the peak carrier concentration (C2) of the solid-state imaging device after completion of the above-described process. ) Is used as one of the selection criteria.

Preferably, the impurity concentration of the crystal growth layer on which the solid-state imaging device is formed is lower than the concentration of the second conductivity type impurity in the second conductivity type semiconductor region functioning as an overflow barrier layer. In the selection of a solid-state imaging device in which the thickness of the crystal growth layer is set to a predetermined thickness within a range in which infrared light incident from the upper surface is sufficiently absorbed,
The value of the ratio (C2 / C1) of the peak carrier concentration 0.2
Is used as one of the criteria for selecting wafers predicted to have good color mixing characteristics.

In this method for selecting a solid-state imaging device, the data relating to the above-mentioned concentration ratio obtained during the manufacturing process is referred to, and the characteristics related to the quality of the crystal growth layer, such as poor color mixture, are given to the completed solid-state imaging device. And the degree of variation in substrate voltage.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. Here, an example in which the present invention is applied to an interline transfer type CCD will be described. The present invention can be widely applied without being limited to a transfer method such as a frame interline transfer method or a frame transfer method.

FIG. 1 is a block diagram showing a schematic configuration of a CCD according to this embodiment. This CCD includes an imaging unit 1,
It comprises a horizontal transfer unit 2 and an output unit 3. Output unit 3
Although not particularly shown, has an output gate unit, a charge-to-voltage conversion unit constituted by, for example, a floating gate amplifier or a floating diffusion amplifier, and a reset gate unit.

The imaging section 1 includes a light receiving section 4 for performing photoelectric conversion,
The pixel 7 including the read gate unit 5 and the vertical transfer unit 6 is
A large number of them are arranged in a planar matrix.
Each pixel 7 is separated by a channel stop (not shown) so as not to cause electrical interference. The vertical transfer units 6 are shared by columns of the light receiving unit 4 and are arranged in a predetermined number in the row direction. A four-phase vertical transfer clock signal for driving the vertical transfer unit 6 is input to the imaging unit 1. In the horizontal transfer unit 2,
A two-phase horizontal transfer clock signal for driving this is input. The horizontal transfer unit 2 and the vertical transfer unit 6 are formed by repeatedly separating a potential well of a minority carrier formed by introducing an impurity into a surface side in a semiconductor substrate and a substrate via a dielectric film. Multiple electrodes (transfer electrodes)
And The above-described four-phase or two-phase transfer clock signals are applied to these transfer units 2 and 6 with their phases periodically shifted to the transfer electrodes. The transfer units 3 and 7 are controlled by the transfer clock signal applied to the transfer electrode, and the potential distribution of the potential well changes sequentially, and transfers the charges in the potential well in the phase shift direction of the transfer clock signal. It functions as a so-called shift register. Hereinafter, the vertical transfer unit is referred to as a vertical transfer register, and the horizontal transfer unit is referred to as a horizontal transfer register.

FIG. 2 is a horizontal sectional view of one pixel taken along the line AA in FIG. This CCD has an n-type silicon substrate 10 on which an n-type (hereinafter referred to as n ^- type) first epitaxial layer 11 having a lower impurity concentration is formed. First epitaxial layer 11
Is formed by crystal growth of single crystal silicon. First
Part of the surface layer of the epitaxial layer 11, that is, the imaging unit 1
A p-type semiconductor impurity region 12 is formed at a location corresponding to. Since the p-type semiconductor impurity region 12 is not formed in the surface layer of the first epitaxial layer 11 except for the imaging unit 1 not shown in FIG. 2, the n-type first epitaxial layer 11 appears on the surface. I have. Then, on the p-type semiconductor impurity region 12 and around n
N-type (hereinafter referred to as n ⁻ -type) having a lower concentration than the first epitaxial layer 11 on the first type epitaxial layer 11.
Of the second epitaxial layer 13 is formed. The second epitaxial layer 13 corresponds to the “crystal growth layer” of the present invention, and is formed by a crystal growth method.

The vertical transfer level in the second epitaxial layer 13 is
A potential well is formed at the position corresponding to the
An n-type transfer channel region 15 to be formed is formed.
The n-type transfer channel region 15 is long in the vertical transfer direction,
The entire part 1 is formed, for example, in a parallel stripe shape.
I have. On the deep side of the substrate in the n-type transfer channel region 15, p ⁺ 
A high-concentration impurity region 16 is formed. This p⁺ 
On the substrate bulk side due to the presence of the
The generated charges are prevented from flowing into n-type transfer channel region 15.
As a result, smear is effectively suppressed.
It should be noted that the n-type transfer channel region 15 also has p
Type impurity region, and make the transfer channel a buried type.
You may. In this case, the signal charge peaks due to the substrate surface level.
And vertical transfer efficiency is improved.

The light receiving section in the second epitaxial layer 13
In the position corresponding to 4, n^- Type impurity region (signal charge storage
(Product area) 18 is formed. Also, n^- Mold impurities
On the substrate surface side of the region 18, p⁺⁺Type
An impurity region (positive charge storage region) 19 is formed.
As a result, the cross section in the vertical direction of the substrate becomes P⁺⁺-N^- -N ^-
A so-called HAD (Hole Accumulated Diode) with -P structure
A photodiode PD called a sensor is formed.
You. The light incident on the photodiode PD undergoes photoelectric conversion.
Is converted to generate signal charges (electrons).
^- It is accumulated for a certain time in the impurity region 18 of the mold. Also,
When the incident light is strong, the extra charges are transferred to the p-type impurity region 1.
Overflows from OFB (Over Flow Barrier) formed by
Discarded on the substrate side. OFB height on substrate 10
It can be changed by the applied substrate voltage Vsub.
You. By changing the substrate voltage Vsub, the signal charge
Changes the accumulation time and changes the accumulation time to activate the shutter function.
Is achieved.

Another cell adjacent to the light receiving section 4 on the right side of FIG. 2 with a vertical transfer section (not shown) of another cell, or another cell adjacent to the above-described vertical transfer section 6 on the left side of FIG. A channel stop region 17 composed of ap ⁺ -type high-concentration impurity region is formed between the light-receiving portion (not shown). The channel stop region 17 includes the photodiode P
The impurity regions 18 and 19 constituting D also extend to the other two sides not shown in FIG. As a result, interference of signal charges between cells in the horizontal and vertical directions is effectively prevented.

The n ⁻ -type impurity region located between the n-type transfer channel region 15 of the vertical transfer register 6 and the n ⁺ -type impurity region 18 of the light receiving section 4 becomes a read gate region.
Note that a low-concentration p-type impurity region for adjusting the height of the potential barrier of the read gate may be formed in this region.

The n ^{− −} in which these various impurity regions are formed
The second epitaxial layer 13 of the mold is covered with a dielectric film 14. Although the dielectric film 14 is depicted as a single layer in FIG. 2, actually, the upper and lower oxide films (for example, a silicon dioxide film) are interposed between the vertical register 6, the read gate unit 5, and the channel stop region. It is a dielectric film having a three-layer structure including a nitride film (for example, a silicon nitride film) having a charge storage capability. This is mainly because the threshold voltage of the read gate portion is changed to enable adjustment of anti-blooming characteristics. A vertical transfer electrode 20 made of, for example, polysilicon is formed over the read gate unit 5, the vertical transfer register 6, and the channel stop region where the three dielectric films 14 are formed. Although not shown, the vertical transfer electrodes 20 are repeatedly arranged in the vertical transfer direction while partially overlapping the vertical transfer electrodes made of other polysilicon layers. Further, the vertical transfer electrode 20 also functions as a control electrode of the read gate unit 5. The surface of the vertical transfer electrode 20 and the surface of the dielectric film 14 in the light receiving section 4 are, for example, PS
It is covered with an interlayer insulating film 21 made of G, SiO ₂ or the like. Light receiving section 4 covering the upper and side surfaces of vertical transfer electrode 20
A light-shielding film 22 having an opening above is formed on the interlayer insulating film 21. The light shielding film 22 is made of, for example, a metal material such as Al and W.

Hereinafter, a method of manufacturing the CCD will be described with reference to FIGS. Here, FIG.
(A) to (C) are cross-sectional views corresponding to the entire imaging unit,
4 to 6 are cross-sectional views in the horizontal transfer direction showing a portion corresponding to one pixel in an enlarged manner.

First, as shown in FIG. 3A, a silicon substrate 10 manufactured by the CZ method is prepared. Silicon substrate 10 has, for example, a (100) main surface, is doped with phosphorus and has n-type conductivity, and has a specific resistance of about 8 to 12 Ω · cm. Here, the size of the silicon substrate 10 was 8 inches in diameter. Crystal growth is performed on the silicon substrate 10 to form an n ⁻ -type first epitaxial layer 11 having a lower concentration than the silicon substrate. For example, n ^- type single crystal silicon having a specific resistance of about 40 to 50 Ω · cm is grown to about 8 μm at a temperature of 1030 ° C. using a single-wafer CVD furnace.

As shown in FIG. 3B, a p-type impurity region 12 is formed in a part of the surface of the n ⁻ -type first epitaxial layer 11. Specifically, an oxide film to be used as a through film at the time of ion implantation is formed on the first epitaxial layer 11, a mask layer is formed on the oxide film so as to open the entire image pickup unit 1, and the mask layer is opened. Implants a p-type impurity into the first epitaxial layer 11 through. For example, boron ions B ⁺ are implanted at an energy of 700 eV and a dose of 1 × 10 ¹¹ / cm ⁻² . afterwards,
Strip the oxide film.

Next, as shown in FIG. 3C, the first epitaxial layer 11 is formed on the p-type impurity region 12 and on the n ⁻ -type first epitaxial layer 11 exposed therearound.
Lower concentration and higher resistance n ⁻ -type second epitaxial layer 1
3 is formed by crystal growth. For example, single-wafer CV
Using a furnace D at a temperature of 1150 ° C, the specific resistance is 500Ω
9-11 μm of n ⁻ -type single crystal silicon larger than 10 cm
To grow. The formation of the second epitaxial layer 11 is performed by first selecting one preceding wafer from a production lot.

An SR (Spreading Resistance) measurement shown in FIG. 3D is performed on the preceding wafer. In particular,
After the preceding wafer is obliquely polished and stained, SR
Move the measurement terminals and examine the distribution of resistance as a function of distance from the surface. FIG. 7 shows an example of a measurement result obtained by converting the resistance distribution in the depth direction into a carrier concentration distribution. As shown in FIG. 7, the measurement of the SR distribution in the depth direction is performed by the imaging unit 1.
This is performed at a portion where the p-type impurity region 12 other than the above is not formed, and is converted into a carrier concentration. FIG. 7 shows the concentration distribution in the case where N-formation is present on the crystal growth surface and the concentration distribution in the case where there is no N-formation on the crystal growth surface.

Cleaning, oxidation, photolithography, ion implantation, and the like performed during the formation of the p-type impurity region 12 described above.
The dopant impurities in the p-type impurity region 12 may be contaminated in each step of removing the oxide film and in the cleaning step before the crystal growth. This is generally referred to as N-type, but similar contamination also exists on the surface of the first epitaxial layer 11 around the p-type impurity region 12. Therefore, if an extremely low-concentration (high-resistance) epitaxial layer 13 is formed on the contaminated surface, the n-type becomes stronger near the interface of the high-resistance epitaxial layer 13 due to the influence of the contamination, and the n-type epitaxial layer 13 is formed.
As shown in FIG. The distance from the peak concentration C2 to the concentration curve when there is no N-conversion is the concentration increase due to N-conversion.

In the above SR measurement, the peak carrier concentration C1 of the p-type impurity region 12 is measured. In the present invention, the ratio (C2 / C1) of the peak carrier concentration C2 to the peak carrier concentration C1 of the p-type impurity region 12 is used as a parameter for determining the quality of the epitaxial substrate. The reason for using this parameter is described below.

The inventor of the present invention believes that the color mixing defect between pixels of a solid-state image sensor is affected by the formation of an epitaxial substrate.
Consider the history (process data) of various elements distributed over a wide range from good to bad in color mixing failure,
As a result of examining wafers in the same lot as the device in which the color mixture defect occurred, it was found that N-type had a great influence on the color mixture defect. Then, the above-described concentration ratio (C2 / C1)
However, it was found that there was an extremely strong correlation with poor color mixing. FIG. 8 shows the correlation diagram. FIG. 8 focuses on a sample in which the color mixing defect of a 1/3 inch, 380,000 pixel CCD solid-state imaging device varies, and the vertical axis represents the typical color mixing defect rate of the same wafer as the device, and the same as the wafer. It is a graph which plotted the concentration ratio (C2 / C1) of the preceding wafer in the lot on the horizontal axis.

From this graph, it can be seen that as the density ratio (C2 / C1) increases, the color mixing defect rate sharply increases with the value at 0.2. Therefore, the concentration ratio (C2 /
By setting C1) to 0.2 or less, a color mixing defect rate of less than 1% can be achieved. Further, a color mixing defect starts to appear little by little around a density ratio (C2 / C1) of around 0.1. Therefore, more preferably, by setting the density ratio (C2 / C1) to 0.1 or less, the color mixing defect rate can be reduced to almost 0%. Under the condition that the concentration ratio (C2 / C1) is 0.2 or less, the substrate voltage Vsu for achieving a predetermined overflow barrier height is set.
It was confirmed that the value of b hardly varied.

The relationship between the defective color mixing ratio and the density ratio (C2 / C1) was examined for other CCD solid-state imaging devices having a similar structure. As a result, it was concluded that when the vertical overflow drain structure was adopted, the color mixing defect rate rapidly increased when the concentration ratio (C2 / C1) exceeded a certain boundary value, and the substrate voltage Vsub was stable below the boundary value. Obtained.

For the above reason, the density ratio (C) shown in FIG.
In the (2 / C1) determination, when the concentration ratio (C2 / C1) is 0.2 or less, it is determined that the state and conditions of the crystal growth apparatus that performed the preceding wafer are good. Therefore, the second epitaxial layer 13 shown in FIG. 3C is formed on another wafer in the same lot as the passed preceding wafer by using the same apparatus as the preceding wafer under the same conditions. On the other hand, when the concentration ratio (C2 / C1) is larger than 0.2, crystal growth is not performed under the same conditions as the preceding wafer. Then, it is desirable to change the way of handling according to the magnitude of the density ratio. For example, if the concentration ratio slightly exceeds 0.2, the concentration ratio can be reduced to 0.2 or less by adjusting the doping amount of PH ₃ during crystal growth. However, if the concentration ratio is up to a certain level, the cleaning conditions of the subsequent wafer are reviewed, for example, by washing a plurality of times or using another cleaning method, and the cleaning conditions are changed alone or in combination with the growth conditions. If the concentration ratio is still higher, the wafer is discarded and the process is repeated from the first formation of the first epitaxial layer. The criterion for determining the concentration ratio is not limited to 0.2 or less, and may be a smaller value, for example, 0.1 or less. In addition, the second epitaxial layer 13 of the present example includes:
The photodiode PD is set to be thick in order to have the sensitivity in the infrared region, but may be thin if the sensitivity is not high.

According to the above steps, the second conductivity type semiconductor region 12 is formed in the first conductivity type semiconductor (first epitaxial layer 11).
And an epitaxial substrate for a CCD solid-state imaging device having the second epitaxial layer 13 thereon is formed.

In FIG. 4, first, a dielectric film 14 is formed on the surface of the n ⁻ -type second epitaxial layer 13. The dielectric film 14 is, for example, a laminated film (ONO film) of a silicon dioxide film / silicon nitride film / silicon dioxide film. Next, various impurity regions are formed in the n ⁻ -type second epitaxial layer 13. Specifically, a mask layer having a predetermined pattern is formed on the dielectric film 14, and the dielectric film 14 is formed through an opening of the mask layer.
Is used as a through film to ion-implant an n-type or p-type impurity under necessary conditions. By repeating the formation of the mask layer and the ion implantation, the n-type transfer channel region 15 constituting the vertical transfer register, the p ⁺ -type high-concentration impurity region 16 thereunder, and the p ⁺ -type channel stop region 17 are formed. Are formed respectively.

As shown in FIG. 5, a transfer electrode 20 is formed on the dielectric film 14. When the transfer electrode has two layers, deposition and patterning of the first polycrystalline silicon, formation of an interlayer dielectric film, and deposition and patterning of the second polycrystalline silicon are performed in this order.

As shown in FIG. 6, an n-type impurity is ion-implanted in the light receiving section 4 to form an n ⁻ -type signal charge storage region 18. In addition, p-type impurities are ion-implanted to form ap ⁺ -type positive charge storage region 19 in the upper layer. In this ion implantation, the ONO film (dielectric film) 14 may be left attached, but prior to the ion implantation, the ONO film 14 of the light receiving section 4 is removed using the transfer electrode 20 as a mask, and the light receiving section 4 is removed.
May be formed again, and the single-layer silicon dioxide film may be used as a through film. Or ON
The ion implantation may be performed while leaving the silicon dioxide film at the lowermost layer of the O film.

Thereafter, activation annealing is performed if necessary. As shown in FIG. 2, for example, PSG or Si is formed on the transfer electrode 20 and the dielectric film 14 of the light receiving section 4.
An interlayer insulating film 21 made of O ₂ is deposited. Further, a metal film serving as the light-shielding film 22 is formed on the interlayer insulating film 21, and is patterned to open above the light receiving unit 4. Further, if necessary, an interlayer insulating film, an in-layer concave lens, a color filter, an OCL (On Chip Lens) are formed, and the CCD is formed.
To complete.

The embodiment of the method for manufacturing a solid-state imaging device according to the present invention is not limited to the above description. For example, an MCZ substrate grown by the MCZ (Magnetic field Czochralski) method may be used instead of the CZ substrate. When an MCZ substrate is used, the surface of the MCZ substrate is subjected to neutron doping to convert silicon into phosphorus without forming the first epitaxial layer 11, and the second conductive type layer becomes OFB.
The conductive impurity region 12 may be formed. The reason for forming the first epitaxial layer 11 on the CZ substrate is as follows.
This is because, when the OFB is formed directly on the Z substrate, the image contrast varies due to the dopant concentration unevenness of the CZ substrate. Since the MCZ substrate has almost no such dopant concentration unevenness, the first epitaxial layer 11 can be omitted by the above-described method. Another reason for providing the first epitaxial layer 11 is to adjust the so-called shutter voltage. If this is not necessary, the first prerequisite is to use an MCZ substrate.
The epitaxial layer 11 can be omitted.

The epitaxial substrate has a low resistance in its formation.
Using a substrate and / or prior to crystal growth
Forming a buried region with low resistance
The series resistance in the region below the axial layer can be reduced.
Noh. Therefore, if an epitaxial substrate is used,
To produce the desired energy barrier change in the device
Drive voltage and applied voltage to the board are reduced, resulting in lower power consumption
This is advantageous for empowerment. Formation of silicon epitaxial substrate
As a practical method, chemical vapor deposition (CVD; Chem)
ical Vapor Diposition). This CVD
Is SiCl_Four Or SiHCl_Three Is the source gas
Hydrogen reduction method used or SiH _Two Cl_Two Or S
iH_Four Is carried out by a pyrolysis method using
It is. The first and second epitaxial layers 11 described above,
In the formation of 13, any method may be used.

Although the second conductivity type impurity region 12 is formed by ion implantation, it can be formed by, for example, a diffusion method.

In the above embodiment, a p-type well may be formed in the second epitaxial layer 13, and a CCD solid-state imaging device may be formed in the p-type well. Also, C
The present invention can be applied to the manufacture of a solid-state imaging device other than a CD, for example, an amplification-type solid-state imaging device or a CMOS-type solid-state imaging device, so that color mixing between pixels can be suppressed and the substrate voltage can be stabilized. Furthermore, even solid-state imaging devices other than CCDs, and even other semiconductor devices, have a crystal growth layer and are likely to have an abnormal concentration near the crystal growth interface due to a low impurity concentration. The invention is widely applicable. In addition, without departing from the gist of the present invention,
Various modifications are possible.

This wafer evaluation method can be applied not only to selection of wafers in a wafer process but also to selection of characteristics of semi-finished products completed in a wafer state or products of a solid-state imaging device completed by packaging. Specifically, data of the above-mentioned concentration ratio (C2 / C1) is accumulated for each lot. Since a production lot of a semi-finished product in a wafer state or a product after packaging is usually managed, if the lot number is checked, the concentration ratio (C2 / C1) in the lot can be found. Therefore, the fact that the concentration ratio is, for example, 0.2 or less (or 0.1 or less) is used as a selection criterion for semi-finished products or products having good color mixing characteristics and small substrate voltage fluctuation. Thereby, the subsequent measurement of the color mixing characteristics and the like can be efficiently performed. For example, in the case where the color mixing characteristics are classified, the sorting efficiency increases, and when the density ratio is 0.1 or less, it is possible to omit a specific measurement item.

[0044]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, the result of detecting the concentration ratio of the preceding wafer is reflected on the conditions for crystal growth of the succeeding wafer or the disposal is determined. be able to. For this reason, the quality of the crystal growth layer is high, the characteristics of the semiconductor device are good, the occurrence of a large number of defects can be effectively prevented, the yield can be improved, and the manufacturing cost can be suppressed. In addition, since appropriate measures are taken at an early stage of the semiconductor device manufacturing process, a production plan can be easily set. When this manufacturing method is applied to a solid-state imaging device, if a density ratio of 0.2 or less is regarded as a passing wafer, color mixing defects can be reduced to 1% or less. Further, the voltage (so-called substrate voltage) applied from the first conductivity type semiconductor side to determine the height of the potential barrier (so-called overflow barrier) formed by the second conductivity type impurity region is stabilized. That is, when a constant substrate voltage is applied, the height of the overflow barrier does not vary.

In the method for selecting a solid-state imaging device according to the second aspect of the present invention, characteristics of the solid-state imaging device after completion can be selected by referring to the data of the concentration ratio obtained during the manufacturing. This saves time and money in the final property check.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a CCD according to an embodiment.

FIG. 2 is a cross-sectional view of the CCD according to the embodiment in the horizontal transfer direction for one pixel along the line AA in FIG. 1;

FIGS. 3A to 3C are cross-sectional views showing the steps up to the formation of an epitaxial substrate in the manufacture of the CCD according to the embodiment. (D) is a diagram showing a process of determining a concentration ratio by SR measurement in the manufacture of the CCD according to the embodiment.

FIG. 4 is a cross-sectional view of one pixel in a horizontal transfer direction after the formation of an impurity region in a vertical transfer portion and a channel stop region in the manufacture of the CCD according to the embodiment.

FIG. 5 is a cross-sectional view of one pixel in a horizontal transfer direction after vertical transfer electrodes are formed in the manufacture of the CCD according to the embodiment.

FIG. 6 is a cross-sectional view in the horizontal transfer direction of one pixel after the impurity region of the light receiving section is formed in the manufacture of the CCD according to the embodiment.

FIG. 7 is a graph showing an example of a carrier concentration distribution in a depth direction based on SR measurement according to the embodiment of the present invention.

FIG. 8 illustrates a 1/3 inch, 38, embodiment of the present invention.
9 is a graph showing a relationship between a color mixing defect rate of a 10,000-pixel CCD solid-state imaging device and a corresponding density ratio (C2 / C1) of a preceding wafer.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 imaging unit 2 horizontal transfer unit 3 output unit 4 light receiving unit 5 readout gate unit 6 vertical transfer unit 7 pixel 10 silicon substrate (semiconductor substrate) 11 first An epitaxial layer (first conductivity type semiconductor), 12 ... p-type impurity region, 13 ... second epitaxial layer (crystal growth layer),
14, 14a dielectric film, 15 vertical transfer channel region, 16 high-concentration impurity region, 17 channel stop region, 18 signal charge storage region, 19 positive charge storage region, 20 vertical transfer electrode, 21 Interlayer insulating film, 22 ... light shielding film.

Continued on the front page F-term (reference) 4M106 AA01 AA10 CB30 DJ38 4M118 AA05 AA09 AB01 BA12 BA13 CA04 DA02 DA05 DB03 DB06 DB08 DD03 DD04 DD12 EA20 FA06 FA13 FA26 5F045 AA01 AA03 AC01 AC03 AC05 BB08 CA13 DA70 GB11

Claims (9)

[Claims] A second conductivity type semiconductor region formed in a part of a surface layer of the first conductivity type semiconductor; and a second conductivity type semiconductor region and a first conductivity type semiconductor surrounding the second conductivity type semiconductor region. A method for manufacturing a semiconductor device, comprising: a step of crystal-growing a crystal growth layer made of a second conductivity type or an intrinsic semiconductor, wherein the crystal growth step comprises the following steps: Crystal growth of one of a plurality of wafers constituting the wafer occurs first, and the peak carrier concentration (C
1) and the peak carrier concentration (C2) of the abnormal concentration change formed in the vicinity of the boundary between the crystal growth layer and the first conductivity type semiconductor is actually measured on the wafer on which the preceding crystal growth is performed. When the ratio (C2 / C1) of the two peak carrier concentrations is equal to or less than a predetermined value, another wafer in the production lot is
A method of manufacturing a semiconductor device, comprising: growing a crystal under the same conditions as the preceding wafer. 2. The method according to claim 1, wherein said peak carrier concentration ratio (C2 / C
When 1) is larger than a predetermined value, at least one of the conditions related to the crystal growth including the pretreatment is changed from the preceding crystal growth of the wafer according to the value,
2. The crystal growth of another wafer in the production lot.
The manufacturing method of the semiconductor device described in the above. 3. The semiconductor device is a solid-state imaging device, and the first conductivity type semiconductor is a first conductivity type semiconductor substrate of the solid-state imaging device or a first conductivity type semiconductor layer formed on the semiconductor substrate. The manufacturing method includes the following steps: ion implantation of a second conductivity type impurity into a first conductivity type semiconductor to form the second conductivity type semiconductor region functioning as an overflow barrier layer; 2. The method according to claim 1, further comprising the steps of: performing a crystal growth step including crystal growth of the first crystal, measurement of the two peak carrier concentrations, and crystal growth of another wafer, and forming a solid-state imaging device on the crystal growth layer. A method for manufacturing a semiconductor device. 4. The method according to claim 1, wherein the impurity concentration of the crystal growth layer is equal to the second impurity concentration.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity is lower than that of the conductivity type semiconductor region. 5. The method according to claim 1, wherein an impurity concentration of said crystal growth layer is equal to said second concentration.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the concentration is lower than the concentration of the second conductivity type impurity in the semiconductor region of the conductivity type. 6. The method of manufacturing a semiconductor device according to claim 3, wherein said crystal growth layer is grown to a predetermined thickness within a range where infrared light incident from an upper surface thereof is sufficiently absorbed. 7. The method of manufacturing a semiconductor device according to claim 3, wherein the value of the ratio (C2 / C1) of the peak carrier concentration used as a criterion for determining the quality of the crystal growth is 0.2. 8. A second conductivity type semiconductor region is formed in a part of the surface layer of the first conductivity type semiconductor, and a second conductivity type semiconductor region is formed on the second conductivity type semiconductor region and on the surrounding first conductivity type semiconductor. 1. A method for selecting a solid-state imaging device manufactured through a process including a step of crystal-growing a crystal growth layer made of a second conductivity type or an intrinsic semiconductor, wherein the crystal growth step is as follows: One of a plurality of wafers, which constitutes a manufacturing lot of semiconductor devices and is manufactured using the same manufacturing apparatus under the same conditions, grows one of the wafers in advance, and the peak carrier concentration (C) of the second conductivity type semiconductor region is increased.
1) and the peak carrier concentration (C2) of the abnormal concentration change formed in the crystal growth layer in the vicinity of the boundary between the crystal growth layer and the first conductivity type semiconductor, based on the wafer on which the preceding crystal growth was performed. A method for selecting a solid-state imaging device, wherein the ratio of the two peak carrier concentrations (C2 / C1) is used as one of selection criteria when selecting characteristics of the completed solid-state imaging device. 9. An impurity concentration of the crystal growth layer on which the solid-state imaging device is formed is lower than a concentration of a second conductivity type impurity of the second conductivity type semiconductor region functioning as an overflow barrier layer, and In selecting a solid-state imaging device in which the thickness of the growth layer is set to a predetermined thickness within a range where infrared light incident from the upper surface is sufficiently absorbed, the ratio of the peak carrier concentration (C2 / C1) is determined. 9. The method for selecting a solid-state imaging device according to claim 8, wherein the value 0.2 is used as one of the selection criteria for wafers predicted to have good color mixing characteristics.