JP2016143732A - Charge-coupled device, manufacturing method of charge-coupled device, and solid-state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge-coupled device capable of reducing dark-time output and improving transfer efficiency.SOLUTION: A charge-coupled device comprises: an n-channel region 101n that is formed on a p-type single crystal silicon substrate 101; a plurality of first layer transfer electrodes 104; a second layer transfer electrode 105; and a virtual electrode 106 formed from a p-type surface impurity region 200. An inner edge Eof a pair of second layer transfer electrodes 105A and 105B formed by separating the second layer transfer electrode 105 in an opening O that extends in a direction vertical to a charge transfer direction in which signal charge generated by photoelectric conversion is transferred, is positioned on a perpendicular T that is vertical to a surface of the p-type single crystal silicon substrate 101, passing an outer edge Eof the surface impurity region 200 formed between the pair of second layer transfer electrodes 105A and 105B, and film thickness of an oxide film 107S that is formed on a surface of the surface impurity region 200 is 50 nm or more and 250 nm or less.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a charge-coupled device (CCD), a method for manufacturing a charge-coupled device, and a solid-state imaging device including a virtual electrode.

  Conventionally, various structures have been proposed as a CCD comprising a CCD channel and a transfer electrode. As an example, in Patent Document 1, an opening is provided between the first layer transfer electrode or the second layer transfer electrode in order to increase the amount of light incident on the CCD channel, and the first layer transfer electrode or the second layer transfer is provided. A device in which a surface impurity region is formed by implanting impurities into an opening using an electrode as a mask is disclosed. According to Patent Document 1, the virtual barrier region and the virtual well region act as virtual electrodes, facilitate charge transfer in the CCD channel, reduce transfer loss, and improve photosensitivity.

JP 2005-39149 A

  However, in the CCD of Patent Document 1, in the etching process for forming the opening to the transfer electrode, the substrate surface is damaged, so that a crystal defect is likely to occur on the surface, and a generated recombination current is generated from the defect level. There is a problem that the output in the dark increases.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a charge coupled device capable of reducing dark output and improving transfer efficiency.

  In order to solve the above-described problems and achieve the object, a first charge coupled device of the present invention is formed on a semiconductor substrate having a channel region and a first insulating film on the surface of the semiconductor substrate. A plurality of first-layer transfer electrodes and a second-layer transfer electrode formed between the first-layer transfer electrodes and partially overlapping with each other on the first-layer transfer electrode via the second insulating film, and photoelectric conversion A transfer unit that transfers the charge generated in the unit, and an opening that is formed along the arrangement direction of the first layer transfer electrode and the second layer transfer electrode and separates the second layer transfer electrode into a pair of second layer transfer electrodes And a virtual electrode composed of a channel region exposed from the opening and a surface impurity region formed on the surface of the channel region. The inner edge of the pair of second layer transfer electrodes facing the opening is located on a vertical line perpendicular to the surface of the semiconductor substrate passing through the outer edge of the surface impurity region formed between the pair of second layer transfer electrodes. An oxide film having a thickness of 50 nm or more is provided on the surface of the region.

  The second charge-coupled device of the present invention includes a semiconductor substrate having a channel region, a plurality of first layer transfer electrodes formed on the surface of the semiconductor substrate via a first insulating film, and a first layer A transfer unit configured to transfer charges generated by the photoelectric conversion unit, the second layer transfer electrode being partially overlapped between the transfer electrodes on the first layer transfer electrode via the second insulating film. The first layer transfer electrode and the second layer transfer electrode formed along the arrangement direction of the first layer transfer electrode and the second layer transfer electrode are respectively connected to the pair of first layer transfer electrodes and the pair of second layer transfer electrodes. An opening portion to be separated, and a photodiode portion including a channel region exposed from the opening portion and a surface impurity region formed on the surface of the channel region are provided. The inner edge of the pair of first layer transfer electrodes and the pair of second layer transfer electrodes facing the opening is the outer edge of the surface impurity region formed between the pair of first layer transfer electrodes and between the pair of second layer transfer electrodes. And an oxide film having a thickness of 50 nm or more on the surface of the surface impurity region, which is located on a vertical line perpendicular to the surface of the semiconductor substrate.

  According to the present invention, a CCD capable of reducing dark output and improving transfer efficiency can be obtained.

1 is a perspective view showing a solid-state imaging device according to Embodiment 1. FIG. 2A and 2B are diagrams illustrating a configuration of a pixel of the solid-state imaging device according to the first embodiment, in which FIG. 3A is a top view, FIG. 3B is a cross-sectional view taken along the line AA in FIG. Cross section The principal part expanded sectional view which shows the overlap of the surface impurity region of the solid-state image sensor of Embodiment 1, and a transfer electrode FIGS. 5A to 5F are process cross-sectional views illustrating a method for manufacturing a pixel portion of the solid-state imaging device according to Embodiment 1. FIGS. (A) to (c) are comparative views showing the overlap between the surface impurity region and the transfer electrode for explaining the first embodiment. (A) And (b) is a comparison figure which shows the oxidation state of the surface of the surface impurity region for demonstrating Embodiment 1. FIG. (A) And (b) is a figure which shows the generation | occurrence | production mechanism of the TAT current for demonstrating Embodiment 1. FIG. It is a figure which shows the structure of the pixel of the solid-state imaging device of Embodiment 2, (a) is a top view, (b) is AA sectional drawing of (a), (c) is BB of (a). Cross section The principal part expanded sectional view which shows the overlap of the surface impurity region of the solid-state image sensor of Embodiment 2, and a transfer electrode FIGS. 5A to 5F are process cross-sectional views illustrating a method for manufacturing a pixel portion of a solid-state imaging device according to Embodiment 2. FIGS.

Embodiment 1 FIG.
Hereinafter, a charge coupled device, a method for manufacturing a charge coupled device, and a solid-state imaging device according to embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited by this embodiment, In the range which does not deviate from the summary, it can change suitably. In the drawings shown below, the scale of each layer or each member may be different from the actual for easy understanding, and the same applies to the drawings. In order to make the drawing easy to see, even a top view may be hatched, and even a cross-sectional view may not be hatched.

  A solid-state imaging device 100 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIG. 1 is a perspective view schematically showing a solid-state imaging device 100 according to Embodiment 1 of the present invention. The solid-state imaging device 100 according to the first embodiment includes a pixel array 110 as a charge transfer unit and a signal charge generated by the pixel array 110 on a p-type single crystal silicon substrate 101 having an n-channel region 101n formed on the surface. And a signal processing circuit 130 for reading out to the outside. A plurality of pixels 111 are arranged in a plurality of columns in the pixel array 110, and the pixels 111 of the pixel array 110 are sequentially selected by the signal processing circuit 130 and read out to the outside.

The pixel array 110 includes a vertical CCD 112 that transfers signal charges generated in the pixels 111 by the internal photoelectric effect in the vertical direction D _v of the pixel array 110, and further transfers the signal charges transferred by the vertical CCD 112 in the horizontal direction D _{H of the} pixel array 110. And a horizontal CCD 113 for transferring the signal charge to the output, and an output amplifier 114 for converting the transferred signal charge into a voltage. When a CCD is used, the output amplifier 114 is often a floating diffusion amplifier (FDA).

The above-described pixel 111 will be described with reference to FIGS. 2A is a top view of the solid-state imaging device according to the first embodiment, FIG. 2B is a cross-sectional view taken along line AA in FIG. 2A, and FIG. 2C is B in FIG. It is -B sectional drawing. In this embodiment mode, a p-type single crystal silicon substrate 101 is used as a semiconductor substrate. The pixel 111 includes a photoelectric conversion unit _RL that is formed in the p-type single crystal silicon substrate 101 and converts incident light into a signal charge, and a charge transfer electrode including the first layer transfer electrode 104 and the second layer transfer electrode 105. And a transfer unit _RT provided. The photoelectric conversion unit R _L includes an n-channel region 101 n made of an n-type impurity region formed in the p-type single crystal silicon substrate 101. The pixel 111 includes a pixel separation region 103R that prevents interference between adjacent pixels 111 along the horizontal direction _DH , an overflow gate (OFG) 103G that determines a saturation charge amount of the CCD channel, and a CCD channel An overflow drain (OFD) 103D that discharges surplus charges exceeding the saturation charge amount. Formed in parallel to each other along the vertical direction D _v between the pixels 111, the pixel isolation regions 103R and OFG103G and OFD103D, constitute inter-element portion R _Div. The pixel isolation region 103R is composed of a p-type impurity region. OFG 103G is formed of a p-type impurity region. The OFD 103D is composed of an n-type impurity region. In the present embodiment, the entire region surrounded by the inter-element portion R _Div is the photoelectric conversion portion R _L.

In this embodiment, it constitutes a vertical CCD112 arranged in a row pixels 111 in the vertical direction D _v. Here, as shown in FIG. 2C, for example, the vertical CCD 112 uses the first layer transfer electrode 104, the second layer transfer electrode 105A, the virtual electrode 106, and the second layer transfer electrode 105B as a period, and uses these electrodes as a cycle. Repeatedly arranged. A plurality of first layer transfer electrodes 104 formed on the first insulating film 107A on the p-type single crystal silicon substrate 101 and a part of the first layer transfer electrode 104 overlap with each other through the second insulating film 107B. As described above, the second layer transfer electrode 105 formed between the first layer transfer electrodes 104 and the p channel formed in the n channel region 101 n located in the opening O formed in the second layer transfer electrode 105. And a surface impurity region 200 made of a type impurity region.

The virtual electrode 106 is formed in an opening O provided between the pair of second charge transfer electrodes 105A and 105B. Therefore, in the virtual electrode 106, light is not absorbed by the second layer transfer electrode 105, but light is incident on the photoelectric conversion unit _RL , and sensitivity is improved. Incidentally, the extending direction of the first layer transfer electrodes 104 and the second layer transfer electrodes 105, the direction perpendicular to the vertical direction D _v, i.e. corresponding to a horizontal direction D _H.

The light detection principle of the pixel 111 will be described. When light emitted from a subject to be imaged by the solid-state imaging device 100 enters the pixel 111 in the pixel array 110, the p-type single crystal silicon substrate 101 has a number corresponding to the amount of incident light due to the internal photoelectric effect. Electron hole pairs are generated and transferred as signal charges. Here, a region of the p-type single crystal silicon substrate 101 where light is incident and electron-hole pairs are generated is defined as a photoelectric conversion unit R _L. For each pixel 111, the signal charge is transferred through the vertical CCD 112 and the horizontal CCD 113, and the transferred charge is converted into a voltage by the output amplifier 114 to obtain a captured image of the subject. The signal charges transferred here are often electrons.

  Charges that exceed the saturation charge amount determined by the CCD channel potential and the potential of the OFG 103G enter the OFD 103D via the OFG 103G, and are discharged to the outside through the OFD 103D.

The pixel 111 will be described in detail. As shown in FIG. 3, the inner edge E _i surrounding the opening O of the pair of second layer transfer electrodes 105A and 105B formed by separating the second layer transfer electrode 105 is a pair of second layer transfer electrodes. Positioned between about 0.15 μm outer side and about 0.15 μm inner side with respect to the perpendicular T perpendicular to the p-type single crystal silicon substrate 101 through the outer edge E _o of the surface impurity region 200 formed between 105A and 105B. I let you. On the surface of the surface impurity region 200, the thickness of the oxide film 107S is set to 50 nm or more and 250 nm or less. At this time, the phosphorus concentration of the pair of second layer transfer electrodes 105A and 105B was set to 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less.

  Although the manufacturing method will be described later, each of the first layer transfer electrode 104 and the second layer transfer electrode 105 is made of polycrystalline silicon containing phosphorus as an impurity, and the second layer is formed by sequentially oxidizing after film formation. An insulating film 107B and a third insulating film 107C are sequentially formed. Further, the dark output can be reduced by sufficiently oxidizing the surface of the surface impurity region 200 to reduce the generated recombination current. In addition, since the oxidation rate varies depending on the impurity concentration of polycrystalline silicon, the dark output can be reduced by optimizing the positional relationship between the surface impurity region 200 and the second layer transfer electrode 105 and reducing the TAT current. Furthermore, by optimizing the positional relationship between the surface impurity region 200 and the second layer transfer electrode 105 and reducing the potential unevenness at the peripheral edge of the surface impurity region 200, the transfer efficiency can be improved.

In the present embodiment, the positional relationship between the outer edge E _o of the surface impurity region 200 and the inner edge E _i surrounding the opening O of the pair of second layer transfer electrodes 105A and 105B is optimized to improve electrical characteristics. It is. The outer edge E _o of the surface impurity region 200 is formed by the horizontal and vertical diffusion of boron ions. The inner edge E _i surrounding the opening O of the pair of second layer transfer electrodes 105A and 105B is formed on the side walls of the pair of second layer transfer electrodes 105A and 105B by oxidation after boron ion implantation into the opening O. It depends on the thickness of the third insulating film 107C. The higher the impurity concentration of the polycrystalline silicon, the higher the oxidation rate of the second layer transfer electrode made of polycrystalline silicon, and the larger the thickness of the third insulating film 107C formed on the sidewall. As a result, the shift amount to the outside of the inner edge E _i of the second layer transfer electrodes 105A and 105B increases. Therefore, in the present embodiment, focusing on the impurity concentration of polycrystalline silicon, the oxide film 107S having a thickness capable of sufficiently absorbing crystal defects on the surface impurity region 200 is formed at the same time. The film thickness of the third insulating film 107C is adjusted by the impurity concentration of the pair of second layer transfer electrodes 105A and 105B.

  In the present embodiment, the surface of the p-type single crystal silicon substrate 101 is damaged by the dry etching for forming the opening O in the second layer transfer electrode 105, and many crystal defects are generated, and the trap level is generated. Is easily formed. Therefore, the virtual electrode 106 is likely to generate a generated recombination current.

  Therefore, in order to reduce crystal defects, a method of oxidizing the surface of the p-type single crystal silicon substrate 101 after forming the opening O and confining the crystal defects in the oxide film 107S on the surface is conceivable. The present inventors paid attention to increase and decrease in dark output and transfer efficiency, and found the following points from various experimental results. That is, when the phosphorus concentration of the second layer transfer electrode 105 is high and the amount of oxidation of the surface of the surface impurity region 200 is large, the amount of side wall oxidation of the second layer transfer electrode 105 becomes large, and the surface impurity region 200 and the second layer The transfer electrode 105 is greatly separated. As a result, potential unevenness occurs at the peripheral edge of the surface impurity region 200, and transfer efficiency is reduced. On the other hand, when the phosphorus concentration of the second layer transfer electrode 105 is low and the amount of oxidation on the surface of the surface impurity region 200 is small, the amount of side wall oxidation of the second layer transfer electrode 105 becomes small and The two-layer transfer electrode 105 overlaps greatly. Therefore, a TAT current is generated at a place where a strong electric field is applied, and the dark output is increased.

  Therefore, in the present embodiment, by determining the impurity concentration of the second layer transfer electrode according to the required thickness of the surface oxide film, the amount of oxidation of the surface of the surface impurity region 200 is made sufficient, and crystal defects are eliminated. Increases containment and generation recombination current. As a result, dark output can be reduced.

FIG. 3 shows the surface impurity region 200 and the pair of second layer transfer electrodes 105A and 105B at the time when the third insulating film 107C is formed by oxidizing the pair of second layer transfer electrodes 105A and 105B surrounding the opening O. It is sectional drawing which shows an overlap. Here, the amount of oxidation on the surface of the surface impurity region 200 is proportional to the amount of side wall oxidation of the pair of second layer transfer electrodes 105A and 105B, but the upper and side walls of the second layer transfer electrodes 105A and 105B are proliferated and oxidized. Oxidized more than the surface of the surface impurity region 200. In this embodiment, the thickness of oxide film 107S on the surface of surface impurity region 200 is not less than 50 nm and not more than 250 nm, and sufficiently absorbs crystal defects caused by etching damage when opening portion O is formed. Therefore, the surface has good crystallinity. Then, the inner edge E _i surrounding the opening O of the pair of second layer transfer electrodes 105A and 105B passes through the outer edge E _o of the surface impurity region 200 formed between the pair of second layer transfer electrodes 105A and 105B. It is located between about 0.15 μm outside and about 0.15 μm inside with respect to the perpendicular T perpendicular to the type single crystal silicon substrate 101. For this reason, electric charges are efficiently transferred without causing unevenness in potential at the peripheral edge portion of the surface impurity region 200, so that transfer efficiency does not decrease. Further, since there is no portion where a strong electric field is applied, no TAT current is generated and the dark output is not increased.

Next, a method for manufacturing the vertical CCD 112 or the pixel array 110 in the present embodiment will be described. Shown in FIGS. 4 (a) from (f), a sectional structure along the vertical direction D _v of the pixel array 110. 4A to 4F, the same reference numerals as those in FIGS. 2A to 2C indicate the same or equivalent portions. In this embodiment, the thickness of the third insulating film 107C is set to 50 nm or more and 250 nm or less on the surface of the surface impurity region 200 including the impurity regions. Prior to forming the second layer transfer electrode 105, the impurity concentration of the second layer transfer electrode 105 is determined according to the thickness of the oxide film 107S required on the surface impurity region 200. The inner edge E _i of the pair of second layer transfer electrodes 105A and 105B formed by separating the second layer transfer electrode 105 at the opening O is a surface formed between the pair of second layer transfer electrodes 105A and 105B. The third insulating film 107C is formed so as to be positioned on a perpendicular line T perpendicular to the surface of the p-type single crystal silicon substrate 101 _passing through the outer edge E _o of the impurity region 200.

  First, as shown in FIG. 4A, an impurity diffusion method or an ion is formed on the surface of the p-type single crystal silicon substrate 101 where the vertical CCD 112 and the horizontal CCD 113 are formed on the p-type single crystal silicon substrate 101. An impurity diffusion layer is formed using an implantation method, and an n-channel region 101n, a pixel isolation region 103R, an OFG 103G, and an OFD 103D are formed. 4A to 4F are not shown because they are cross sections that do not pass through the pixel isolation region 103R, OFG 103G, and OFD 103D. Next, an isolation oxide film (not shown) is formed at a specified position by a LOCOS (Local Oxidation of Silicon) isolation method or a trench isolation method. Next, a first insulating film 107A is formed on the p-type single crystal silicon substrate 101 by thermal oxidation.

Next, a phosphorus-doped polycrystalline silicon film is formed over the first insulating film 107A by a CVD (Chemical Vapor Deposition) method. Is then patterned by photolithography to form a first layer transfer electrode 104 at an interval in the vertical direction D _v, as shown in Figure 4 (b). Here, the phosphorus concentration of the phosphorus-doped polycrystalline silicon film constituting the first layer transfer electrode 104 is not particularly limited. However, considering from the viewpoint of the specific resistance of the wiring electrode, it is preferably set to 1.0 × 10 ¹⁹ cm ⁻³ or more, and the optimum value is preferably selected from this range. The first layer transfer electrode 104 extends along a direction perpendicular to the vertical direction D _v , that is, along the horizontal direction _DH . Next, the first layer transfer electrode 104 is oxidized by thermal oxidation to form a second insulating film 107B.

Next, a phosphorus-doped polycrystalline silicon film is formed over the second insulating film 107B by a CVD method. Is then patterned by photolithography, as shown in FIG. 4 (c), to form the second layer transfer electrodes 105 in an alternating arrangement and first layer transfer electrodes 104 in the vertical direction D _v. Here, the phosphorus-doped polycrystalline silicon film constituting the second layer transfer electrode 105 has a phosphorus concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less. select. Second layer transfer electrodes 105 perpendicular to the vertical direction D _v, i.e. extending along a horizontal direction D _H.

  Next, as shown in FIG. 4D, an opening O is formed in the second layer transfer electrode 105 by photolithography. Thus, the second layer transfer electrode 105 is divided into a pair of second layer transfer electrodes 105A and second layer transfer electrodes 105B, and a plurality of pairs of second layer transfer electrodes 105A and 105B are formed. Further, the surface impurity region 200 is formed in a part of the opening O by using an impurity diffusion method or an ion implantation method.

  Next, by performing a heat treatment at 900 ° C. to 1000 ° C. for about 30 minutes, the surface of the surface impurity region 200 exposed from the pair of second layer transfer electrodes 105A and 105B and the opening O is oxidized, and FIG. ), An oxide film 107S is formed. At this time, a silicon oxide film having a thickness of 50 nm to 250 nm is formed on the surface of the surface impurity region 200. On the other hand, a third insulating film 107C made of a silicon oxide film is formed on the upper and side walls of the pair of second layer transfer electrodes 105A and 105B by growth oxidation. The film thickness of the third insulating film 107C formed on the upper and side walls of the pair of second layer transfer electrodes 105A and 105B is determined by the phosphorus concentration of the second layer transfer electrode 105 and the heat treatment conditions.

In the present embodiment, on the surface of surface impurity region 200, oxide film 107S has a thickness of 50 nm to 250 nm. The inner edge E _i surrounding the opening O of the pair of second layer transfer electrodes 105A and 105B passes through the outer edge E _o of the surface impurity region 200 formed between the pair of second layer transfer electrodes 105A and 105B. It is located between about 0.15 μm outside and about 0.15 μm inside with respect to the perpendicular T perpendicular to the p-type single crystal silicon substrate 101. In the present embodiment, such a deviation range is assumed to be on the perpendicular line T.

  Next, after forming a fourth insulating film 108a made of TEOS (Tetra Ethyl OrthoSilicate) on the opening O, an aluminum layer is formed on this upper layer and patterned by photolithography to form a wiring layer 109.

  Finally, as shown in FIG. 4F, a protective film 108b made of TEOS is formed. In this way, the charge coupled device of the solid-state imaging device 100 in the present embodiment is completed.

The main points of the present embodiment will be described. In this embodiment mode, after the opening O is formed, the substrate surface is sufficiently oxidized, and the oxide film 107S having a thickness of 50 nm to 250 nm is formed. Generation of a coupling current can be prevented, and an increase in dark output can be suppressed. The oxide film 107S is formed in the same process as the third insulating film 107C, but the film thickness of the third insulating film 107C changes depending on the impurity concentration of the polycrystalline silicon constituting the second layer transfer electrode 105. The film thickness is often different from that of the oxide film 107S. In the present embodiment, since the phosphorous concentration of the polycrystalline silicon layer constituting the second layer transfer electrode 105 is set to 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less, the second layer The amount of side wall oxidation of the transfer electrode 105 can be appropriately controlled. Therefore, the outer edge E _o of the surface impurity region 200 and the inner edge E _{i of} the second layer transfer electrode 105 can be formed to coincide with each other. Therefore, there is no potential unevenness at the periphery of the surface impurity region 200, and there is no portion where a strong electric field is applied, so that efficient charge transfer and low dark output are realized.

  By the way, also in the above structure, when the phosphorus concentration of the phosphorus-doped polycrystalline silicon film constituting the second layer transfer electrode 105 is high, an attempt to sufficiently increase the oxidation amount of the surface of the surface impurity region 200 will result in the phosphorus-doped polycrystalline. Since the oxidation rate of the silicon film is high, the amount of side wall oxidation of the second layer transfer electrode 105 increases. At this time, as shown in FIG. 5A, the surface impurity region 200 and the pair of second layer transfer electrodes 105A and 105B are greatly separated. As a result, potential unevenness occurs at the peripheral edge of the surface impurity region 200, and transfer efficiency is reduced.

  Conversely, if the phosphorus concentration of the phosphorus-doped polycrystalline silicon film constituting the second layer transfer electrode is low and the oxidation amount of the surface of the surface impurity region 200 is small, the oxidation rate of the phosphorus-doped polycrystalline silicon film Therefore, the amount of side wall oxidation of the second layer transfer electrode 105 is small. At this time, as shown in FIG. 5B, the amount of side wall oxidation of the second layer transfer electrodes 105A and 105B becomes small, and the surface impurity region 200 and the second layer transfer electrode 105 overlap greatly. Therefore, a TAT current is generated at a place where a strong electric field is applied, and the dark output is increased.

  Further, if the surface oxidation amount of the surface impurity region 200 is insufficient, as shown in FIG. 6A, the number of crystal defects M that cannot be confined in the oxide film 107S increases. Therefore, a generated recombination current is generated from the defect level, and the dark output is increased.

In contrast, in the solid-state imaging device 100 according to the first embodiment, the phosphorus concentration of the second layer transfer electrode 105 made of polycrystalline silicon is 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ^{−. While} limiting to ³ or less, the surface oxidation amount of the surface impurity region 200 is limited to 50 nm or more and 250 nm or less. As a result, as shown in FIG. 5C, the side wall oxidation amount of the second layer transfer electrode 105 becomes moderate, and the positional relationship between the surface impurity region 200 and the second layer transfer electrode 105 can be optimized. For this reason, potential unevenness does not occur in the peripheral portion of the surface impurity region 200, and the transfer efficiency does not decrease. Further, since there is no portion where a strong electric field is applied, no TAT current is generated and the dark output is not increased. The specific resistance when the phosphorus concentration of the second layer transfer electrode 105 is 1.0 × 10 ¹⁹ cm ⁻³ is 5.44 mΩcm, and the specific resistance when the phosphorus concentration is 1.5 × 10 ²⁰ cm ⁻³ is 0.2. 55 mΩcm. Therefore, by setting the phosphorus concentration within the above range, it is possible to improve the transfer efficiency and reduce the dark output while maintaining a good function as the transfer electrode.

  Further, as shown in FIG. 6B, the amount of oxidation on the surface of the surface impurity region 200 is sufficient to confine the crystal defect M in the surface oxide film 107S. Therefore, almost no generation recombination current is generated from the defect level, and the dark output is reduced.

  As a result, the solid-state imaging device 100 according to the present embodiment sufficiently oxidizes the surface of the surface impurity region 200 to reduce the generated recombination current, and the surface impurity region 200 and the second layer transfer electrode. By optimizing the positional relationship 105 and reducing the TAT current, the dark output can be reduced. Furthermore, by optimizing the positional relationship between the surface impurity region 200 and the second layer transfer electrode 105 and reducing the unevenness of the potential at the peripheral edge of the surface impurity region 200, the transfer efficiency can be improved. For this reason, it is possible to provide the solid-state imaging device 100 having a high SN ratio (Signal to Noise Ratio) and capable of acquiring an image with a small blur.

Here, the mechanism of the dark output increase due to the generation of the TAT current will be described.
As shown in FIG. 7A, when a strong electric field is applied to the pn junction, electrons in the valence band B _v of the P-type semiconductor are caused to pass through the trap level in the band gap due to the tunnel phenomenon. It moves to the conduction band B _c of the n-type semiconductor. This is the TAT current. Alternatively, as shown in FIG. 7B, even when a strong electric field that is not as great as that in FIG. 7A is applied to the pn junction, electrons in the valence band B _v of the p-type semiconductor are not within the band gap. After moving to the trap level, it is thermally excited to a trap level having a higher potential and then moved to the conduction band B _c of the n-type semiconductor. This is the TAT current with thermal excitation. From the above, it can be seen that the TAT current increases when a strong electric field is applied to the pn junction, when the number of trap levels is large, and when the temperature of the solid-state imaging device 100 is high.

  7A and 7B, the p-type impurity region corresponds to the surface impurity region 200, and the n-type impurity region corresponds to the n-channel region 101n. That is, electrons accumulate in the n-channel region 101n not by photoelectric conversion but by the TAT current, thereby increasing dark output.

Actually, the phosphorus concentration of the transfer electrode made of polycrystalline silicon is limited to 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less, and the surface oxidation amount of the surface impurity region 200 is 50 nm. It is limited to 250 nm or less. The surface oxidation amount of the surface impurity region 200 is equal to the thickness of the oxide film on the surface of the surface impurity region 200. If the surface oxidation amount of the surface impurity region 200 is less than 50 nm, crystal defects formed by etching cannot be taken into the oxide film, and crystal defects remain on the surface of the surface impurity region 200. Produced recombination current is likely to occur. Further, when the phosphorus concentration is low, the surface impurity region 200 and the second layer transfer electrode 105 overlap with each other and the TAT current increases. On the other hand, when the surface oxidation amount of the surface impurity region 200 exceeds 250 nm, the control of the impurity concentration of the second layer transfer electrode has no effect and the side wall oxidation amount of the second layer transfer electrode increases. As a result, the surface impurity region 200 and the transfer electrode are greatly separated. For this reason, potential unevenness is formed between the surface impurity region 200 and the transfer electrode, and charges are not transferred smoothly.

Therefore, after limiting the surface oxidation amount of the surface impurity region 200 to 50 nm or more and 250 nm or less, the phosphorus concentration of the second layer transfer electrode 105 made of polycrystalline silicon is set to 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 ×. By determining from the range of 10 ²⁰ cm ⁻³ or less, the surface impurity region 200 is sufficiently oxidized to reduce the generated recombination current, and the positional relationship between the surface impurity region 200 and the second layer transfer electrode 105 is determined. Optimize to reduce TAT current. If the phosphorus concentration of the second layer transfer electrode 105 is less than 1.0 × 10 ¹⁹ cm ⁻³ , the conductivity of the second layer transfer electrode 105 itself cannot be sufficiently obtained. Further, when the oxidation amount is small, the surface impurity region 200 and the second layer transfer electrode 105 overlap with each other and the TAT current increases. On the other hand, if it exceeds 1.5 × 10 ²⁰ cm ⁻³ , the oxidation rate is high, and if the surface impurity region 200 is sufficiently oxidized to attempt to incorporate crystal defects, the surface impurity region 200 and the second layer transfer electrode 105 become large. Potential unevenness is formed apart, and transfer efficiency is lowered.

In the first embodiment, the inner edge E _i of the pair of second layer transfer electrodes 105A and 105B facing the opening O is the surface impurity region 200 formed between the pair of second layer transfer electrodes 105A and 105B. of passing through the outer edge E _o, was located on a line perpendicular T to the silicon substrate surface may not be just lines, electric field can be applied, to the extent that can not be uneven potential, the second layer transfer electrodes 105 The inner edge E _i and the outer edge E _o of the surface impurity region 200 may be separated from each other. Further, the inner edge E _{i of} the second layer transfer electrode 105 and the outer edge E _o of the surface impurity region 200 may overlap so that the TAT current is not generated.

In the first embodiment, the first and second layer transfer electrodes 104 and 105 are formed of polycrystalline silicon containing phosphorus. However, the impurity diffusion length and the diffusion temperature are not limited to phosphorus. Considering this, the heat treatment conditions may be controlled after selecting the type of impurities such as using arsenic or boron as the impurities of the first and second layer transfer electrodes 104 and 105. Furthermore, the inner edge E _i of the second layer transfer electrode 105 is formed between the pair of second layer transfer electrodes 105A and 105B by controlling the heat treatment conditions after selecting the type of impurities in the surface impurity region 200. The surface impurity region 200 can be configured to lie on a vertical line T passing through the outer edge E _o of the surface impurity region 200 and perpendicular to the surface of the p-type single crystal silicon substrate 1.

  In the first embodiment, the impurity concentration of the first layer transfer electrode can be made higher than the impurity concentration of the second layer transfer electrode, and the increase in resistance can be suppressed even when the transfer distance is long. . Needless to say, the first layer transfer electrode and the second layer transfer electrode may have the same impurity concentration.

Embodiment 2. FIG.
The solid-state imaging device according to the second embodiment will be described with reference to FIGS. The solid-state imaging device 100 according to the second embodiment is different in that an opening O ₁ is formed in the first layer transfer electrode 104 and an opening O ₀ is formed in the second layer transfer electrode 105, and the openings O ₁ , O ₀ are formed. The photodiode portion 120 is formed inside. The overall structure is the same as that of the solid-state imaging device 100 of the first embodiment shown in FIG. The pixel array according to the second embodiment is the same as the pixel array 110 according to the first embodiment.

The pixel 111 according to the second embodiment will be described with reference to FIGS. In the second embodiment, unlike the first embodiment, there is no virtual electrode 106 sandwiched between the pair of second layer transfer electrodes 105A and 105B. Instead, the first layer transfer electrode 104 and the second layer transfer electrode 105 have the openings O ₁ and O ₀ , respectively, and the p-type surface impurity region 200 is formed in the openings O ₁ and O _0. Thus, the embedded photodiode portion 120 is formed. In the present embodiment, the entire region surrounded by the inter-element portion R _Div forms a pn junction with the p-type single crystal silicon substrate 101 and the n-channel region 101n, and serves as a photoelectric conversion portion R _L.

Here, the principle of light detection of the pixel 111 in the second embodiment is the same as that in the first embodiment. In the first embodiment, the virtual electrode 106 serves as a transfer path for charges generated by the photoelectric conversion unit R _L , whereas in the second embodiment, the photodiode unit 120 does not serve as a charge transfer path. Different. However, by using the microlens to collect the incident light to the pixel 111 in the openings O ₁ and O ₀ , the photodiode unit 120 is directly transmitted without passing through the first and second layer transfer electrodes 104 and 105. The amount of light that is taken in and photoelectrically converted increases, and the sensitivity is improved. The photodiode portion 120 is different from the virtual electrode 106 of Embodiment 1 in that it does not become a charge transfer path.

  FIG. 9 shows the surface impurity region 200 and the first layer transfer electrode 104 when the surface of the surface impurity region 200, the first layer transfer electrode 104 and the second layer transfer electrode 105 are oxidized to form the third insulating film 107C. FIG. 6 is a cross-sectional view showing the overlap with the second layer transfer electrode 105. Here, although the amount of oxidation on the surface of the surface impurity region 200 is proportional to the amount of side wall oxidation of the transfer electrode, the side wall of the transfer electrode is proliferated and oxidized, so that it is oxidized more than the surface of the surface impurity region 200.

Next, a manufacturing process of the solid-state imaging device according to the second embodiment will be described with reference to FIGS. Shown in FIG. 10 (a) from (f), a sectional structure along the vertical direction D _v of the pixel array 110. 10A to 10F, the same reference numerals as those in FIGS. 8A to 8C denote the same or equivalent portions. In this embodiment, the thickness of the third insulating film 107 </ b> C is set to 50 nm to 250 nm on the surface of the surface impurity region 200. Prior to the formation of the first and second layer transfer electrodes 104 and 105, the impurity concentration of the first and second layer transfer electrodes 104 and 105 depends on the thickness of the oxide film required on the surface impurity region 200. Is determined. The inner edges of the pair of first and second layer transfer electrodes 104A, 104B, 105A, 105B formed by separating the first and second layer transfer electrodes 104, 105 at the openings O ₁ , O ₀ are defined as inner edges E _i1. , E _i0 . The outer edges of the surface impurity region 200 formed between the pair of first and second layer transfer electrodes 104A, 104B, 105A, and 105B are referred to as outer edges E _o1 and E _o0 . A third insulating film 107C is formed such that the inner edges E _i1 and E _i0 are positioned on the perpendicular lines T ₁ and T ₀ perpendicular to the surface of the p-type single crystal silicon substrate 101 _passing through the outer edges E _o1 and E _o0. It is characterized by doing.

  First, as shown in FIG. 10A, an impurity diffusion method or an ion is applied to the surface of the p-type single crystal silicon substrate 101 where the vertical CCD 112 and the horizontal CCD 113 are formed on the p-type single crystal silicon substrate 101. An impurity diffusion layer is formed using an implantation method, and an n-channel region 101n, a pixel isolation region 103R, an OFG 103G, and an OFD 103D are formed. 10A to 10F are cross sections that do not pass through the pixel isolation region 103R, OFG 103G, and OFD 103D, and are not shown. Next, an isolation oxide film (not shown) is formed at a specified position by LOCOS isolation or trench isolation. Next, a first insulating film 107A is formed on the p-type single crystal silicon substrate 101 by thermal oxidation.

Next, a phosphorus-doped polycrystalline silicon film is formed over the first insulating film 107A by a CVD method. Is then patterned by photolithography to form a first layer transfer electrode 104 at an interval in the vertical direction D _v, as shown in Figure 10 (b). Here, the phosphorus-doped polycrystalline silicon film has a phosphorus concentration of 1.0 × 10 ¹⁹ cm ^{−3 to} 1.5 × 10 ²⁰ cm ^−3, and an optimum value is selected from this range. The first layer transfer electrode 104 extends along a direction perpendicular to the vertical direction D _v , that is, along the horizontal direction _DH . Next, the first layer transfer electrode 104 is oxidized by thermal oxidation to form a second insulating film 107B.

Next, a phosphorus-doped polycrystalline silicon film is formed over the second insulating film 107B by a CVD method. Is then patterned by photolithography, as shown in FIG. 10 (c), to form the second layer transfer electrodes 105 in an alternating arrangement and first layer transfer electrodes 104 in the vertical direction D _v. Here, the phosphorus-doped polycrystalline silicon film has a phosphorus concentration of 1.0 × 10 ¹⁹ cm ^{−3 to} 1.5 × 10 ²⁰ cm ^−3, and an optimum value is selected from this range. Second layer transfer electrodes 105 perpendicular to the vertical direction D _v, i.e. extending along a horizontal direction D _H.

Next, as shown in FIG. 10D, openings O ₀ and O ₁ are formed in the second layer transfer electrode 105 and the first layer transfer electrode 104 by photolithography. As a result, the first layer transfer electrode 104 is divided into a pair of first layer transfer electrodes 104A and a first layer transfer electrode 104B, and a plurality of pairs of first layer transfer electrodes 104A and 104B are formed. The second layer transfer electrode 105 is divided into a pair of second layer transfer electrodes 105A and second layer transfer electrodes 105B, and a plurality of pairs of second layer transfer electrodes 105A and 105B are formed. Further, the surface impurity region 200 is formed in the openings O ₀ and O ₁ by using an impurity diffusion method or an ion implantation method.

Next, by performing a heat treatment at 900 ° C. to 1000 ° C. for about 30 minutes, the pair of first layer transfer electrodes 104A and 104B, the pair of second layer transfer electrodes 105A and 105B, and the openings O ₁ and O _{0 are} exposed. The surface of the surface impurity region 200 to be oxidized is oxidized to form an oxide film 107S as shown in FIG. At this time, a silicon oxide film having a thickness of 50 nm to 250 nm is formed on the surface of the surface impurity region 200. On the other hand, a third insulating film 107C made of a silicon oxide film is formed on the upper and side walls of the pair of first layer transfer electrodes 104A and 104B and the pair of second layer transfer electrodes 105A and 105B by growth oxidation. The thickness of the third insulating film 107C formed on the upper and side walls of the pair of first layer transfer electrodes 104A and 104B and the pair of second layer transfer electrodes 105A and 105B is the same as that of the first layer transfer electrode 104 and the second layer. It depends on the phosphorus concentration of the transfer electrode 105 and the heat treatment conditions.

In the present embodiment, the oxide film 107S has a thickness of 50 nm to 250 nm on the surface of the surface impurity region 200. The inner edges E _i0 and E _i1 surrounding the openings O ₀ and O ₁ of the pair of second layer transfer electrodes 105A and 105B are the pair of first layer transfer electrodes 104A and 104B and the pair of second layer transfer electrodes 105A. , 105B is located between about 0.15 μm outside and about 0.15 μm inside with respect to the perpendicular T ₀ perpendicular to the p-type single crystal silicon substrate through the outer edge E _0o of the surface impurity region 200. ing. In the present embodiment, such a deviation range is assumed to be on the vertical line T ₀ .

Next, after forming a fourth insulating film 108a made of TEOS on the openings O ₀ and O ₁ , an aluminum layer is formed on this upper layer and patterned by photolithography to form a wiring layer 109.

  Finally, as shown in FIG. 10F, a protective film 108b made of TEOS is formed. In this way, the charge coupled device of the solid-state imaging device 100 in the present embodiment is completed.

The main points of the present embodiment will be described. In this embodiment, after the openings O ₀ and O _{1 are} formed, the substrate surface is sufficiently oxidized to form the oxide film 107S having a thickness of 50 nm to 250 nm, so that crystal defects are confined in the oxide film 107S. Therefore, generation recombination current can be prevented and increase in dark output can be suppressed. The oxide film 107S is formed in the same process as the third insulating film 107C, but the film thickness of the third insulating film 107C changes depending on the impurity concentration of the polycrystalline silicon constituting the second layer transfer electrode 105. The film thickness is often different from that of the oxide film 107S. In the present embodiment, the phosphorus concentration of the polycrystalline silicon layers constituting the first and second layer transfer electrodes is 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less. The amount of side wall oxidation of the first-layer and second-layer transfer electrodes can be appropriately controlled. Accordingly, the outer edges E _o0 and E _o1 of the surface impurity region 200 can be formed so as to coincide with the inner edges E _i0 and E _{i1 of the} charge transfer electrode. Therefore, potential unevenness does not occur in the peripheral portion of the surface impurity region 200, and there is no portion where a strong electric field is applied, so that efficient charge transfer and low dark output are realized.

  Also in the second embodiment, as in the first embodiment, when the phosphorus concentration is high and the amount of oxidation on the surface of the surface impurity region 200 is large, the first layer is the same as shown in FIG. The amount of side wall oxidation of the transfer electrode 104 and the second layer transfer electrode 105 increases, and the surface impurity region 200 and the first layer transfer electrode 104 or the second layer transfer electrode 105 are greatly separated. Therefore, potential unevenness occurs between the surface impurity region 200 and the second layer transfer electrode 105, and transfer efficiency decreases.

  On the other hand, when the phosphorus concentration is low and the oxidation amount on the surface of the surface impurity region 200 is small, the side wall oxidation of the first layer transfer electrode 104 and the second layer transfer electrode 105 is the same as shown in FIG. The amount becomes small, and the surface impurity region 200 and the first layer transfer electrode 104 or the second layer transfer electrode 105 overlap. Therefore, a TAT current is generated at a place where a strong electric field is applied, and the dark output is increased.

  Further, if the surface oxidation amount of the surface impurity region 200 is insufficient, the number of crystal defects M that cannot be confined in the oxide film increases as shown in FIG. 6A. Therefore, a generated recombination current is generated from the defect level, and the dark output is increased.

On the other hand, in the solid-state imaging device 100 according to the second embodiment, the phosphorus concentration of the second layer transfer electrode 104 and the second layer transfer electrode 105 made of polycrystalline silicon is 1.0 × 10 ¹⁹ cm ⁻³ or more and 1 In addition to limiting to 5 × 10 ²⁰ cm ⁻³ or less, the amount of surface oxidation of the surface impurity region 200 is limited to 50 nm to 250 nm. As a result, as shown in FIG. 9, the amount of side wall oxidation of the first layer transfer electrode 104 and the second layer transfer electrode 105 becomes moderate, and the surface impurity region 200 and the first layer transfer electrode 104 or the second layer transfer electrode. The positional relationship of 105 can be optimized. Therefore, the unevenness of the potential does not occur in the peripheral portion of the surface impurity region 200, and the transfer efficiency does not decrease. Further, since there is no portion where a strong electric field is applied, no TAT current is generated and the dark output is not increased. The specific resistance when the phosphorus concentration of the second layer transfer electrode 105 is 1.0 × 10 ¹⁹ cm ⁻³ is 5.44 mΩcm, and the specific resistance when the phosphorus concentration is 1.5 × 10 ²⁰ cm ⁻³ is 0.2. 55 mΩcm. Therefore, by setting the phosphorus concentration within the above range, it is possible to improve the transfer efficiency and reduce the dark output while maintaining a good function as the transfer electrode.

  Further, as shown in FIG. 6B, the amount of oxidation on the surface of the surface impurity region 200 is sufficient to confine the crystal defects M in the oxide film 107S. Therefore, almost no generation recombination current is generated from the defect level, and the dark output is reduced.

  As a result, the solid-state imaging device 100 of the present embodiment sufficiently oxidizes the surface of the surface impurity region 200 to reduce the generated recombination current, and the surface impurity region 200 and the first layer transfer electrode 104 or the second layer. By optimizing the positional relationship of the transfer electrode 105 and reducing the TAT current, the dark output can be reduced. Further, by optimizing the positional relationship between the surface impurity region 200 and the first layer transfer electrode 104 or the second layer transfer electrode 105 to reduce potential unevenness at the peripheral portion of the surface impurity region 200, transfer efficiency can be improved. For this reason, it is possible to provide the solid-state imaging device 100 that has a high SN ratio and can acquire an image with a small blur.

  Here, the mechanism of increase in dark output due to generation of the TAT current in the second embodiment is the same as that in the first embodiment.

In the second embodiment, the inner edges E _i1 and E _{i0 of} the first layer transfer electrode 104 and the second layer transfer electrode 105 are _arranged between the pair of first layer transfer electrodes and the pair of second layer transfer electrodes. Located on perpendicular lines T ₁ and T ₀ perpendicular to the surface of the silicon substrate through the outer edges E _o1 and E _o0 of the surface impurity region 200 formed between them, but not necessarily on the line, and an electric field can be applied. The inner edges E _i1 , E _{i0 of} the first layer and second layer transfer electrodes 104, 105 and the outer edges E _o1 , E _{o0 of the} surface impurity region 200 are so _large that the peripheral edge of the surface impurity region 200 cannot be uneven. May be separated. Further, the inner edge E _{i of} the second layer transfer electrode 105 and the outer edge E _o of the surface impurity region 200 may overlap so that the TAT current is not generated.

In the second embodiment, the first and second layer transfer electrodes 104 and 105 are formed of polycrystalline silicon containing phosphorus. However, the impurity diffusion length and the diffusion temperature are not limited to phosphorus. Considering this, the heat treatment conditions may be controlled after selecting the type of impurities such as using arsenic or boron as the impurities of the first and second layer transfer electrodes 104 and 105. Further, by selecting the type of impurities in the surface impurity region 200 and controlling the heat treatment conditions, the inner edges E _i1 and E _{i0 of} the first layer transfer electrode 104 and the second layer transfer electrode 104 105 are first layer transfer electrodes and between the outer edge E of the pair of second layer transfer electrode surface impurity region 200 formed between _o1 of, E _o0 the passing, p-type single-crystal surface in line perpendicular T ₁ of the silicon substrate 101 , T ₀ .

  In the first and second embodiments, the example in which the signal processing circuit 130 is integrated on the p-type single crystal silicon substrate 101 on which the pixel array 110 is formed has been described. However, the present invention is not limited to this. The signal processing circuit 130 may be provided separately, or a chip having the signal processing circuit 130 mounted on a substrate on which the pixel array 110 is mounted may have a hybrid structure.

  Here, as the solid-state imaging device 100 of the first and second embodiments, a panchromatic detector that detects the entire light region and a color filter are arranged above to detect the light region by dividing it into several parts. There are two types of multiband detectors. In the present embodiment, both panchromatic detectors and multiband detectors are targeted.

Also, the solid-state imaging device 100 according to the first and second embodiments can be classified into two types depending on the signal charge readout method. One is an area sensor in which the vertical CCD 112 and the photoelectric conversion unit _RL are arranged in parallel, and is a detector used when the readout method is frame transfer or interline transfer. The other one is a detector that is used when the vertical CCD 112 includes a photoelectric conversion unit _RL , is a line sensor, and a readout method is TDI (Time Delay Integration). In the present embodiment, both area sensors and line sensors are targeted.

  In the first and second embodiments, the p-type single crystal silicon substrate 101 is used as the semiconductor substrate. However, the p-type single crystal silicon substrate 101 is not limited to the p-type, and may be an n-type, a silicon-based substrate such as SiC, and the like. Alternatively, a substrate on which an amorphous silicon-based thin film layer is formed, or a bonded substrate such as an SOI (Silicon on Insulator) substrate may be used.

  The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

100 solid-state imaging device, 101 p-type single crystal silicon substrate, 101 n-n channel region, 103R pixel isolation region, 103G OFG, 103D OFD, 104 first layer transfer electrode, 105 second layer transfer electrode, 106 virtual electrode, 107A first , 107B second insulating film, 107C third insulating film, 107S oxide film, 108a fourth insulating film, 108b protective film, 109 wiring layer, 110 pixel array, 111 pixel, _RL photoelectric conversion unit, R _Div inter-element section, 112 vertical CCD, 113 horizontal CCD, 114 output amplifier, 120 photodiode section, 130 signal processing circuit, D _v vertical direction, _DH horizontal direction, O, O ₀ , O ₁ opening, M crystal _{defect, E i, E i0, E} i1 inner _{edge, E o, E o0, E} o1 outer edge, T, T _0, T ₁ perpendicular, R _T transfer unit, 200 a surface impurity regions.

Claims (12)

A semiconductor substrate with a channel region;
A plurality of first layer transfer electrodes formed on the surface of the semiconductor substrate via a first insulating film, and a second insulating film on the first layer transfer electrode from between the first layer transfer electrodes. A transfer unit that partially overlaps and is formed of the formed second layer transfer electrode, and transfers the charge generated by the photoelectric conversion unit;
An opening formed along an arrangement direction of the first layer transfer electrode and the second layer transfer electrode and separating the second layer transfer electrode into a pair of second layer transfer electrodes;
A charge coupled device comprising: the channel region exposed from the opening; and a virtual electrode formed of a surface impurity region formed on a surface of the channel region,
Inner edges of the pair of second layer transfer electrodes facing the opening,
Located on a perpendicular line passing through the outer edge of the surface impurity region formed between the pair of second layer transfer electrodes and perpendicular to the surface of the semiconductor substrate;
A charge-coupled device comprising an oxide film having a thickness of 50 nm or more on a surface of the surface impurity region. The semiconductor substrate is a silicon substrate;
The second layer transfer electrode is
2. The charge-coupled device according to claim 1, wherein the charge-coupled device is a phosphorus-doped polycrystalline silicon layer having a phosphorus concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less.   The charge coupled device according to claim 1, wherein the oxide film has a thickness of 250 nm or less. A pixel array formed by arranging a plurality of the charge coupled devices according to any one of claims 1 to 3 in a vertical direction and a horizontal direction;
A solid-state imaging device comprising: a signal processing circuit that processes an output of the pixel array. A semiconductor substrate with a channel region;
A plurality of first layer transfer electrodes formed on the surface of the semiconductor substrate via a first insulating film, and a second insulating film on the first layer transfer electrode from between the first layer transfer electrodes. A transfer unit that partially overlaps and is formed of the formed second layer transfer electrode, and transfers charges generated by the photoelectric conversion unit;
The first layer transfer electrode and the second layer transfer electrode formed along the arrangement direction of the first layer transfer electrode and the second layer transfer electrode are respectively connected to a pair of first layer transfer electrode and a pair of second layer transfer. An opening that separates into electrodes;
A charge coupled device comprising: the channel region exposed from the opening; and a photodiode portion comprising a surface impurity region formed on a surface of the channel region,
Inner edges of the pair of first layer transfer electrodes and the pair of second layer transfer electrodes facing the opening,
Located on a perpendicular perpendicular to the surface of the semiconductor substrate passing through the outer edge of the surface impurity region formed between the pair of first layer transfer electrodes and between the pair of second layer transfer electrodes,
A charge-coupled device comprising an oxide film having a thickness of 50 nm or more on a surface of the surface impurity region. The semiconductor substrate is a silicon substrate;
The first layer transfer electrode and the second layer transfer electrode are:
6. The charge-coupled device according to claim 5, wherein the charge-coupled device is a polycrystalline silicon layer having a phosphorus concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less.   The charge coupled device according to claim 5, wherein the oxide film has a thickness of 250 nm or less. A pixel array formed by arranging a plurality of the charge coupled devices according to claim 5 in the vertical direction and the horizontal direction,
A solid-state imaging device comprising: a signal processing circuit that processes an output of the pixel array. A channel forming step of forming a second conductivity type impurity region on the surface of the first conductivity type semiconductor substrate;
Forming a first transfer film comprising a polycrystalline silicon layer containing impurities after forming a first insulating film on the surface of the semiconductor substrate;
Forming a second layer transfer electrode made of a polycrystalline silicon layer containing impurities, partially overlapping between the first layer transfer electrodes via the second insulating film on the first layer transfer electrode;
Etching a part of the second layer transfer electrode to form an opening and forming a pair of second layer transfer electrodes;
Forming a surface impurity region on the surface of the semiconductor substrate exposed from the opening;
Performing a thermal oxidation, and forming an oxide film on the surface of the surface impurity region and the surface of the second layer transfer electrode,
Forming the second layer transfer electrode on the surface of the surface impurity region,
Determining the impurity concentration of the second layer transfer electrode according to the thickness of the oxide film to be formed on the surface of the surface impurity region,
Inner edges of a pair of second layer transfer electrodes formed by separating at the opening,
Located on a perpendicular line passing through the outer edge of the surface impurity region formed between the pair of second layer transfer electrodes and perpendicular to the surface of the semiconductor substrate;
The method of manufacturing a charge coupled device, wherein the oxide film has a thickness of 50 nm or more on the surface of the surface impurity region. The semiconductor substrate is a silicon substrate;
The second layer transfer electrode is
The method for manufacturing a charge-coupled device according to claim 9, wherein the polycrystalline silicon layer has a phosphorus concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less.   11. The method of manufacturing a charge coupled device according to claim 9, wherein the oxide film has a thickness of 250 nm or less. The first layer transfer electrode is
A polycrystalline silicon layer having a phosphorus concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ²⁰ cm ⁻³ or less,
The step of forming the opening includes
Etching the first layer transfer electrode and the second layer transfer electrode to form an opening;
The step of forming the oxide film includes
12. The method according to claim 9, further comprising a step of performing thermal oxidation to form an oxide film on the surface of the impurity region exposed to the opening, the first layer transfer electrode, and the second layer transfer electrode. The manufacturing method of the charge coupled device of any one of Claims 1.

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