JP2009010189A - Solid-state imaging apparatus and manufacturing method thereof, imaging apparatus, and semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus, a manufacturing method thereof and an imaging apparatus, wherein a transfer electrode having no warp-up in both end parts, hence no formation of a potential dip, and having no decline in transfer efficiency can be formed with the same resistance and same film thickness as a conventional one. <P>SOLUTION: A first transfer electrode 25 and a second transfer electrode 26 are so formed as to have a three-layer structure consisting of a non-doped polysilicon layer 31 doped with no impurities, an oxide film layer 32, and a polysilicon layer 33 doped with impurities, which are stacked in this order. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device including a high-temperature manufacturing process, a manufacturing method thereof, an imaging device, a semiconductor device, and a manufacturing method thereof.

FIG. 10 is a diagram showing transfer electrodes of a horizontal transfer register of a conventional CCD solid-state imaging device.
As shown in FIG. 10, a gate oxide film 102 is formed on a semiconductor substrate 101 on which a transfer channel is formed, and a transfer electrode 103 and an interlayer insulating film 104 covering the transfer electrode 103 are formed on the gate oxide film 102. Is formed. The transfer electrode 103 is made of polysilicon doped with an impurity such as phosphorus. The interlayer insulating film 104 is formed by oxidizing the surface of a polysilicon film for forming the transfer electrode 103.

  In a CCD solid-state imaging device having a polysilicon transfer electrode doped with impurities, the film thickness of the gate oxide film 102 under both end portions 103A of the transfer electrode 103 becomes thicker than other portions due to the oxidation process, and both end portions 103A. There is a problem that the film is formed to warp upward. For this reason, in the buried channel immediately below both end portions 103A of the transfer electrode 103, the potential becomes deeper than other portions, so-called potential dip is formed, and signal electrons are likely to accumulate in those portions, resulting in a decrease in transfer efficiency. There was a problem such as.

FIG. 11 is a diagram showing the relationship between the oxidation treatment time of phosphorus-doped silicon and the thickness of the oxide layer when the impurity concentration of phosphorus and the treatment temperature are changed (see Non-Patent Document 1).
As shown in FIG. 11, in the polysilicon doped with phosphorus as an impurity, the oxidation rate depends on the concentration of phosphorus. For this reason, a solid-state imaging device including a transfer electrode having a two-layer structure in which a non-doped polysilicon layer not doped with phosphorus and a polysilicon layer doped with phosphorus are stacked in this order has been proposed (see Patent Document 1). ).
JP 2003-324189 A S. M.M. Sze VLSI Technology Page 146

However, in the conventional solid-state imaging device of Patent Document 1, phosphorus diffuses into the first non-doped polysilicon layer during the deposition of the second-layer phosphorus-doped polysilicon, so that both ends of the transfer electrode There is a problem that it is impossible to prevent the phenomenon that the thickness of the gate oxide film under the portion increases.
Although it is conceivable to increase the thickness of the first non-doped polysilicon layer, in this case, if the total thickness of the first layer and the second layer is the same as the conventional one, the resistance of the transfer electrode is increased. When trying to obtain the same resistance as the above, there is a problem that the entire thickness of the first layer and the second layer is increased.

The present invention has been made in view of such circumstances, and its purpose is to increase the thickness of the gate oxide film below both ends of the transfer electrode, and to warp the both ends of the transfer electrode upward, Overcoming the conventional disadvantage of forming a potential dip and lowering the transfer efficiency, eliminating the warping of both ends of the transfer electrode, thereby preventing the formation of a potential dip and reducing the transfer efficiency as before It is in providing the solid-state imaging device which can be formed with the resistance and film thickness, its manufacturing method, and an imaging device.
In addition, the present invention has a drawback in that the channel length is substantially shortened by increasing the thickness of the gate oxide film below both ends of the gate electrode and warping both ends of the gate electrode upward. And a solid-state imaging device capable of forming a gate electrode having a channel length as designed, a semiconductor device, and a semiconductor device, and a manufacturing method thereof.

In order to achieve the above object, a solid-state imaging device of the present invention includes a plurality of sensor units that perform photoelectric conversion, a plurality of vertical transfer registers that read and transfer signal charges accumulated in the sensor units in the vertical direction, and the plurality A horizontal transfer register that horizontally transfers the signal charge transferred in the vertical direction by the vertical transfer register, the vertical transfer register has a plurality of vertical transfer electrodes,
The horizontal transfer register has a plurality of horizontal transfer electrodes, and at least one of the vertical transfer electrode and the horizontal transfer electrode is a non-doped polysilicon layer not doped with impurities, an oxide film layer, and polysilicon doped with impurities. It has a three-layer structure in which layers are laminated in that order.
In addition, the method for manufacturing a solid-state imaging device according to the present invention includes a plurality of sensor units that perform photoelectric conversion, a plurality of vertical transfer channels for reading and transferring signal charges accumulated in the sensor units in the vertical direction, and the plurality of the plurality of sensor units. Forming a horizontal transfer channel for transferring signal charges transferred through the vertical transfer channel in a horizontal direction on a semiconductor substrate, forming a plurality of vertical transfer electrodes on the vertical transfer channel, and performing the horizontal transfer A transfer electrode forming step of forming a plurality of horizontal transfer electrodes on the channel, the transfer electrode forming step comprising: a non-doped polysilicon layer not doped with impurities; an oxide film layer; and a polysilicon layer doped with impurities. The plurality of vertical transfer electrodes and the plurality of horizontal transfer electrodes are formed by laminating in that order.
The imaging device of the present invention includes an imaging unit using a solid-state imaging device, a control unit that controls the imaging unit, and an operation unit that operates the imaging unit, and the solid-state imaging device performs photoelectric conversion. A plurality of sensor units to perform, a plurality of vertical transfer registers for reading out and transferring the signal charges accumulated in the sensor units in the vertical direction, and a signal charge transferred in the vertical direction by the plurality of vertical transfer registers in the horizontal direction The vertical transfer register has a plurality of vertical transfer electrodes, the horizontal transfer register has a plurality of horizontal transfer electrodes, and at least one of the vertical transfer electrode and the horizontal transfer electrode Has a three-layer structure in which a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order. To.

The solid-state imaging device of the present invention includes a plurality of sensor units that perform photoelectric conversion, a transfer transistor that transfers signal charges photoelectrically converted by the sensor units to a signal charge detection unit, and a potential of the signal charge detection unit. A reset transistor that periodically resets, and an amplifying transistor that detects a potential fluctuation of the signal charge detection unit and converts it into an electric signal, wherein the transfer transistor, the reset transistor, and the amplifying transistor are provided on a semiconductor substrate The gate electrode of the MOS transistor has three layers in which a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are stacked in that order. It has a structure.
The method of manufacturing a solid-state imaging device according to the present invention includes a step of forming a plurality of sensor units that perform photoelectric conversion on a semiconductor substrate, and a transfer transistor that transfers signal charges photoelectrically converted by the sensor units to a signal charge detection unit. And a transistor forming step of forming, on a semiconductor substrate, a reset transistor that periodically resets the potential of the signal charge detection unit, and an amplification transistor that detects a potential variation of the signal charge detection unit and converts it into an electric signal. The transfer transistor, the reset transistor, and the amplification transistor are each composed of a MOS transistor, and the transistor forming step includes a gate electrode forming step of forming a gate electrode of the MOS transistor on a semiconductor substrate, and the gate electrode The formation process is non-doped polysilicon that is not doped with impurities. When, and forming an oxide film layer, and a polysilicon layer doped with impurities are laminated in their order the transfer transistor, the gate electrode of the reset transistor and the amplifier transistor.

The semiconductor device of the present invention includes a semiconductor substrate and a MOS transistor provided on the semiconductor substrate, and the MOS transistor includes a gate electrode provided on the semiconductor substrate. It has a three-layer structure in which a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order.
The method for manufacturing a semiconductor device of the present invention includes a step of forming a source electrode and a drain electrode of a MOS transistor on a semiconductor substrate, and a gate electrode forming step of forming a gate electrode of the MOS transistor on the semiconductor substrate. And the step of forming the gate electrode is characterized in that the gate electrode is formed by laminating a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities in that order. .

According to the solid-state imaging device, the manufacturing method thereof, and the imaging device of the present invention, the vertical transfer electrode and the horizontal transfer electrode include a non-doped polysilicon layer that is not doped with impurities, an oxide film layer, and a polysilicon layer that is doped with impurities. It has a three-layer structure laminated in this order.
For this reason, an increase in the thickness of the oxide film under both ends of the transfer electrode is suppressed by the first non-doped polysilicon layer. During the formation of the third polysilicon layer, the diffusion of impurities from the polysilicon layer doped with the third impurity is blocked by the second oxide film, and the first non-doped polysilicon layer and The polysilicon layer doped with the third impurity is separated. Therefore, oxidation at both ends of the transfer electrode is suppressed, and warping of both ends of the transfer electrode as in the conventional case is suppressed, so that a potential dip is formed as in the conventional case, thereby preventing transfer efficiency from being lowered. .
Also, the second oxide film can be made thin enough to block the diffusion of impurities from the polysilicon layer doped with the third impurity. Since the diffusion of impurities from the polysilicon layer doped with the third impurity is blocked by the second oxide film, the first non-doped polysilicon layer can be made as thin as necessary. Therefore, the entire film thickness of the transfer electrode can be reduced to the same level as the conventional one.

In addition, according to the solid-state imaging device and the manufacturing method thereof of the present invention, the gate electrode of the MOS transistor includes a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities. It has a three-layer structure laminated in order.
For this reason, for the same reason as above, both ends of the gate electrode are warped when processed by a high-temperature oxidation process, preventing the conventional problem that the short channel effect occurs, and there is no warping of both ends as designed. A gate electrode having a channel length of can be formed.

According to the semiconductor device and the manufacturing method thereof of the present invention, the gate electrode of the MOS transistor has a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities stacked in that order. It has a three-layer structure.
Therefore, for the same reason as above, when processed by a high-temperature oxidation process, both ends of the gate electrode are warped and the conventional problem of short channel effect is prevented, and both ends are not warped. A gate electrode having a channel length of can be formed.

Hereinafter, a solid-state imaging device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment.
As shown in FIG. 1, the solid-state imaging device according to the first embodiment is a CCD solid-state imaging device, and includes an imaging region 1 and a peripheral region 2. The imaging area 1 is an area for taking an image. The peripheral area 2 includes a peripheral circuit for driving the imaging area 1.
The imaging area 1 includes a plurality of photosensors 11 arranged in a matrix. The photosensor 11 performs photoelectric conversion according to the amount of incident light. In the horizontal direction of the photosensor 11, there is provided a vertical transfer register 12 that reads out the signal charge accumulated by the photosensor 11 and transfers it in the vertical direction. A channel stop region 13 for element isolation is provided adjacent to the vertical transfer register 12 in the horizontal direction. On one end side of the vertical transfer register 12, a horizontal transfer register 14 for transferring the signal charges transferred by the vertical transfer register 12 in the horizontal direction is provided. One end of the horizontal transfer register 14 is provided with an output unit 15 that converts the signal charge transferred by the horizontal transfer register 14 into a voltage and outputs the voltage.

2 is a diagram illustrating a configuration of a vertical transfer register of the solid-state imaging device illustrated in FIG. 1, FIG. 21A is a plan view, and FIG. 2B is a cross-sectional view taken along line AA ′ of FIG. FIG. 2 and FIG. 2C are explanatory diagrams of the transfer electrode portion of FIG.
As shown in FIG. 2B, a vertical transfer channel 22 extending in the vertical direction is provided on the upper layer portion of the semiconductor substrate 21 adjacent to the photosensor 11 in the horizontal direction, and a gate is formed on the vertical transfer channel 22. An oxide film 23 is formed.

A first transfer electrode 25 and a second transfer electrode 26 are formed on the gate oxide film 23. As shown in FIGS. 2A and 2C, the first transfer electrode 25 is floating island-like (isolated) on the vertical transfer channel 22 adjacent in the horizontal direction of the central portion 11A in the vertical direction of the photosensor 11. And away).
The second transfer electrode 26 is provided on the vertical transfer channel 22 adjacent in the horizontal direction of the central portion 11B between the photosensors 11 in the vertical direction and connected to the second transfer electrode 26 in another column by a connecting portion 26D. It has been. The second transfer electrode 26 is connected in the horizontal direction for each row by the connecting portion 26D, and also serves as a second wiring (which connects the second transfer electrode 26 in the horizontal direction).

  As shown in FIGS. 2A to 2C, the first transfer electrode 25 is formed by a first wiring 27 formed on the first transfer electrode 25 and the second transfer electrode 26. Each is connected in the horizontal direction. The first wiring 27 includes a horizontal portion 27A extending in the horizontal direction above the second transfer electrode 26, and a branch leaf portion 27B extending from the horizontal portion 27A and extending vertically on the transfer channel 102. The branch and leaf portion 27B is connected to the first transfer electrode 25 through a contact portion 27C below the branch and leaf portion 27B.

  As shown in FIG. 2B, the first transfer electrode 25 and the second transfer electrode 26 are composed of a non-doped polysilicon layer 31 that is not doped with impurities, an oxide film layer 32, and a polysilicon layer 33 that is doped with impurities. And a three-layer structure in which these are stacked in that order.

  The first non-doped polysilicon layer 31 suppresses an increase in the thickness of the oxide film under the end of the transfer electrode, which is a conventional drawback. During the formation of the third polysilicon layer 33, the diffusion of impurities from the third polysilicon layer 33 is blocked by the second oxide film 32, and the first non-doped polysilicon layer 31 and The third polysilicon layer 33 is separated. Therefore, the oxidation at the end of the transfer electrode is suppressed, and the warping of the end of the transfer electrode as in the conventional case is suppressed, so that the potential dip is formed as in the conventional case, and the transfer efficiency is prevented from being lowered. .

  The second oxide film 32 can be made thin enough to block the diffusion of impurities from the polysilicon layer 33 doped with the third impurity. The thickness of the oxide film layer 32 is preferably 2 nm or more and 10 nm or less. If the thickness of the oxide film layer 32 is smaller than 2 nm, the diffusion of impurities from the third polysilicon layer 33 is not completely blocked. On the other hand, if the thickness of the oxide film layer 32 is larger than 10 nm, the electrode capability of the transfer electrode (bias application capability to the Si substrate 21) is affected. Since the thickness of the oxide film layer 32 is so thin, it is considered that this hardly affects the electrode capability.

  Since the diffusion of impurities from the polysilicon layer doped with the third impurity is surely blocked by the second oxide film 32, the first non-doped polysilicon layer 31 can be made as thin as necessary. it can. If the oxide film is generated by thermal oxidation (pyro oxidation), the thickness of the first non-doped polysilicon layer 31 is about 5 to 10 times the amount to be oxidized, and is preferably 20 nm to 50 nm. Further, the film thickness of the third polysilicon layer 33 is preferably 150 nm or more and 250 nm or less in consideration of the same resistance as the conventional one.

  The total film thickness of the non-doped polysilicon layer 31, the oxide film layer 32, and the polysilicon layer 33 is preferably 200 nm or more and 300 nm or less. When the total film thickness is 300 nm or more, it is not preferable in that the first transfer electrode 25, the second transfer electrode 26, and the first wiring 27 themselves largely block light incident on the photosensor 11. Therefore, the entire thickness of the transfer electrode can be reduced to the same level as the conventional one.

FIG. 3 is a diagram showing the configuration of the horizontal transfer register of the solid-state imaging device shown in FIG. FIG. 4 is a diagram showing a cross-sectional structure of the horizontal transfer register shown in FIG.
As shown in FIG. 3, the horizontal transfer register 14 includes a horizontal transfer channel 40 formed in the semiconductor substrate 21 extending in the horizontal direction and a plurality of gate oxide films 23 formed on the semiconductor substrate 21. A horizontal transfer electrode 41. The horizontal transfer electrode 41 is connected to and driven by two bus lines 42 and 43.

As shown in FIG. 4, the horizontal transfer electrode 41 has a three-layer structure in which a non-doped polysilicon layer 31 that is not doped with impurities, an oxide film layer 32, and a polysilicon layer 33 that is doped with impurities are laminated in that order. .
The horizontal transfer electrode 41 of the horizontal transfer register 14 and the vertical transfer electrode (the first transfer electrode 25 and the second transfer electrode 26) of the vertical transfer register 12 are formed simultaneously from the viewpoint of simplification of manufacturing.

  For this reason, the horizontal transfer electrode 41 of the horizontal transfer register 14 is suppressed from oxidation at both ends of the transfer electrode for the same reason as the vertical transfer electrode of the vertical transfer register 12 described above, and both ends of the transfer electrode as in the conventional case. Therefore, the potential dip is formed as in the conventional case, and the transfer efficiency is prevented from being lowered.

FIG. 5 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the first embodiment.
Since the horizontal transfer electrode 41 of the horizontal transfer register 14 and the vertical transfer electrode of the vertical transfer register 12 are simultaneously formed by the same method, a method of forming the horizontal transfer electrode 41 of the horizontal transfer register 14 will be described here.
As shown in FIG. 5A, after forming a gate oxide film (about 40 nm) 23 on the Si substrate 21, a non-doped polysilicon film 31A is deposited on the gate oxide film 23 by LPCVD. The film thickness is about 50 nm.
Next, as shown in FIG. 5B, an oxide film 32A is deposited on the non-doped polysilicon layer 31A by LPCVD. The film thickness is about 5 nm. The oxide film may be generated by thermal oxidation (pyro oxidation).
Next, as shown in FIG. 5C, a polysilicon film 33A doped with phosphorus is deposited on the oxide film 32A by LPCVD. The film thickness is about 250 nm.
Next, as shown in FIG. 5D, a photoresist electrode pattern 34 is formed by photolithography.
Next, as shown in FIG. 5E, unnecessary portions are removed by dry etching, and a horizontal transfer electrode 41 is formed.

6 is a diagram showing a configuration of the output unit shown in FIG. 1, FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view.
As shown in FIG. 6A, the output unit 15 converts the signal charge transferred by the horizontal transfer register 14 into a voltage and outputs it, and outputs four MOS transistors 51, 52, 53 and 54. It has a source follower circuit.
As shown in FIG. 6B, the MOS transistors 51, 52, 53, and 54 are formed on the semiconductor substrate 21 through the gate oxide film 23 and the source 62 and the drain 63 formed on the semiconductor substrate 21. The gate electrode 61 is provided.

The gate electrode 61 has a three-layer structure in which a non-doped polysilicon layer 31 that is not doped with impurities, an oxide film layer 32, and a polysilicon layer 33 that is doped with impurities are laminated in that order. The gate electrodes 61 of the MOS transistors 51, 52, 53, and 54 are formed from the horizontal transfer electrode 41 of the horizontal transfer register 14 and the vertical transfer electrode (the first transfer electrode 25 and the first transfer electrode 25) of the horizontal transfer register 14 from the viewpoint of simplification of manufacturing. 2 transfer electrodes 26).
Therefore, the gate electrode 61 has a thick oxide film at both end portions thereof, can prevent the conventional defect in which the short channel effect occurs, and can form the gate electrode 61 having the designed channel length.

  In the first embodiment, a so-called single-layer transfer electrode structure is illustrated as a vertical transfer electrode having a three-layer structure of non-doped polysilicon layer 31 / oxide film layer 32 / impurity doped polysilicon layer 33. However, the vertical transfer electrode having a three-layer structure is not limited to this, and is also applicable to a conventional vertical CCD structure in which two-layer or three-layer polysilicon vertical transfer electrodes are formed by the three-layer structure. be able to.

(Embodiment 2)
FIG. 7 is a diagram illustrating a schematic configuration of the solid-state imaging device according to the second embodiment.
As shown in FIG. 7, the solid-state imaging device of the second embodiment is a CMOS type solid-state imaging device, and includes a pixel array unit 71, a vertical scanning circuit 72, a load MOS transistor circuit 74, a column signal processing unit 75, a horizontal selection. A transistor circuit 76, a horizontal scanning circuit 78, and an output processing unit 79 are provided.
The pixel array unit 71 forms an imaging region by a plurality of pixels 70 arranged in a matrix. The vertical scanning circuit 72 scans each pixel 70 of the pixel array unit 71 in the vertical direction and controls a pixel signal reading operation. The load MOS transistor circuit 74 controls the vertical signal line 73 led from each pixel column of the pixel array unit 71.
The column signal processing unit 75 receives the signal of each pixel obtained through the vertical signal line 73 one row at a time, performs predetermined signal processing for each column (column), and temporarily holds the signal. The column signal processing unit 75 includes, for example, one or both of a CDS (Correlated Double Sampling) circuit and an ADC (Analog to Digital Converter) circuit for each column (row). The CDS circuit performs noise removal on the pixel signal by correlated double sampling processing. The ADC circuit converts an analog pixel signal into a digital signal.
The horizontal selection transistor circuit 76 outputs the pixel signal of the column signal processing unit 75 to the horizontal signal line 77. The horizontal scanning circuit 78 sequentially selects the horizontal selection transistor circuit 76 in the horizontal direction and controls the output of the pixel signal. The output processing unit 79 performs predetermined processing on the signal from the horizontal signal line 77 and outputs the signal to the outside, and has, for example, a gain control circuit and a color processing circuit.

FIG. 8A is a diagram illustrating the structure of the pixel shown in FIG. 7, and FIG. 8B is a cross-sectional view of the transistor shown in FIG. 8A.
As shown in FIG. 8A, the pixel 70 includes a photodiode (PD) 1 that photoelectrically converts incident light, and an electric signal photoelectrically converted by the PD1 based on a transfer pulse (ΦTRG). A transfer transistor 83 for transferring to the FD) unit 82, a reset transistor 84 for resetting the potential of the FD unit 82 to the power supply voltage VDD based on a reset pulse (ΦRST), and a potential change of the FD unit 82 to a voltage signal or a current signal. An amplification transistor 85 for conversion and a selection transistor 86 for connecting the output of the amplification transistor 85 to the vertical signal line 73 based on the selection signal (ΦSEL).
In the vicinity of the pixel 70, a vertical signal line 73, a power supply line, and the like are wired in the vertical direction, and a readout line 83A, a reset line 84A, a selection line 85A, and the like are wired in the horizontal direction.
Note that the pixel 70 is not limited to the four-transistor configuration described above, and may have a three-transistor configuration that combines an amplification transistor and a selection transistor.

As shown in FIG. 8B, the transfer transistor 83, the reset transistor 84, the amplification transistor 85, and the selection transistor 86 are made of MOS transistors, and include a source 93 and a drain 94 formed on the semiconductor substrate 91, and the semiconductor substrate 91. A gate electrode 95 formed on the gate oxide film 92 is formed thereon. The gate electrode 95 has a three-layer structure in which a non-doped polysilicon layer 31 not doped with impurities, an oxide film layer 32, and a polysilicon layer 33 doped with impurities are stacked in that order.
Therefore, the gate electrode 95 can be formed with a gate electrode 95 having a designed channel length by preventing the conventional drawback that the short channel effect occurs because the oxide films at both ends of the gate electrode 95 are thick.
As described above, the semiconductor device having the MOS transistor can have a three-layer structure in which the gate electrode of the MOS transistor is a non-doped polysilicon layer 31 / an oxide film layer 32 / an impurity-doped polysilicon layer 33.
(Embodiment 3)

Hereinafter, an imaging apparatus according to Embodiment 3 to which the present invention is applied will be described.
FIG. 9 is a block diagram showing a configuration example of a camera apparatus using the image sensor of the present invention.
In FIG. 9, the imaging unit 310 images a subject using, for example, the CCD image sensor shown in FIGS. 1 to 6 and outputs an imaging signal to the system control unit 320 mounted on the main board. That is, the imaging unit 310 performs processing such as AGC (automatic gain control), OB (optical black) clamping, CDS (correlated double sampling), and A / D conversion on the output signal of the CCD image sensor described above, and performs digital processing. An imaging signal is generated and output.
In this example, an example in which an imaging signal is converted into a digital signal and output to the system control unit 320 in the imaging unit 310 is shown. However, an analog imaging signal is sent from the imaging unit 310 to the system control unit 320, and the system The control unit 320 may convert to a digital signal. Further, there are various methods for processing in the imaging unit 310, and it is needless to say that the processing is not particularly limited.

  The imaging optical system 300 includes a zoom lens 301 and a diaphragm mechanism 302 disposed in a lens barrel, and forms a subject image on a light receiving unit of a CCD image sensor. Under the control of the drive control unit 330 based on this, each part is mechanically driven to perform control such as autofocus.

The system control unit 320 includes a CPU 321, a ROM 322, a RAM 323, a DSP 324, an external interface 325, and the like.
The CPU 321 uses the ROM 322 and the RAM 323 to send an instruction to each part of the camera apparatus to control the entire system.
The DSP 324 performs various kinds of signal processing on the imaging signal from the imaging unit 310, thereby generating a still image or moving image video signal (for example, a YUV signal) in a predetermined format.
The external interface 325 is provided with various encoders and D / A converters, and with external elements (in this example, the display 360, the memory medium 340, and the operation panel unit 350) connected to the system control unit 320. Various control signals and data are exchanged.

The display 360 is a small display such as a liquid crystal panel incorporated in the camera apparatus, and displays a captured image. In addition to the small display device incorporated in such a camera device, it is of course possible to transmit the image data to an external large display device for display.
The memory medium 340 can appropriately store images taken on various memory cards, for example, and the memory medium can be exchanged with the memory medium controller 341, for example. As the memory medium 340, in addition to various memory cards, a disk medium using magnetism or light can be used.
The operation panel unit 350 is provided with input keys for a user to give various instructions when performing a photographing operation with the camera device. The CPU 321 monitors an input signal from the operation panel unit 350, Various operation controls are executed based on the input contents.

  By applying the present invention to such a camera device, it is possible to perform high-quality shooting for various subjects. In the above configuration, unit devices and unit modules as system components, a combination method, a set size, and the like can be appropriately selected based on the actual state of commercialization and the like. The device shall include a wide variety of variations.

In the solid-state imaging device and imaging device of the present invention, the imaging target (subject) is not limited to a general image such as a person or a landscape, but a special fine image pattern such as a counterfeit bill detector or a fingerprint detector. It can also be applied to. The apparatus configuration in this case is not the general camera apparatus shown in FIG. 9, but further includes a special imaging optical system and a signal processing system including pattern analysis. This makes it possible to realize accurate image detection.
Furthermore, when configuring a remote system such as telemedicine, security monitoring, personal authentication, etc., it is also possible to configure the device configuration including a communication module connected to the network as described above, and a wide range of applications can be realized. It is.

1 is a diagram illustrating a schematic configuration of a solid-state imaging device according to Embodiment 1. FIG. It is a figure which shows the structure of the vertical transfer register | resistor of the solid-state imaging device shown by FIG. It is a figure which shows the structure of the horizontal transfer register | resistor of the solid-state imaging device shown by FIG. FIG. 4 is a diagram showing a cross-sectional structure of the horizontal transfer register shown in FIG. 3. 6 is a diagram showing a method for manufacturing the solid-state imaging device according to Embodiment 1. FIG. It is a figure which shows the structure of the output part shown by FIG. FIG. 3 is a diagram illustrating a schematic configuration of a solid-state imaging device according to a second embodiment. FIG. 8A is a diagram illustrating the structure of the pixel shown in FIG. 7, and FIG. 8B is a cross-sectional view of the transistor shown in FIG. 8A. 6 is a diagram illustrating a configuration of an imaging apparatus according to Embodiment 3. FIG. It is a figure which shows the transfer electrode of the horizontal transfer register of the conventional CCD solid-state imaging device. It is a figure which shows the relationship between the oxidation treatment time of the silicon | silicone doped with phosphorus when the impurity concentration of phosphorus and process temperature are changed, and the film thickness of an oxide layer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Imaging region, 2 ... Peripheral region, 11 ... Photo sensor, 12 ... Vertical transfer register, 13 ... Channel stop, 14 ... Horizontal transfer register, 15 ... Output part, 21 ... Si substrate, 22... Vertical transfer channel, 23... Gate oxide film, 25... First vertical transfer electrode, 26... Second vertical transfer electrode (second wiring), 27. ... non-doped polysilicon layer, 32 ... oxide film layer, 33 ... impurity-doped polysilicon layer, 40 ... horizontal transfer channel, 41 ... horizontal transfer electrode.

Claims (13)

A plurality of sensor units for performing photoelectric conversion;
A plurality of vertical transfer registers for reading and transferring signal charges accumulated in the sensor unit in the vertical direction;
A horizontal transfer register that horizontally transfers signal charges transferred in the vertical direction by the plurality of vertical transfer registers;
The vertical transfer register has a plurality of vertical transfer electrodes,
The horizontal transfer register has a plurality of horizontal transfer electrodes,
At least one of the vertical transfer electrode and the horizontal transfer electrode has a three-layer structure in which a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order.
A solid-state imaging device. An output circuit that converts the signal charge transferred in the horizontal direction by the horizontal transfer register into a voltage and outputs the voltage;
The output circuit has a source follower circuit having a plurality of MOS transistors,
The solid-state imaging device according to claim 1, wherein a gate electrode of the MOS transistor has the three-layer structure.   The solid-state imaging device according to claim 1, wherein the oxide film layer has a thickness of 2 nm to 10 nm.   The solid-state imaging device according to claim 1, wherein the non-doped polysilicon layer has a thickness of 20 nm to 50 nm.   The solid-state imaging device according to claim 1, wherein a film thickness of the impurity-doped polysilicon layer is 150 nm or more and 250 nm or less. A plurality of sensor units for performing photoelectric conversion, a plurality of vertical transfer channels for reading and transferring signal charges accumulated in the sensor units in the vertical direction, and a signal charge transferred through the plurality of vertical transfer channels in the horizontal direction Forming a horizontal transfer channel for transferring to the semiconductor substrate;
Forming a plurality of vertical transfer electrodes on the vertical transfer channel, and forming a plurality of horizontal transfer electrodes on the horizontal transfer channel,
The transfer electrode forming step includes
A non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order to form the plurality of vertical transfer electrodes and the plurality of horizontal transfer electrodes;
A method of manufacturing a solid-state imaging device. An output circuit forming step of forming an output circuit that converts the signal charge transferred through the horizontal transfer channel into a voltage and outputs the voltage;
The output circuit forming step includes a source follower circuit forming step of forming a source follower circuit having a plurality of MOS transistors,
The source follower circuit forming step includes a gate electrode forming step of forming a gate electrode of the MOS transistor,
7. The solid-state imaging device according to claim 6, wherein in the gate electrode forming step, a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order. Production method.   8. The method of manufacturing a solid-state imaging device according to claim 7, wherein the transfer electrode formed in the transfer electrode forming step and the gate electrode formed in the gate electrode forming step are formed simultaneously. An imaging unit using a solid-state imaging device, a control unit that controls the imaging unit, and an operation unit that operates the imaging unit,
The solid-state imaging device
A plurality of sensor units for performing photoelectric conversion;
A plurality of vertical transfer registers for reading and transferring the signal charges accumulated in the sensor unit in the vertical direction;
A horizontal transfer register that horizontally transfers the signal charges transferred in the vertical direction by the plurality of vertical transfer registers;
The vertical transfer register has a plurality of vertical transfer electrodes,
The horizontal transfer register has a plurality of horizontal transfer electrodes,
At least one of the vertical transfer electrode and the horizontal transfer electrode has a three-layer structure in which a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order.
An imaging apparatus characterized by that. A plurality of sensor units for performing photoelectric conversion;
A transfer transistor that transfers the signal charge photoelectrically converted by the sensor unit to the signal charge detection unit;
A reset transistor for periodically resetting the potential of the signal charge detection unit;
An amplification transistor that detects a potential variation of the signal charge detection unit and converts it into an electrical signal;
The transfer transistor, the reset transistor, and the amplification transistor are each composed of a MOS transistor having a gate electrode provided on a semiconductor substrate.
The gate electrode of the MOS transistor has a three-layer structure in which a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order.
A solid-state imaging device. Forming a plurality of sensor portions for performing photoelectric conversion on a semiconductor substrate;
A transfer transistor that transfers the signal charge photoelectrically converted by the sensor unit to the signal charge detection unit, a reset transistor that periodically resets the potential of the signal charge detection unit, and a potential variation of the signal charge detection unit A transistor forming step of forming an amplification transistor for converting into an electric signal on a semiconductor substrate;
The transfer transistor, the reset transistor and the amplification transistor are composed of MOS transistors,
The transistor forming step includes a gate electrode forming step of forming a gate electrode of the MOS transistor on a semiconductor substrate,
The gate electrode forming step includes stacking a non-doped polysilicon layer not doped with an impurity, an oxide film layer, and a polysilicon layer doped with an impurity in that order to form gates of the transfer transistor, the reset transistor, and the amplification transistor. Forming electrodes,
A method of manufacturing a solid-state imaging device. A semiconductor substrate;
A MOS transistor provided on the semiconductor substrate;
The MOS transistor has a gate electrode provided on a semiconductor substrate,
The gate electrode has a three-layer structure in which a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities are laminated in that order.
A semiconductor device. Forming a source electrode and a drain electrode of a MOS transistor on a semiconductor substrate;
Forming a gate electrode of the MOS transistor on a semiconductor substrate,
The gate electrode forming step forms the gate electrode by laminating a non-doped polysilicon layer not doped with impurities, an oxide film layer, and a polysilicon layer doped with impurities in that order.
A method for manufacturing a semiconductor device.

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