JP2008227357A - Solid image pickup device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve picture quality by reducing the noise of an in-pixel transistor, and validly preventing the crystal defect of the periphery of an FD part. <P>SOLUTION: An element separation region (LOCOS or STI) 121 is formed at the predetermined position of a silicon substrate 100, and a silicon oxide film 111 for a diffusion layer element separation part 110 is formed. Afterwards, various types of ion injection or gate electrode pattern formation are carried out so that an in-layer insulating film 114 can be formed. Afterwards, connection holes 116, 117, 126, and 127 different in length are successively formed by the etching of another process, and conductive materials (tungsten/titanium nitride/titanium) are filled in those respective connection holes 116, 117, 126 and 127, and metallic plugs 118, 119. 128 and 129 different in length are formed. Also, one portion of a plug corresponding to the FD part can be replaced with a poly-silicon material. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device represented by a CMOS image sensor or the like, in which a laminated film including an upper wiring is provided on a semiconductor substrate provided with a pixel array portion, and a method for manufacturing the same.

In recent years, amplification-type solid-state imaging devices represented by CMOS image sensors have been actively developed. In this amplification type solid-state imaging device, a photodiode which is a photoelectric conversion unit and a signal charge generated by the photodiode are FD (floating diffusion) unit to each of a plurality of pixels constituting the imaging unit (pixel array unit). Read transistor, an amplification transistor that converts the signal charge read to the FD portion into a pixel signal and outputs the pixel signal to a vertical signal line, a reset transistor that resets the signal charge of the FD portion, and an output timing by the amplification transistor A selection transistor or the like for selecting is provided.
Various transistors (MOSFETs) formed in the pixel are collectively referred to as a pixel transistor. Further, various structures such as LOCOS, STI, and diffusion layer isolation are employed for element isolation on the silicon substrate. Among them, diffusion layer element isolation is effective in reducing noise such as dark current and white spots generated in pixels of a CMOS image sensor compared to conventional LOCOS and STI, and increases the dynamic range of the output image. It contributes.
On the silicon substrate provided with such pixels and the like, a laminated film including wirings and plugs such as pixel transistors is formed, and color filters and microlenses are formed thereon. Note that a polysilicon film and various metal films are used for the wiring material and the plug material depending on the use site.

12 and 13 are cross-sectional views showing the element configuration of a CMOS image sensor using diffusion layer element isolation technology, FIG. 12 shows the configuration of the pixel portion, and FIG. 13 shows the configuration of the peripheral circuit portion.
First, in FIG. 12, the FD portion 402 and the MOS transistor 403 are formed in a region isolated by the element isolation region 401 in the upper layer portion of the silicon substrate 400.
The element isolation region 401 is obtained by injecting a P-type diffusion layer into the silicon substrate 400, and constitutes a diffusion layer element isolation portion by a combination with the silicon oxide film 411 laminated thereon.
On the silicon substrate 400, a silicon oxide film 411 of the diffusion layer element isolation portion is formed via a gate insulating film (not shown), and a gate electrode 412 is formed.
The gate electrode 412 is formed of a polysilicon film, and is partially formed on the diffusion layer element isolation portion as shown in the figure.
In addition, a metal wiring (first metal wiring) 415 is arranged on the gate electrode 412 through various insulating films 413 and an interlayer insulating film 414 in the illustrated example, and the metal wiring 415 and the gate electrode 412 and the FD are arranged. A contact hole (connection hole) 416 is formed between the portions 402 as necessary, and a plug 417 such as tungsten is embedded to connect each element to the upper wiring.

Similarly, in FIG. 13, various MOS transistors 422 are formed in a region insulated and isolated by the element isolation region 421 in the upper layer portion of the silicon substrate 400.
This element isolation region 421 employs STI in which an oxide film is embedded in the silicon substrate 400. In FIG. 13, since the MOS transistor 422 has a CMOS structure and includes both N-channel and P-channel, the distinction between N-type and P-type is not particularly described.
A gate electrode 423 is formed on the silicon substrate 400 via a gate insulating film (not shown). Various insulating films 413 and an interlayer insulating film 414 are formed on the gate electrode 423. A metal wiring 415 is arranged between the metal wiring 415 and the gate electrode 423 as necessary, and a contact hole 416 is formed as necessary, and a plug 417 such as tungsten is embedded so that each element is connected to the upper wiring. Connected.
The upper wiring usually has a laminated structure of a plurality of layers, and a color filter, a microlens, and the like are arranged on the uppermost layer via a planarizing film.

In addition, in such a CMOS image sensor, with regard to noise reduction technology due to crystal defects related to contact connection in a pixel, when contact connection by a metal plug is formed in the FD portion, there is a crystal defect due to formation of an alloy of metal and silicon. It has been reported that this is a noise generation source of video signals (see, for example, Patent Document 1).
As a countermeasure against this crystal defect, it has been proposed to use polysilicon as a contact connection material.
JP 2005-72178 A

However, the prior art shown in FIGS. 12 and 13 has the following problems.
1) Noise reduction of amplification transistor First, when a contact hole is opened in the gate electrode of the amplification transistor by an etching method, PID (process induced damage) occurs in the MOSFET.
Due to this PID, the variation in the characteristics of the amplification transistors of each pixel is increased, and an output signal difference of the image sensor is generated, thereby degrading the image quality of the video signal.
Hereinafter, this phenomenon will be described.

As described above, when the diffusion layer isolation technique is adopted for element isolation in the pixel, the contact hole for connecting the gate electrode of the transistor formed in the diffusion layer element isolation region and the metal wiring of the first layer is shown in FIG. When the contact hole is opened by etching, the interlayer insulating film has the smallest thickness in the gate electrode in the pixel.
That is, the film thickness of the interlayer insulating film in the contact formation portion is thin on the gate electrode of the in-pixel transistor, thick on the gate electrode of the peripheral circuit portion, and thicker in the region without the gate electrode.
For this reason, when a contact mask is opened and a photoresist mask is formed in the same lithography process and etching is performed, a conductive object (that is, a gate electrode in a pixel) is first formed into a charged etchant generated by etching plasma. Finally, the silicon substrate is exposed to a charged etchant.
Therefore, the gate electrode is exposed to an etchant charged for a long time as compared with the silicon substrate, and charges are accumulated. When the potential difference from the silicon substrate increases due to the accumulation of the charges, the gate electrode passes through the gate insulating film (usually a silicon oxide film). This phenomenon flows into the silicon substrate, and this phenomenon damages the interface between the silicon oxide film and the silicon substrate, resulting in variations in transistor characteristics.
As a result, the characteristics of the amplifying transistor in the pixel vary, and it becomes impossible to amplify the signal in proportion to the signal (number of electrons) generated by the photodiode in the many elements in the pixel constituting the image sensor. Yes, it contributes to the noise of the video signal.

2) Crystal defects at the interface between the FD portion and the connection hole The interface between the connection hole and the silicon substrate is composed of a silicon substrate and titanium. That is, when tungsten is used as the main material of the plug, the material composition is silicon substrate → titanium → titanium nitride → tungsten.
For this reason, an alloying reaction between silicon and titanium (necessary for reducing and removing the naturally formed silicon oxide film existing on the silicon surface with titanium) occurs at the interface of the connection hole, and crystal defects occur in the silicon substrate. Because of this defect, noise was added to the video signal.
As a countermeasure, for example, as disclosed in Patent Document 1, it has been proposed to use polysilicon as a plug material.
However, in this method, the connection hole has a self-aligned structure with the gate electrode formed adjacent to the FD portion. For this reason, the distance between the connection hole and the gate electrode becomes close, and the parasitic capacitance increases, and as a result, it is difficult to read out the charge signal accumulated in the FD portion due to the influence of the parasitic capacitance (that is, all Cannot be read).

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device capable of effectively preventing noise in an in-pixel transistor and crystal defects around the FD portion and improving the image quality, and a method for manufacturing the same.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a semiconductor substrate on which a plurality of pixels are formed, and a stacked film formed on the semiconductor substrate, and the amount of light received in the pixels. And a plurality of pixel transistors that read out the signal charges accumulated in the photoelectric conversion unit to a floating diffusion unit, convert the signal charges into a pixel signal, and output the pixel signal. The connection hole for connecting to the gate electrode of at least one pixel transistor of the plurality of pixel transistors and the connection hole for connecting to the semiconductor substrate are formed by an etching process independent from each other. It is formed.

  The manufacturing method of the present invention includes a semiconductor substrate on which a plurality of pixels are formed, and a laminated film formed on the semiconductor substrate, and stores signal charges corresponding to the amount of received light in the pixels. A method for manufacturing a solid-state imaging device, comprising: a photoelectric conversion unit; and a plurality of pixel transistors that read out signal charges accumulated in the photoelectric conversion unit to a floating diffusion unit, convert the signal charges into pixel signals, and output the pixel signals. Of the connection holes formed in the film, the connection hole for connecting to the gate electrode of at least one pixel transistor of the plurality of pixel transistors and the connection hole for connecting to the semiconductor substrate are independent of each other. It is characterized by forming by.

  According to the solid-state imaging device and the manufacturing method thereof of the present invention, the connection hole for connecting to the gate electrode of the pixel transistor and the connection hole for connecting to the semiconductor substrate are formed by etching processes independent from each other. Each connection hole can be appropriately formed, noise in the pixel transistor can be reduced, crystal defects around the FD portion can be effectively prevented, and image quality can be improved.

In the embodiment of the present invention, the following method is adopted to reduce the PID of the gate electrode of the transistor in the pixel and the crystal defect of the FD portion in the CMOS image sensor.
First, in order to reduce noise generation due to PID of the gate electrode of the pixel amplification transistor, the following connection hole is formed.
First, a connection hole between the silicon substrate and the first layer metal wiring in the pixel region and a connection hole between the silicon substrate and the first layer metal wiring in the peripheral circuit region are formed in a common process.
In addition, a connection hole between the gate electrode on the diffusion layer element isolation in the pixel region and the first layer metal wiring is formed in another process.
Further, a connection hole between the gate electrode on the element isolation (LOCOS, STI, etc.) in the peripheral circuit region and the first layer metal wiring is formed in a further step.
In this way, a hole forming process corresponding to the thickness of the interlayer insulating film is performed separately, and by forming an appropriate contact plug, the PID of the gate electrode of the transistor in the pixel is reduced and noise suppression is realized.
Next, in order to reduce crystal defects in the FD portion, the following connection holes are formed.
First, polysilicon is used as a plug material embedded in the connection hole. In addition, the gate electrode adjacent to the FD portion is not self-aligned.

The outline of the connection hole forming process used in this embodiment will be described below.
Step 1) The connection hole between the silicon substrate and the gate electrode of the MOS transistor and the first layer metal wiring is opened by an etching method divided for each part.
Step 2) A connection hole is opened in the FD portion by etching and filled with polysilicon containing impurity ions (for example, phosphorus-doped or arsenic-doped) by a CVD method. Then, polysilicon other than the connection hole is removed by a CMP method or an etching method.
Step 3) The connection hole in the diffusion layer formation region of the silicon substrate is subjected to resist patterning by a lithography method and then opened by an etching method.
Step 4) Resist patterning is performed on the connection hole of the gate electrode on element isolation (such as LOCOS or STI) other than diffusion layer isolation by lithography, and then opening is performed by etching.
Step 5) The connection hole on the diffusion layer element isolation is subjected to resist patterning by a lithography method and then opened by an etching method.

If the PID at the time of forming the connection hole in step 4) does not become a noise source of the video signal in the operation of the image sensor, the connection holes in step 3) and step 4) may be formed simultaneously.
If the PID other than the time of etching on the gate electrode is small in the connection hole etching method in the above step 3), step 4) and step 5), the order of opening from step 3) to step 4) is changed. It may be moved back and forth. Further, when the PID of the transistor is small enough to be allowed in actual use in the etching in the above steps 3) and 4), the etching opening may be performed simultaneously.
In addition, after forming a plug in a connection hole, the manufacturing method similar to the conventional CMOS image sensor shall be used.

By using the method as described above, the following effects can be obtained.
First, by using the method shown in the above step 2), crystal defects at the interface between the FD portion and the connection hole can be eliminated. In addition, by securing the distance between the connection hole and the gate electrode of the transistor formed adjacent to the FD portion, the parasitic capacitance between the connection hole and the gate electrode when formed in a self-aligned manner can be reduced. It becomes possible.
In addition, by using the connection hole forming method shown in 3) to 5), it becomes possible to unify the thickness of the interlayer insulating film in the wafer plane when the connection hole is opened on the gate electrode by the etching method. As a result, the over-etching time of the opening etching of the connection hole can be shortened.
As described above, a CMOS image sensor with less noise can be manufactured.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
First, the overall configuration of a CMOS image sensor to which the present invention is applied will be described.
FIG. 1 is a plan view showing a specific example of a solid-state imaging device in an embodiment of the present invention, and shows an example of a CMOS image sensor. FIG. 2 is a circuit diagram showing a circuit configuration in a pixel of the solid-state imaging device shown in FIG.
As shown in FIG. 1, the solid-state imaging device of the present embodiment includes a pixel array unit 20 that forms an imaging region by a plurality of pixels 16 arranged in a two-dimensional direction, and each pixel of the pixel array unit 20 is arranged in the vertical direction. A vertical scanning circuit 21 that scans and controls a pixel signal reading operation, a load MOS transistor circuit 24 that controls a vertical signal line 28 led from each pixel column of the pixel array unit 20, and a pixel array unit 20 A CDS circuit 26 that takes in pixel signals read from each pixel column and removes noise by correlated double sampling processing, a horizontal selection transistor circuit 26 that outputs pixel signals of the CDS circuit 26 to a horizontal signal line 27, A horizontal scanning circuit 22 for sequentially selecting the horizontal selection transistor circuit 26 in the horizontal direction and controlling the output of the pixel signal.
The pixel signal output to the horizontal signal line 27 is transmitted to the subsequent circuit through the buffer amplifier.

Further, as shown in FIG. 2, each pixel 16 includes a photodiode (PD) 1 that photoelectrically converts incident light, and a floating diffusion (FD) based on a transfer pulse (ΦTRG) of the photoelectrically converted electric signal. The transistor (TG) 12 transferred to the unit 3, the reset transistor (RST) 14 that resets the potential of the FD unit 3 to the power supply voltage VDD based on the reset pulse (ΦRST), and the potential fluctuation of the FD unit 3 as a voltage signal or current An amplification transistor (AMP) 13 that converts the signal into a signal and a selection transistor 15 that connects the output of the amplification transistor 13 to the vertical signal line 28 based on the selection signal (ΦSEL).
Therefore, in the vicinity of the pixel 16, a vertical signal line 28, a power supply line 23, and the like are wired in the vertical direction, and a readout line 17, a reset line 18, a selection line 19, and the like are wired in the horizontal direction.

Next, a method for forming a connection hole according to an embodiment of the present invention will be described.
3 to 6 are cross-sectional views showing a method of forming a connection hole according to the first embodiment of the present invention, and show a case where a metal material is used for a connection plug for the first metal wiring.
First, in FIG. 3A (pixel region), an FD portion 102 and a MOS transistor 103 are formed in a region isolated by the element isolation region 101 in the upper layer portion of the silicon substrate 100, and a gate insulating film ( A silicon oxide film 111 and a polysilicon gate electrode 112 are formed in the diffusion layer separation portion, and various insulating films 113 and interlayer insulating films 114 are stacked.
Similarly, in FIG. 3B (peripheral circuit region), various MOS transistors 122 are formed in regions isolated by STI element isolation regions 121 in the upper layer portion of the silicon substrate 100. Note that the MOS transistor 122 has a CMOS structure and includes both N-channel and P-channel, so that the distinction between N-type and P-type is not particularly described.
A gate electrode 123 is formed on the silicon substrate 100 via a gate insulating film (not shown), and various insulating films 113 and an interlayer insulating film 114 are laminated on the gate electrode 123. Yes.

The configuration shown in FIG. 3 is formed by the following procedure, for example.
First, after an element isolation region (LOCOS or STI) 121 is formed at a predetermined position on the silicon substrate 100, a silicon oxide film 111 for the diffusion layer element isolation part 110 is formed.
Next, a pattern is formed in each region of the silicon substrate 100 with a photoresist, and impurity ion implantation is performed. Then, after the ion implantation, the photoresist is peeled off by chemical treatment.
Next, a gate insulating film (gate oxide film) is formed, a polysilicon film is formed thereon by CVD, and a gate electrode pattern is formed by photoresist pattern formation, etching, and resist stripping.
Thereafter, LDD formation is performed, and impurity ion implantation is performed in the source / drain regions. Then, heat treatment is performed to activate the implanted ions.
Then, an interlayer insulating film is formed thereon.

Then, in such a stacked state, connection holes 116 and 126 that reach the silicon substrate (FD portion) 100 are formed in both the pixel region and the peripheral circuit region. Since these films have the same type and thickness of the intervening insulating film, they can be formed with high accuracy in an appropriate time by performing etching under the same conditions.
Next, as shown in FIG. 4, a connection hole 127 reaching the gate electrode 123 existing on the LOCOS or STI element isolation region is formed.
Next, as shown in FIG. 5, a connection hole 117 reaching the gate electrode 112 existing on the diffusion layer element isolation part 110 is formed.
Thereafter, as shown in FIG. 6, conductive materials (tungsten / titanium nitride / titanium) are embedded in the connection holes 116, 117, 126, and 127 to form plugs 118, 119, 128, and 129 having different lengths. .
A first metal wiring (not shown) is formed on the upper surface, but the subsequent manufacturing method is the same as the conventional method, and the description thereof is omitted.

Next, Example 2 will be described.
7 to 8 are cross-sectional views showing a method of forming a connection hole according to the second embodiment of the present invention, and show a case where a polysilicon material is used for a part of the connection plug for the first metal wiring. In addition, about the structure which is common in FIGS. 3-6, the same code | symbol is attached | subjected and demonstrated.
The state shown in FIG. 7 is substantially the same as the state shown in FIG. 3, but the interlayer insulating film 114A is formed in a state where it is thinner by a predetermined amount than the interlayer insulating film 114 shown in FIG.
In this state, for example, a connection hole 116A using a polysilicon plug is formed in a region corresponding to the FD portion 102. Then, as shown in FIG. 8, a polysilicon material is buried in the connection hole 116A to form a plug 118A (herein referred to as a second layer polysilicon plug).

Next, as shown in FIG. 9, an additional interlayer insulating film 114B is stacked on the interlayer insulating film 114A. As a result, the film is formed to a thickness equivalent to that of the interlayer insulating film 114 shown in FIG.
Next, in a separate process, the remaining connection hole 116B of the connection hole 116A is formed in the interlayer insulating film 114B, the connection hole 117 is formed in the interlayer insulating films 114A and 114B, and the interlayer insulating films 114A and 114B are formed. A connection hole 126 is formed for the interlayer insulating films 114A and 114B.
Then, a conductive material (tungsten / titanium nitride / titanium) serving as a plug material is embedded in these connection holes 116B, 117, 126, 127 to form metal plugs 118B (herein referred to as first layer metal plugs), 119, 128 and 129 are formed.
In this way, a configuration using a polysilicon plug can be created only on the FD portion.
In addition, since processes such as individual film formation and perforation are the same as those in the first embodiment, description thereof is omitted.

In the above embodiment, the following effects can be expected.
(1) Overetching at the time of forming a connection hole applied to the gate electrode in the pixel can be reduced, and as a result, characteristic deterioration due to PID of the transistor can be eliminated.
Thereby, uniform signal amplification can be performed by the amplification transistor, and noise generation can be reduced.
(2) By using a connection hole that is not a self-alignment structure in the connection hole of the FD portion and using polysilicon as the material of the connection hole, crystal defects at the interface between the connection hole and the silicon substrate can be eliminated.
(3) By connecting the gate electrode of the amplification transistor of the pixel and the FD portion with the second layer polysilicon plug, a part of the first layer metal plug that has been conventionally used can be replaced. As a result, the wiring occupation ratio of the first-layer metal plug can be reduced and the opening area of the illumination light can be expanded. Further, as the area of the first-layer metal plug is reduced, the phenomenon that light is reflected by the metal wiring (so-called vignetting) can be reduced.
Thereby, it is possible to accurately read out the charges accumulated in the FD portion.

The specific embodiments of the solid-state imaging device according to the present invention have been described above, but the present invention can be further modified in various ways. For example, in the above embodiment, the description is given on the assumption that four transistors (reading, reset, amplification, and selection) are provided in one pixel. For example, a three-transistor configuration in which the selection transistor is omitted, A five-transistor configuration having two transistors for row selection and column selection has also been proposed, and the present invention can be applied to any method.
The solid-state imaging device to which the present invention can be applied is not limited to the two-dimensional area type CMOS image sensor as shown in the figure, and can be applied to a one-dimensional array linear sensor type solid-state imaging device, and has an FD section. It can be widely applied to solid-state imaging devices.

  The solid-state imaging device is not limited to an image sensor or the like configured on one chip, and may be a module in which an imaging unit, a signal processing unit, and an optical system are packaged together. Moreover, the apparatus utilized for a camera system or a mobile telephone device may be used. In the present invention, a configuration having a CMOS image sensor function alone is called a solid-state imaging device, and the solid-state imaging device and other elements (control circuit, operation unit, display unit, data storage function, communication function, etc.) An integrated configuration is referred to as an imaging device.

Hereinafter, a specific example of an imaging apparatus to which the present invention is applied will be described.
FIG. 11 is a block diagram showing a configuration example of a camera device using the CMOS image sensor of this example.
In FIG. 11, an imaging unit 310 performs imaging of a subject using, for example, the CMOS image sensor shown in FIG. 1, and outputs an imaging signal to a system control unit 320 mounted on the main board.
That is, the imaging unit 310 performs processing such as AGC (automatic gain control), OB (optical black) clamping, CDS (correlated double sampling), and A / D conversion on the output signal of the above-described CMOS image sensor, and performs digital processing. An imaging signal is generated and output.

In this example, an example in which an imaging signal is converted into a digital signal and output to the system control unit 320 in the imaging unit 310 is shown. However, an analog imaging signal is sent from the imaging unit 310 to the system control unit 320, and the system The control unit 320 may convert to a digital signal.
Various methods have been conventionally provided for specific control operations, signal processing, and the like in the imaging unit 310, and it is needless to say that the imaging device of the present invention is not particularly limited.

  The imaging optical system 300 includes a zoom lens 301 and an aperture mechanism 302 disposed in a lens barrel, and forms a subject image on the light receiving unit of the CMOS image sensor. Under the control of the drive control unit 330 based on this, each part is mechanically driven to perform control such as autofocus.

The system control unit 320 includes a CPU 321, a ROM 322, a RAM 323, a DSP 324, an external interface 325, and the like.
The CPU 321 uses the ROM 322 and the RAM 323 to send an instruction to each part of the camera apparatus to control the entire system.
The DSP 324 performs various kinds of signal processing on the imaging signal from the imaging unit 310, thereby generating a still image or moving image video signal (for example, a YUV signal) in a predetermined format.
The external interface 325 is provided with various encoders and D / A converters, and with external elements (in this example, the display 330, the memory medium 340, and the operation panel unit 350) connected to the system control unit 320. Various control signals and data are exchanged.

The display 330 is a small display such as a liquid crystal panel incorporated in the camera apparatus, and displays a captured image. In addition to the small display device incorporated in such a camera device, it is of course possible to transmit the image data to an external large display device for display.
The memory medium 340 can appropriately store images taken on, for example, various memory cards, and can replace the memory medium with the memory medium controller 341, for example. As the memory medium 340, in addition to various memory cards, a disk medium using magnetism or light can be used.
The operation panel unit 350 is provided with input keys for a user to give various instructions when performing a photographing operation with the camera device. The CPU 321 monitors an input signal from the operation panel unit 350, Various operation controls are executed based on the input contents.

  By applying the solid-state imaging device of the present invention to such a camera device, a high-quality imaging device can be provided. In the above configuration, unit devices and unit modules as system components, a combination method, a set size, and the like can be appropriately selected based on the actual state of commercialization and the like. The device shall include a wide variety of variations.

In the solid-state imaging device and imaging device of the present invention, the imaging target (subject) is not limited to a general image such as a person or a landscape, but a special fine image pattern such as a counterfeit bill detector or a fingerprint detector. It can also be applied to.
The apparatus configuration in this case is not the general camera apparatus shown in FIG. 11, but further includes a special imaging optical system and a signal processing system including pattern analysis. In this case as well, the operational effects of the present invention are included. This makes it possible to realize accurate image detection.
Furthermore, when configuring a remote system such as telemedicine, security monitoring, personal authentication, etc., it is also possible to configure the device configuration including a communication module connected to the network as described above, and a wide range of applications can be realized. It is.

It is a top view which shows the specific example of the solid-state imaging device in the Example of this invention. FIG. 2 is a circuit diagram showing a circuit configuration in a pixel of the solid-state imaging device shown in FIG. 1. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 1 of this invention. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 1 of this invention. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 1 of this invention. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 1 of this invention. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 2 of this invention. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 2 of this invention. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 2 of this invention. It is sectional drawing which shows the formation process of the CMOS image sensor by Example 2 of this invention. It is a block diagram which shows the structural example of the camera apparatus in the other Example of this invention. It is sectional drawing which shows the structure of FD part periphery in the pixel area | region of the conventional CMOS image sensor. It is sectional drawing which shows the structure in the peripheral circuit area | region of the conventional CMOS image sensor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Silicon substrate, 101, 121 ... Element isolation region, 102 ... FD part, 103, 122 ... MOS transistor, 110 ... Diffusion layer isolation part, 112, 123 ... Gate electrode, 113 ... Insulating film, 114... Interlayer insulating film.

Claims (10)

A photoelectric conversion unit having a semiconductor substrate on which a plurality of pixels are formed and a stacked film formed on the semiconductor substrate, and storing signal charges in accordance with the amount of received light in the pixels; and the photoelectric conversion A plurality of pixel transistors that read out the signal charge accumulated in the unit to the floating diffusion unit, convert it into a pixel signal, and output it,
Of the connection holes formed in the stacked film, a connection hole for connecting to a gate electrode of at least one pixel transistor of the plurality of pixel transistors and a connection hole for connecting to the semiconductor substrate are independent from each other. Formed by an etching process,
A solid-state imaging device.   Of the connection holes formed in the laminated film, the connection holes for connecting to the floating diffusion portion are not adjacent to the conductive material used for the gate electrode of the pixel transistor adjacent to the floating diffusion portion in a self-aligning manner. The solid-state imaging device according to claim 1, further comprising a hole.   3. The solid-state imaging device according to claim 2, wherein a polysilicon material containing an impurity for enhancing conductivity is used as a plug material formed in a connection hole for connecting to the floating diffusion portion.   4. The solid-state imaging device according to claim 3, wherein the impurity is phosphorus or arsenic.   A polysilicon material is used for the plug material formed in the connection hole of the gate electrode of the pixel transistor, and a polysilicon material is used for the plug material formed in the connection hole of the floating diffusion portion. 3. The solid-state imaging device according to claim 2, wherein a polysilicon material or a material in which metal wiring is laminated on the polysilicon is used as the material. A photoelectric conversion unit having a semiconductor substrate on which a plurality of pixels are formed and a stacked film formed on the semiconductor substrate, and storing signal charges in accordance with the amount of received light in the pixels; and the photoelectric conversion A method of manufacturing a solid-state imaging device including a plurality of pixel transistors that read out signal charges accumulated in the unit to the floating diffusion unit, convert the pixel charges into pixel signals, and output the pixel signals,
Of the connection holes formed in the stacked film, a connection hole for connecting to a gate electrode of at least one pixel transistor of the plurality of pixel transistors and a connection hole for connecting to the semiconductor substrate are independent of each other. Formed by an etching process,
A method of manufacturing a solid-state imaging device.   Of the connection holes formed in the laminated film, the connection holes for connecting to the floating diffusion portion are not adjacent to the conductive material used for the gate electrode of the pixel transistor adjacent to the floating diffusion portion in a self-aligning manner. The method for manufacturing a solid-state imaging device according to claim 6, wherein a hole is formed.   8. The method of manufacturing a solid-state imaging device according to claim 7, wherein a polysilicon material containing an impurity for enhancing conductivity is used as a plug material formed in a connection hole for connecting to the floating diffusion portion.   9. The method of manufacturing a solid-state imaging device according to claim 8, wherein the impurity is phosphorus or arsenic.   A polysilicon material is used for the plug material formed in the connection hole of the gate electrode of the pixel transistor, and a polysilicon material is used for the plug material formed in the connection hole of the floating diffusion portion. 8. The method of manufacturing a solid-state imaging device according to claim 7, wherein a polysilicon material or a material in which a metal wiring is laminated on the polysilicon is used as the material.

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