JP2010219563A - Solid-state imaging device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the read-out characteristics of a MOS solid-state imaging device. <P>SOLUTION: The solid-state imaging device includes: a photoelectric conversion unit 23 having a semiconductor region 26 of a second conductivity type and an accumulation region 27 of a first conductivity type on the surface of the semiconductor region, a floating diffusion unit 24, a transfer gate electrode 32 composed of an n-type semiconductor, a sidewall 34 composed of an n-type semiconductor formed on the photoelectric conversion side of the transfer gate electrode 32 via an insulating film 33, and a sidewall 35 composed of an insulating layer formed on the floating diffusion side of the transfer gate electrode 32. The accumulation region 27 is formed, either not directly under the sidewall 34, or partially overlapping the sidewall 34. On the sidewall 34 on the photoelectric conversion unit side, the voltage of the transfer gate electrode 32 is applied through a coupling capacitance. At the reading out charge, the read-out voltage is applied on the transfer gate electrode 32. At the charge storage, the voltage that induces charge, which is the inverse of the signal charge, directly under the sidewall on the photoelectric conversion unit side, is applied on the transfer gate electrode 32. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an electronic apparatus including the solid-state imaging device.

The solid-state imaging device includes a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor and an M such as a CMOS (Complementary Metal Oxide Semiconductor).
It is roughly classified into an amplification type solid-state imaging device represented by an OS type image sensor. When comparing a CCD image sensor and a MOS type image sensor, the CCD image sensor requires a high driving voltage for transferring signal charges, and therefore the power supply voltage must be higher than that of the MOS type image sensor.

  Therefore, in recent years, solid-state imaging devices mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) have a lower power supply voltage than CCD image sensors, and from the viewpoint of power consumption, CCD images MOS type image sensors that are more advantageous than sensors are often used.

  The MOS type image sensor is composed of an imaging region in which a unit pixel is formed by a photodiode which is a photoelectric conversion unit and a plurality of MOS transistors, and the plurality of unit pixels are arranged in an array, and a peripheral circuit region. The

  FIG. 15 shows a main part of a charge reading portion of a pixel of a conventional general MOS image sensor. In the pixel, a photodiode 102 serving as a photoelectric conversion portion and an n-type semiconductor region from which signal charges of the photodiode 102 are read, that is, a floating diffusion portion 103 are formed on the semiconductor substrate 101. A transfer transistor Tr1 is formed by forming a gate electrode (so-called transfer gate electrode) 105 between the photodiode 102 and the floating diffusion portion 103 via a gate insulating film 104, and a charge reading portion is formed here. The

The photodiode 102 is an embedded photodiode having an n-type semiconductor region 107 serving as a charge storage region and a p-type semiconductor region formed at an interface portion of the surface, that is, a so-called p-type accumulation layer 108. It is configured. The photodiode 102 is configured as a so-called HAD (Hole Accumulation Diode) sensor. A sidewall 106 made of an insulating layer is formed on the sidewall of the gate electrode 105.

  In the charge accumulation period, 0 V is applied to the gate electrode 105, the transfer transistor Tr1 is turned off, and the signal charge is accumulated in the photodiode 102. At the time of reading, a positive voltage is applied to the gate electrode 105 to transfer the signal charge accumulated in the photodiode 102 to the floating diffusion portion 103.

  In the photodiode 102, signal charges corresponding to the amount of incident light and dark current components (dark electrons) that flow into the photodiode 102 even when no light is incident are accumulated during the charge accumulation period. Dark electrons are electrons that flow out from the interface between the insulating film and the silicon region under the gate electrode 105, become fixed pattern noise, and cause white spots.

  As a technique for improving this, a MOS image sensor disclosed in Patent Document 1 that reduces dark current by applying a negative voltage to the gate electrode of a transfer transistor during a charge accumulation period has been proposed. As shown in FIG. 16, the MOS image sensor has a configuration in which a negative voltage −V is applied to the gate electrode 105 of the transfer transistor Tr1 during the charge accumulation period. In this configuration, by applying a negative voltage −V to the gate electrode 105, a hole (hole) h is induced immediately below the gate electrode 105 to turn off the transfer transistor Tr 1, and at the same time, a side near the gate electrode 105. A hole h is also induced just below the wall 106 by a fringe capacitance. That is, a hole pinning state is created electrically immediately below the gate electrode 105 and immediately below the sidewall 106 in the vicinity of the gate electrode 105. As a result, the white spot is suppressed by recombining the electrons that spring out at the interface between the gate insulating film 104 and the sidewall 106 in the vicinity thereof and the silicon region with the hole h.

  Further, in Patent Document 2, the gate electrode of a transfer transistor is formed of p-type polysilicon having a work function difference with respect to an intrinsic semiconductor, and dark current from the transfer gate interface can be reduced without introducing a negative voltage. There has been proposed a MOS image sensor that suppresses the occurrence.

  By the way, when the signal charge of the photodiode 102 is read out to the floating diffusion portion 103, when the p-type accumulation layer 108 approaches the gate electrode 105, the read voltage Vtg of the transfer transistor Tr1 becomes high and it becomes difficult to read out. FIG. 3 shows the potential distribution before reading out signal charges and the potential distribution during reading. In the configuration of the normal charge reading portion in FIG. 15, a read voltage is applied to the gate electrode 105 of the transfer transistor Tr1, and the signal charge of the photodiode 102 is read by modulating the potential a before reading. At this time, if the read voltage is low, as shown in FIG. 3, a potential barrier c is formed immediately below the side wall 106, making it difficult to read the signal charge. In order to make it easy to read out the signal charges, a high read voltage is needed to collapse the potential barrier c. Note that FIG. 3A corresponds to the reading portion of the conventional example.

  In recent MOS solid-state imaging devices, improvement of readout characteristics is desired.

  In order to make it easy to read out the signal charge, it is conceivable to separate the high-concentration p-type accumulation layer 108 from the gate electrode 105, but this causes a white spot. When the p-type accumulation layer 108 is brought close to the vicinity of the gate electrode 105 in order to suppress the generation of white spots, the read voltage increases. There is a contradictory relationship between improving read characteristics and suppressing white spot generation.

  Looking at the relationship between the read characteristics and the saturation charge amount (maximum handled charge amount) Qs of the photodiode, if the concentration of the n-type semiconductor region of the photodiode is increased, Qs increases, but it becomes difficult to read. Increasing the concentration of the n-type semiconductor region causes an increase in white spots.

JP 2002-217397 A JP 2006-32681 A

  In view of the above, the present invention provides a solid-state imaging device with improved readout characteristics, and an electronic apparatus including the solid-state imaging device.

  A solid-state imaging device according to the present invention includes a photoelectric conversion portion having a second conductivity type semiconductor region and a first conductivity type accumulation region on the surface thereof, a floating diffusion portion, a transfer gate electrode made of an n-type semiconductor, and a transfer The n-type semiconductor side wall is formed on the photoelectric conversion part side of the gate electrode through an insulating film, and the insulating layer side wall is formed on the floating diffusion part side of the transfer gate electrode. The accumulation region is not formed directly under the sidewall, or part of it overlaps the sidewall. The voltage of the transfer gate electrode is applied to the sidewall on the photoelectric conversion unit side through a coupling capacitor. A read voltage is applied to the transfer gate electrode at the time of charge reading, and a voltage that induces a charge opposite to the signal charge immediately below the side wall on the photoelectric conversion unit side is applied to the transfer gate electrode at the time of charge accumulation. .

  In the solid-state imaging device of the present invention, the sidewall of the n-type semiconductor is formed on the photoelectric conversion portion side of the transfer gate electrode of the n-type semiconductor via the insulating film, so that a read voltage is applied to the transfer gate electrode. The read voltage is also applied to the sidewalls of the n-type semiconductor due to the coupling capacitance. For this reason, the potential of the photoelectric conversion portion immediately below the sidewall is gently modulated without forming a barrier, and signal charges can be read at a low voltage. Also, with this configuration, during charge accumulation, the regions under the n-type transfer gate electrode and directly under the n-type sidewall are in a hole pinning state, and white spot generation is suppressed.

An electronic apparatus according to the present invention includes a solid-state imaging device, an optical system that guides incident light to a photoelectric conversion unit of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device.
The solid-state imaging device includes a photoelectric conversion portion having a second conductivity type semiconductor region and a first conductivity type accumulation region on the surface thereof, a floating diffusion portion, a transfer gate electrode made of an n-type semiconductor, and a photoelectric transfer gate electrode. The n-type semiconductor side wall is formed on the conversion part side through an insulating film, and the insulating layer side wall is formed on the floating diffusion part side of the transfer gate electrode. The accumulation region is not formed directly under the sidewall, or part of it overlaps the sidewall. The voltage of the transfer gate electrode is applied to the sidewall on the photoelectric conversion unit side through a coupling capacitor. A read voltage is applied to the transfer gate electrode at the time of charge reading, and a voltage that induces a charge opposite to the signal charge immediately below the sidewall on the photoelectric conversion unit side is applied to the transfer gate electrode at the time of charge accumulation.

  In the electronic apparatus of the present invention, the signal charge can be read at a low voltage by including the solid-state imaging device according to the present invention. Further, it is possible to suppress the generation of white spots or to improve the saturation charge amount.

With the solid-state imaging device according to the present invention, it is possible to improve the signal charge readout characteristics.
According to the electronic apparatus of the present invention, it is possible to improve signal charge readout characteristics in a solid-state imaging device.

It is a schematic block diagram which shows an example of the MOS type solid-state imaging device to which this invention is applied. 1 is a configuration diagram illustrating a first embodiment of a solid-state imaging device according to the present invention. A, B, and C are a cross-sectional view of a conventional read portion, a cross-sectional view of a read portion of the first embodiment of the present invention, and a potential distribution diagram before and during reading. It is a block diagram which shows 2nd Embodiment of the solid-state imaging device which concerns on this invention. It is a top view which shows an example of the pixel layout applied to this invention. It is an enlarged plan view of the principal part of FIG. It is sectional drawing with which it uses for description of the solid-state imaging device of 2nd Embodiment concerning this invention. It is a block diagram which shows 3rd Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram which shows 4th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram which shows 5th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram which shows the example of the transfer gate electrode of the solid-state imaging device which concerns on this invention. It is a block diagram which shows the example of the transfer gate electrode of the solid-state imaging device which concerns on this invention. It is a block diagram which shows the example of the transfer gate electrode of the solid-state imaging device which concerns on this invention. It is a schematic block diagram of the electronic device which concerns on this invention. It is a block diagram of the read-out part of the solid-state imaging device which concerns on a prior art example. It is a block diagram of the read-out part of the solid-state imaging device which concerns on another prior art example.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic configuration of an example of a solid-state imaging device applied to the present invention, that is, a MOS type solid-state imaging device. The solid-state imaging device 1 of this example includes a pixel unit (so-called imaging region) 3 in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged in a semiconductor substrate 11, for example, a silicon substrate, a peripheral circuit unit, It is comprised. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion element and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be configured by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, for example, a selection transistor can be added and configured by four transistors. Since the equivalent circuit of these unit pixels is the same as usual, detailed description is omitted.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 generates a clock signal and a control signal as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, and selectively scans each pixel 2 of the pixel unit 3 in the vertical direction sequentially in units of rows, and is a photoelectric conversion element of each pixel 2 through the vertical signal line 9, for example, a photodiode. A pixel signal based on the signal charge generated according to the amount of received light is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and signals output from the pixels 2 for one row are generated from black reference pixels (formed around the effective pixel region) for each pixel column. The signal processing such as noise removal is performed by the signal. That is, the column signal processing circuit 5 removes fixed pattern noise unique to the pixel 2, for example, an S / H (sample hold) circuit and a CDS (Correlated Double Sampling) circuit, or a signal such as signal amplification. Process. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.

  A multilayer wiring layer is formed above the substrate 11 on which the pixel portion 3 and the peripheral circuit portion are formed via an interlayer insulating film. In the pixel unit 3, an on-chip color filter is formed on the multilayer wiring layer via a planarizing film, and an on-chip microlens is further formed thereon. A light-shielding film is formed in a region other than the pixel portion in the imaging region, more specifically, in the peripheral circuit portion and other region other than the photodiode (so-called light receiving portion) in the imaging region. This light shielding film can be formed by, for example, the uppermost wiring layer of the multilayer wiring layer.

  Next, an embodiment of the present invention applied to a so-called readout portion including the photoelectric conversion portion, the floating diffusion portion, and the transfer transistor in the unit pixel 2 will be described.

  FIG. 2 shows a first embodiment of a solid-state imaging device according to the present invention, particularly a first embodiment of a readout portion thereof. The solid-state imaging device 21 according to the present embodiment includes a photodiode (PD) 23 serving as a photoelectric conversion unit in a region of each unit pixel of the first conductivity type, in this example, a p-type semiconductor substrate 22, and a first conductivity type. A floating diffusion portion (FD) 24 made of an n-type semiconductor region and a read portion 25 made up of a transfer transistor Tr1 are formed.

  The photodiode 23 is formed of a buried photodiode having an n-type semiconductor region 26 of the second conductivity type and a p-type accumulation layer 27 on the surface thereof. The transfer transistor Tr1 forms an n-type semiconductor, that is, a transfer gate electrode (hereinafter referred to as n + gate electrode) 32 of an n-type semiconductor, that is, polysilicon via a gate insulating film 31 on the substrate surface between the photodiode 23 and the floating diffusion portion 24. Configured. In the transfer transistor Tr1, the photodiode 23 serves as a source region, and the floating diffusion portion 24 serves as a drain region. The gate insulating film 31 is formed of, for example, a silicon oxide film.

  Further, an n-type semiconductor, that is, a side wall made of polysilicon (hereinafter referred to as n + poly side wall) 34 is formed on the n + gate electrode 32 on the photodiode 23 side through an insulating film 33, for example, a silicon oxide film. A sidewall (hereinafter referred to as an insulating sidewall) 35 made of an insulating layer is formed on the floating diffusion portion 24 side of the n + gate electrode 32. This insulating sidewall 35 has a two-layer structure in this example, and is formed of, for example, two layers of a silicon oxide film 33 and a silicon nitride layer 36. The insulating sidewall 35 can also be formed with a single layer structure or a multilayer structure of two or more layers.

  The n + poly sidewall 34 is formed corresponding to the n-type semiconductor region 26 of the photodiode 23. The n-type semiconductor region 26 is formed so as to partially overlap the n + gate electrode 32, and the p + accumulation layer 27 is formed so as to partially overlap the n + poly sidewall 34. The floating diffusion portion 24 is formed so that a part thereof passes under the insulating sidewall 35 and overlaps a part of the n + gate electrode 32.

  According to the solid-state imaging device 21 according to the first embodiment, a positive voltage is applied to the n + gate electrode 32 at the time of reading out the signal charge from the photodiode 23 to the floating diffusion unit 24. This positive voltage is also applied to the n + poly sidewall 34 by the coupling capacitance. By applying a gate voltage to the n + poly sidewall 34, the potential of the n-type semiconductor region 26 of the photodiode 23 immediately below the n + poly sidewall 34 is modulated. As shown in the potential distribution b at the time of reading in FIG. 3C, this potential modulation is modulated so that the potential barrier c is crushed just below the n + poly sidewall 34 and has a gentle gradient. Note that FIG. 3B corresponds to the reading portion 25 of the present embodiment. This gentle gradient potential distribution b makes it easy to read out and allows signal charges to be read out at a low voltage. That is, read characteristics are improved.

  A negative voltage is applied to the n + gate electrode 32 during the signal charge accumulation period. Since this negative voltage is also applied to the n + poly sidewall 34 by the coupling capacitance, a hole h is induced on the surface of the n-type semiconductor region 26 of the photodiode 23 immediately below the n + poly sidewall 34. That is, the surface of the n-type semiconductor region 26 immediately below the n + poly sidewall 34 is in a so-called hole pinning state. At the same time, the channel surface directly under the n + gate electrode 32 is also in the hole pinning state. Since the channel surface and the surface of the n-type semiconductor region 26 of the photodiode 23 just below the n + poly sidewall 34 are hole-pinned, electrons that have spouted from the interface of the insulating film recombine with the holes h to suppress the generation of white spots Can do.

  Since the sidewall 35 on the floating diffusion portion 24 side is formed of an insulating sidewall, the capacity of the floating diffusion portion 24 can be reduced and the conversion efficiency can be improved. The capacitance of the floating diffusion portion 24 in this case is the overlap capacitance between the floating diffusion portion 24 and the sidewall 35. For example, when the sidewall 35 is formed of a poly sidewall in the same manner as the photodiode 23 side. The overlap capacity becomes large and the conversion efficiency decreases.

  FIG. 4 shows a second embodiment of the solid-state imaging device according to the present invention, in particular, a second embodiment of its readout portion. 4 is a cross-sectional view taken along the line AA of FIG. 5 and the pixel layout of FIG. 5 and an enlarged view of the main part of FIG.

  First, the pixel layout will be described with reference to FIG. The pixel layout of the solid-state imaging device according to the present embodiment is a pixel layout in which a required pixel transistor is shared by four photoelectric conversion units, and so-called four pixel sharing is used as one unit. In this solid-state imaging device, as shown in FIG. 5, four photoelectric conversion units 42, 43, 44 and 45 are arranged in two columns and two rows. A common floating diffusion portion 46 in the central portion surrounded by the four photoelectric conversion portions 42 to 45 is disposed.

  Transfer gate electrodes 47, 48, 49, and 50 having a substantially triangular shape are formed between the respective corner portions of the four photoelectric conversion units 42 to 45 and the floating diffusion portion 46, and the corresponding transfer transistors Tr11, Tr12, Tr13, and Tr14 are formed. The transfer gate electrodes 47 to 50 are formed in a substantially triangular shape with the photoelectric conversion units 42 to 45 side as the bottom and the floating diffusion portion 46 side as the top, respectively.

  A common pixel transistor, that is, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4, is disposed on the lower side of the group of four photoelectric conversion units 42 to 45, for example, with respect to the four photoelectric conversion units 42 to 45. The reset transistor Tr2 includes a pair of source / drain regions 51 and 52 and a reset gate electrode 55 formed through a gate insulating film. The amplification transistor Tr3 includes a pair of source / drain regions 52 and 53 and an amplification gate electrode 56 formed through a gate insulating film. The selection transistor Tr4 includes a pair of source / drain regions 53 and 54 and a selection gate electrode 57 formed through a gate insulating film.

  FIG. 6 shows an enlarged detailed configuration of one readout portion in FIG. 4 corresponds to a cross-sectional view taken along the line AA in FIG.

  As shown in FIG. 4, the solid-state imaging device 41 according to the second embodiment is provided in the region of each unit pixel (each pixel constituting the shared pixel) of the first conductivity type, in this example, the p-type semiconductor substrate 61. Then, a photoelectric conversion portion 43, a floating diffusion portion (FD) 46 made up of an n-type semiconductor region of the first conductivity type, and a readout portion 63 made up of a transfer transistor Tr12 are formed.

  The transfer transistor Tr12 is configured by forming an n + gate electrode 48 on a substrate surface between the photoelectric conversion unit 43 and the floating diffusion unit 46 via a gate insulating film 71. In the transfer transistor Tr12, the photoelectric conversion unit 43 serves as a source region, and the floating diffusion unit 46 serves as a drain region. The gate insulating film 71 is formed of, for example, a silicon oxide film.

  An n + poly sidewall 74 is formed on the n + gate electrode 48 on the photoelectric conversion portion 43 side through an insulating film 73, for example, a silicon oxide film. An insulating sidewall 75 is formed on the n + gate electrode 48 on the floating diffusion portion 47 side. The insulating sidewall 75 has a two-layer structure in this example, and is formed of two layers, for example, a silicon oxide film 73 and a silicon nitride layer 76. The insulating sidewall 75 can be formed with a single layer structure or a multilayer structure of two or more layers.

  In the present embodiment, in particular, the photoelectric conversion unit 43 includes a first photodiode (PD1) 64 and a second photodiode (PD2) 65. The first photodiode 64 is formed of a buried photodiode having an n-type semiconductor region 66 of the second conductivity type and a p-type accumulation layer 67 on the surface thereof. The second photodiode 65 is formed of a photodiode having an n-type semiconductor region 68 of the second conductivity type and a region whose surface is hole-pinned by an n + poly sidewall 74.

  That is, the second photodiode 65 is formed of a photodiode whose surface has an electric field opposite to the signal charge excited by an electric field of a transfer gate electrode, which will be described later, or a poly sidewall.

  The first photodiode 64 is formed over a region where the photoelectric conversion unit 43 is formed. The second photodiode 65 is shallower than the first photodiode 64, has an impurity concentration higher than that of the first photodiode 64, and is formed in the vicinity of the n + gate electrode 48. That is, in the second photodiode 65, the n-type semiconductor region 68 is formed shallower than the n-type semiconductor region 66 of the first photodiode 64. Further, the n-type semiconductor region 68 has an impurity concentration set higher than the impurity concentration of the n-type semiconductor region 66 of the first photodiode 64 and is formed in the vicinity of the n + gate electrode 48.

  The p-type accumulation layer 67 of the first photodiode 64 is formed so as to extend to the n-type semiconductor region 68 of the second photodiode 65, but is not formed directly under the n + poly sidewall 74. The p-type accumulation layer 67 may be formed so as to slightly enter directly under the n + poly sidewall 74.

  In this example, the n-type semiconductor region 66 of the first photodiode 64 is formed so as to enter directly under the n + gate electrode 48 so as to partially overlap the n + gate electrode 48. Further, the n-type semiconductor region 68 of the second photodiode 65 exists in the n-type semiconductor region 66 of the first photodiode 64, and immediately below the n + gate electrode 48 so that a part thereof overlaps the n + gate electrode 48. It is formed by entering. The element isolation portion 77 is formed of a second conductivity type semiconductor layer, in this example, a p-type semiconductor layer.

  The silicon oxide film 73 on the n + poly sidewall 74 side is formed thinner than the silicon oxide film 73 of the insulating sidewall 75. In the illustrated example, the n + poly sidewall 74 is formed in a triangular shape inclined at 45 degrees, that is, a triangular shape having a taper angle θ1 of 45 degrees. The taper angle θ1 of the n + poly sidewall 74 is preferably 40 degrees to 50 degrees. The n + poly sidewall 74 may be formed in a round shape like the insulating sidewall 75.

  In the present embodiment, all of the read portions 63 are formed by self-alignment. That is, after the n + gate electrode 48 is formed, the n-type semiconductor region 66 of the first photodiode 64 is formed by ion implantation through the n + gate electrode 48 and the first photoresist mask. Further, the floating diffusion portion 46 is formed by ion implantation through the n + gate electrode 48 and the second photoresist mask. An n-type semiconductor region 68 of the second photodiode 65 is formed by ion implantation through the n + gate electrode 48 and the third photoresist mask. Further, after forming the n + poly sidewall 74 including the insulating sidewall 75 and the insulating film 73, the p-type accumulation layer of the first photodiode 64 is interposed through the n + poly sidewall 74 and the fourth photoresist mask. 67 is formed.

  According to the solid-state imaging device according to the second embodiment, the signal charge (electrons in this example) generated by photoelectric conversion by the first and second photodiodes 64 and 65 during the charge accumulation period has an impurity concentration. Accumulated in the n-type semiconductor region 68 of the high second photodiode 65. That is, signal charges are accumulated in a region near the n + gate electrode 48.

  At the time of reading out the signal charge, the signal charge is accumulated in the second photodiode 65 near the n + gate electrode 48 and in the shallow region, so that the potential of the second photodiode 65 is immediately increased when the read voltage is applied. Modulation is facilitated, and signal charges can be easily read out. Further, since there is no p-type accumulation layer on the surface of the second photodiode 65 and no potential barrier is generated immediately below the n + poly sidewall 74 at the potential of the n + poly sidewall 74, signal charges can be easily read out. That is, at the time of charge reading, a positive voltage is applied to the n + gate electrode 48 and the transfer transistor Tr12 is turned on. Even at this ON time, as in the first embodiment, the potential of the n + poly sidewall 74 is modulated by the coupling capacitance, and is modulated to a gentle gradient potential without the potential barrier immediately below the n + poly sidewall 74. The Therefore, in combination with the above-described event, the signal charge becomes easier to read. That is, the signal charge can be read at a low voltage, and the read characteristics are improved.

  The insulating film (for example, silicon oxide film) 73 on the n + poly sidewall 74 side is formed thinner than the silicon oxide film 73 of the insulating sidewall 75. As a result, the coupling capacitance between the n + gate electrode 48 and the n + poly sidewall 74 is increased, and the coupling is easily performed, and the potential modulation on the surface of the second photodiode 65 by the n + poly sidewall 74 is easily performed.

  The film thickness of the insulating film 73 on the n + poly sidewall 74 side is a parameter for controlling the effect of the n + poly sidewall such as the coupling capacitance and the potential modulation. Parameters that control the effect of the n + poly sidewall include the impurity concentration of the n + poly sidewall 74 and the overhang dimension of the insulating film 73 and the n + poly sidewall 74 to the photodiode (PD) side. Furthermore, the effect of the n + poly sidewall can be controlled by the interaction between the impurity profile in the Si substrate near the gate electrode of the transfer transistor and the n + poly sidewall.

  In the second embodiment, the saturation charge amount Qs can be increased by providing the second photodiode 65 having a high impurity concentration in the n-type semiconductor region 68. The solid-state imaging device according to the present embodiment has a configuration in which signal charges can be easily read although the saturation charge amount Qs is large.

In the charge accumulation period, a negative voltage is applied to the n + gate electrode 48. Since this negative voltage is also applied to the n + poly sidewall 74 due to the coupling capacitance, a hole h is induced on the surface of the n-type semiconductor region 68 of the second photodiode 65 immediately below the n + poly sidewall 74. That is, as shown in FIG. 7, an accumulation region is formed on the surface of the n-type semiconductor region 68 immediately below the n + poly sidewall 74 due to holes h induced by the electric field from the n + poly sidewall 74. The surface of the n-type semiconductor region 68 is in a hole pinning state. At the same time, the channel surface directly under the n + gate electrode 48 is also in the hole pinning state. Since the surface of the channel and the surface of the n-type semiconductor region 68 of the second photodiode 65 immediately below the n + poly sidewall 74 are hole-pinned, electrons that have spouted from the interface of the insulating film recombine with the holes h, and white spots are generated. Can be suppressed.
Since it has the structure which has the n + gate electrode 48 and the n + poly sidewall 74, there exists an effect similar to 1st Embodiment.

  Since the readout portion 63 including the transfer transistor Tr12 and the first and second photodiodes 64 and 65 are all formed by self-alignment, the readout portion 63 can be accurately formed even if the pixels are miniaturized. The solid-state imaging device of this embodiment can be manufactured with high accuracy.

  By making the n + poly sidewall 74 triangular, the following effects are obtained. After the n + poly sidewall 74 is formed, it is necessary to remove the n + poly sidewall where it is not necessary. For example, if the n + poly sidewall is left in the peripheral circuit, the transistor characteristics deteriorate, and therefore it is necessary to remove the n + poly sidewall. When an insulating sidewall is formed after the removal, the insulating sidewall is formed outside the n + poly sidewall at the place where the n + poly sidewall is left. Incomplete sidewalls are formed in unintended locations, and the shape causes control defects and characteristic variations.

  On the other hand, if the n + poly sidewall 74 has a triangular shape, the insulating sidewall does not have to be formed outside the n + sidewall 74, so that the shape can be controlled and characteristic fluctuations do not occur.

  However, if the shape can be controlled, an insulating sidewall may remain. In that case, the shape of the n + poly sidewall 74 may be other than a triangular shape. Also, ion implantation of the source / drain of the peripheral circuit is performed using the n + poly sidewall and the gate electrode as a mask, and then the unnecessary portion of the n + poly sidewall is removed to eliminate the insulating sidewall formation step. Is also possible.

  FIG. 8 to FIG. 10 show modifications of the second embodiment described above, that is, the third embodiment, the fourth embodiment, and the fifth embodiment.

  As shown in FIG. 8, the solid-state imaging device 81 according to the third embodiment includes a first photodiode (PD1) 64 and a second photodiode (PD2) 65, as in the second embodiment. The photoelectric conversion unit 43, the floating diffusion unit 46, and the transfer transistor Tr12 constitute a reading portion 82.

In the present embodiment, the second photodiode 65 is formed immediately below the n + poly sidewall 74. That is, the n-type semiconductor region 68 of the second photodiode 65 is formed immediately below the n + poly sidewall 74. The p-type accumulation layer 67 of the first photodiode 64 is configured not to overlap the n-type semiconductor region 68 of the second photodiode 65.
Since the other configuration is the same as that of the second embodiment in FIG. 4, portions corresponding to those in FIG.

  According to the solid-state imaging device 81 according to the third embodiment, since the second photodiode 65 is formed to have a narrower region than the second embodiment, the accumulated charge is closer to the n + gate electrode 48 and the signal It makes it easy to read out the charge. In addition, the same effects as described in the second embodiment can be obtained.

  As shown in FIG. 9, the solid-state imaging device 83 according to the fourth embodiment includes a first photodiode (PD1) 64 and a second photodiode (PD2) 65, as in the second embodiment. The photoelectric conversion unit 43, the floating diffusion unit 46, and the transfer transistor Tr12 constitute a readout portion 84.

In this embodiment, a part of the n-type semiconductor region 68 of the second photodiode 65 is formed so as to extend beyond the n-type semiconductor region 66 of the first photodiode 64 to the n + gate electrode 48 side. Is done. The n-type semiconductor region 68 can be formed by, for example, oblique ion implantation. The other part of the n-type semiconductor region 68 of the second photodiode 65 is formed in the n-type semiconductor region 66 of the first photodiode 64. The p-type accumulation layer 67 of the first photodiode 64 is formed up to just below the n + poly sidewall 74. The p-type accumulation layer 67 may be configured not to be formed directly under the n + poly sidewall 74.
Since the other configuration is the same as that of the second embodiment in FIG. 4, portions corresponding to those in FIG.

  According to the solid-state imaging device 83 according to the fourth embodiment, the second photodiode 65 is formed so as to partially extend from the first photodiode 64 to the n + gate electrode 48 side. With this configuration, the second photodiode 65 is brought closer to the floating diffusion portion 46, and the region modulated by the n + gate electrode 48 of the second photodiode 65 is increased, thereby making it easier to read the signal charge. In addition, the same effects as described in the second embodiment can be obtained.

  As shown in FIG. 10, the solid-state imaging device 85 according to the fifth embodiment includes a first photodiode (PD1) 64 and a second photodiode (PD2) 65, as in the second embodiment. The photoelectric conversion unit 43, the floating diffusion unit 46, and the transfer transistor Tr12 constitute a readout portion 86.

In this embodiment, the first photodiode 64 and the second photodiode 65 are formed in the same positional relationship as in the second embodiment of FIG. 4 described above, and the second photodiode just below the n + poly sidewall 74 is formed. A p-type low impurity concentration region 87 is formed on the surface of the photodiode 65. That is, a p-type low impurity concentration region 87 having a lower concentration than the p-type accumulation layer 67 of the first photodiode 64 is formed on the surface of the n-type semiconductor region 68 immediately below the n + poly sidewall 74 of the second photodiode 65. A so-called low concentration p-accumulation layer is formed.
Since the other configuration is the same as that of the second embodiment in FIG. 4, portions corresponding to those in FIG.

  According to the solid-state imaging device 85 according to the fifth embodiment, since the p-type semiconductor region 87 serving as the p-accumulation layer is formed, holes on the surface of the second photodiode 65 due to the n + poly sidewall 74 are formed. Combined with induction, the generation of white spots can be further suppressed. In addition, the same effects as those of the second embodiment described above can be obtained, such as the ease of reading signal charges and the amount of saturation charge being increased.

  In the solid-state imaging device having the photoelectric conversion unit 43 including the first photodiode 64 and the second photodiode 65 described above, the configuration shown in FIGS. 11 to 13 is adopted as the configuration of the gate electrode and the sidewall of the transfer transistor. obtain.

  In the example of FIG. 11, the transfer gate electrode of the transfer transistor is formed by the n + gate electrode 72 as described in FIG. 4. The side wall on the photoelectric conversion unit 43 side is formed of an n + poly sidewall 74 including an insulating film (for example, a silicon oxide film) 73. The sidewall on the floating diffusion portion 46 side is formed of two layers by an insulating sidewall 75, in this example, a silicon oxide film 73 and a silicon nitride film 76.

  In the example of FIG. 12, the transfer gate electrode of the transfer transistor is formed by the p + gate electrode 88. The side wall on the photoelectric conversion unit 43 side is formed by a p + poly side wall 89 including an insulating film (for example, a silicon oxide film) 73. The sidewall on the floating diffusion portion 46 side is formed of two layers by an insulating sidewall 75, in this example, a silicon oxide film 73 and a silicon nitride film 76. The side wall on the photoelectric conversion unit 43 side can also be formed by an n + poly side wall 89 including an insulating film (for example, a silicon oxide film) 73.

  In the case of the configuration having the p + gate electrode 88 and the p + poly sidewall 89 shown in FIG. 12, even if the gate voltage is set to 0 V due to the work function difference from n +, the portion immediately below the p + poly sidewall 89 is in a pinned state. Can do.

In the example of FIG. 13, the transfer gate electrode 90 of the transfer transistor is formed of a gate electrode of a required conductivity type by a p + gate electrode or an n + gate electrode. Both the side wall on the photoelectric conversion portion 43 side and the side wall on the floating diffusion portion side are formed in two layers by an insulating side wall 75, in this example, a silicon oxide film 73 and a silicon nitride film 76.
In this example, the surface of the second photodiode 65 is in a hole pinning state by the electric field generated by the transfer gate electrode 90.

  Furthermore, although not shown in the drawings, the gate electrode and the sidewall of the transfer transistor may be configured such that the insulating sidewall 75 on the floating diffusion portion 46 side is eliminated in the configurations of FIGS.

  The configuration of the photoelectric conversion unit 43 including the first and second photodiodes 64 and 65 may be any of the configurations shown in FIGS.

  In the above-described embodiment, the signal charge is configured as an electron. However, the signal charge may be configured as a hole. In this case, the conductivity type of each semiconductor region is the opposite conductivity type from the above example.

  The solid-state imaging device of the present invention is not limited to application to an area image sensor in which pixels are two-dimensionally arranged on a matrix, and can be similarly applied to a linear image sensor in which pixels are one-dimensionally arranged on a straight line. It is.

The solid-state imaging device according to the present invention can be applied to electronic devices such as a camera equipped with a solid-state imaging device, a portable device with a camera, and other devices equipped with a solid-state imaging device.
FIG. 14 shows an embodiment applied to a camera as an example of the electronic apparatus of the present invention. The camera 95 according to the present embodiment includes an optical system (optical lens) 96, a solid-state imaging device 97, and a signal processing circuit 98. As the solid-state imaging device 97, any one solid-state imaging device in each of the above-described embodiments is applied. The optical system 96 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 97. As a result, signal charges are accumulated in the photoelectric conversion element of the solid-state imaging device 97 for a certain period. The signal processing circuit 98 performs various signal processing on the output signal of the solid-state imaging device 97 and outputs it. The camera 95 according to the present embodiment includes a camera module in which an optical system 96, a solid-state imaging device 97, and a signal processing circuit 98 are modularized.

The present invention can constitute a camera-equipped mobile device represented by, for example, a mobile phone provided with the camera of FIG. 14 or a camera module.
Furthermore, the configuration of FIG. 14 can be configured as a module having an imaging function in which the optical system 96, the solid-state imaging device 97, and the signal processing circuit 98 are modularized, a so-called imaging function module. The present invention can constitute an electronic apparatus provided with such an imaging function module.

  According to the electronic apparatus according to the present embodiment, the readout characteristics in the solid-state imaging device are excellent, the pixel characteristics are excellent, and low-voltage readout is possible. In addition, it is possible to provide a high-quality electronic device that can suppress generation of white spots or increase the saturation charge amount.

  21..Solid-state imaging device, 22..Semiconductor substrate, 23..Photoelectric conversion unit, 24..Floating diffusion unit, 25..Reading portion, Tr1..Transfer transistor, 26..n-type semiconductor region ..P-type accumulation layer, 31..gate insulating film, 32..transfer gate electrode (n + gate electrode), 33..insulating film (silicon oxide film), 34..n + poly sidewall, 25..insulating Side wall, 36 .. Silicon nitride layer, h .. Hall, 41 .. Solid state imaging device, 46 .. Floating diffusion part, 47 .. Photoelectric conversion part, 61 .. Semiconductor substrate, 63 .. Readout part, 64. .. First photodiode, 65 .. Second photodiode, 66, 68... N-type semiconductor region, 67... P-type accumulation layer, 71 · Gate insulation film, 72 ·· n + gate electrode, 73 · · Insulation film (silicon oxide film), 74 · · n + poly sidewall, 75 · · insulation sidewall, 76 · · silicon nitride layer, 77 · · element isolation Part

Claims (4)

A photoelectric conversion unit having a second conductivity type semiconductor region and a first conductivity type accumulation region on the surface thereof;
Floating diffusion part,
a transfer gate electrode made of an n-type semiconductor;
A sidewall of an n-type semiconductor formed through an insulating film on the photoelectric conversion part side of the transfer gate electrode;
A sidewall of an insulating layer formed on the floating diffusion portion side of the transfer gate electrode;
The accumulation region is not formed directly under the sidewall, or part of it overlaps the sidewall,
A voltage of the transfer gate electrode is applied to the side wall on the photoelectric conversion unit side through a coupling capacitor,
During charge reading, a read voltage is applied to the transfer gate electrode,
A solid-state imaging device in which a voltage that induces a charge opposite to a signal charge is applied to the transfer gate electrode immediately below the side wall on the photoelectric conversion unit side during charge accumulation. A semiconductor region of the photoelectric conversion portion and the floating diffusion portion are formed of an n-type semiconductor region;
The accumulation region is formed of a p-type semiconductor region;
During charge reading, a positive voltage is applied to the transfer gate electrode,
The solid-state imaging device according to claim 1, wherein a negative voltage is applied to the transfer gate electrode during charge accumulation. A solid-state imaging device;
An optical system for guiding incident light to the photoelectric conversion unit of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device;
The solid-state imaging device
A photoelectric conversion unit having a second conductivity type semiconductor region and a first conductivity type accumulation region on the surface thereof;
Floating diffusion part,
a transfer gate electrode made of an n-type semiconductor;
A sidewall of an n-type semiconductor formed through an insulating film on the photoelectric conversion part side of the transfer gate electrode;
A sidewall of an insulating layer formed on the floating diffusion portion side of the transfer gate electrode;
The accumulation region is not formed directly under the sidewall, or part of it overlaps the sidewall,
A voltage of the transfer gate electrode is applied to the side wall on the photoelectric conversion unit side through a coupling capacitor,
During charge reading, a read voltage is applied to the transfer gate electrode,
An electronic device in which a voltage that induces a charge opposite to a signal charge is applied to the transfer gate electrode immediately below the side wall on the photoelectric conversion unit side during charge accumulation. A semiconductor region of the photoelectric conversion portion and the floating diffusion portion are formed of an n-type semiconductor region;
The accumulation region is formed of a p-type semiconductor region;
During charge reading, a positive voltage is applied to the transfer gate electrode,
The electronic device according to claim 3, wherein a negative voltage is applied to the transfer gate electrode during charge accumulation.

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