JPH11284167A - Semiconductor device, its manufacture, and solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cancel the stress of a side wall spacer required in a process for LDD structure formation when an MOS transistor of LDD structure is formed. SOLUTION: On a semiconductor substrate(Sub) comprising a first conductivity, a second conductivity region for a source region and drain region of polarity different from the semiconductor substrate is formed, a gate electrode G is formed in the region bridging the second conductive region for the source region on the semiconductor substrate and that for the drain region, a side wall spacer(Sws) is formed beside the gate electrode G, the impurity or second conductivity is injected in the second conductivity region to form a high-concentration impurity region in the second conductivity region, and a low-concentration impurity region extending from the high-concentration impurity region toward a channel region is formed under the Sws, which constitutes an MOS transistor of LDD structure for a semiconductor device. Here, the Sws is formed of polycrystal silicon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a MOS solid-state imaging device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A MOS type solid-state imaging device (MOS image sensor) can be miniaturized and can be driven by a single power supply. In recent years, it has attracted attention because of its advantages such as being able to constitute a chip as one integrated circuit.

[0003] A number of techniques have been proposed for an amplifying MOS image sensor having an amplifying function inside a pixel. Such an amplifying MOS sensor requires an increase in the number of pixels and an image size in order to respond to the pursuit of high image quality. Is expected to be suitable for the reduction of the pixel size by the reduction of the pixel size.

[0004] Amplifying MOS image sensors are particularly suitable for C
It is highly expected that power consumption is lower than that of a CD image sensor, and integration with other peripheral circuits using the same CMOS process as the sensor portion is easy.

FIG. 9 shows an amplification type MO according to the prior art.
1 shows a schematic device structure of an S image sensor. That is, the drawing is an enlarged plan view of a cell portion forming each pixel. As shown in the drawing, the cells forming each pixel are formed on the same semiconductor substrate Sub by the photoelectric conversion element PD and the transistors Tr1, Tr2, Tr2. And are arranged side by side. The signal charge generated by the photoelectric conversion by the photoelectric conversion element PD gives a potential to the transistor Tr1 constituting the signal charge storage unit, and modulates the amplifying transistor Tr2 inside the pixel by the potential to have an amplifying function inside the pixel. I'm making it. Then, the amplification transistor Tr2
The signal amplified in is read out via the horizontal address line Lh, and becomes an image signal at the pixel. A plurality of cells are arranged in a matrix (two-dimensional matrix).

However, this type of image sensor has the following problems. In other words, one technical trend that increases the added value of this type of amplifying MOS image sensor is to increase the number of pixels to obtain high definition image quality, and thus to reduce the size of pixels.

However, in order to realize a high definition of the amplification type MOS image sensor, not only miniaturization of a photodiode as a photoelectric conversion element, that is, reduction of a photodiode constituting a pixel, but also peripheral circuits around the pixel are required. Unless the MOS transistor itself is also made small, high-resolution amplification type MOS image sensors cannot be realized. Regarding the MOS transistor, even if the size is reduced, in order to obtain the same characteristics as the transistor of the original size, an LDD (lightly doped drain) structure for lowering the impurity distribution in the drain region has a MOS structure.
It is known that it is necessary for transistors.

FIG. 10A shows the structure of a conventional MOS transistor Tr and photodiode PD which do not have the LDD structure employed before the advance of the high definition. FIG. MOS transistor Tr and photodiode P
The structure of D is shown in FIG.

That is, in the former, an n + region forming the photodiode PD is formed in the p-type semiconductor substrate Sub, and the n + region is slightly separated from the n + region of the photodiode PD.
A region is formed to serve as the drain D of the MOS transistor Tr, the n + layer of the photodiode PD serves as the source S, and a gate electrode G is formed therebetween through an insulating layer.
An S transistor Tr is obtained. The charge generated by the photodiode PD flows to the drain S side through the channel region below the gate electrode G. By miniaturizing the pixel, the charge is reduced to a lower region between the source S and the drain D, that is, the semiconductor. Leakage occurs through a portion closer to the substrate Sub side. To suppress this, an n- region having a low n-type impurity concentration is formed outside each n + region. This is the structure shown in FIG.

However, even if this structure is applied to an amplification type MOS image sensor in the case of miniaturization, it has no effect on improving characteristics and suppressing leakage. In the latter case, p
Constituting the photodiode PD on the semiconductor substrate Sub
+ Region is formed, and an n + region is formed slightly apart from the n + region of the photodiode PD to serve as the drain D of the MOS transistor Tr. The n + layer of the photodiode PD serves as the source S. Then, a gate electrode G is formed, and a MOS transistor Tr is obtained. The electric charge generated by the photodiode PD flows to the drain S side through a channel region below the gate electrode G by applying a voltage to the gate electrode G of the MOS transistor. Leaks through a lower region between the source S and the drain D irrespective of the control by the gate electrode G, that is, a portion closer to the semiconductor substrate Sub side. An n- region having a low n-type impurity concentration is formed outside the + region and below the gate electrode G. This n− region is first formed in the semiconductor substrate Sub, and a mask is prepared for forming an n + region by implanting n-type impurities later. This is a wall spacer made of SiN beside the gate electrode G. is there. An n + region is formed by ion-implanting an n-type impurity from above the spacer, and as a result, an n- region is formed so as to protrude toward the upper channel region opposing portion of the n + region.
This is the LDD structure shown in FIG.

According to this LDD structure, the electric charge generated in the photodiode PD passes through the channel region under the gate electrode G from the n − region on the photodiode PD side by applying a voltage to the gate electrode G, and the charge on the drain D side. -It flows into the n + region of the drain D and further flows into the n + region of the drain D, so that a leak phenomenon that directly passes through the lower part of the n + region constituting these between the source S and the drain D does not occur.

Therefore, this structure can be applied to an amplification type MOS image sensor in the case of miniaturization, and the effect of improving the characteristics and suppressing leakage can be expected. Next, steps for fabricating a conventional LDD structure will be described with reference to a simple process flow shown in FIG. FIG. 11 (a)
As shown in FIG. 11, after forming a gate electrode, ion implantation for forming an n @-layer is performed, and then, as shown in FIG.
An N insulating film is deposited. This deposited film thickness changes with the thickness of the gate electrode, and is generally set to be equal to or larger than the thickness of the gate electrode.

Thereafter, when this insulating film is etched by anisotropic etching using REI, the insulating film remains only on the side surface of the gate electrode (FIG. 11C). This S
The iN insulating film serves as a sidewall spacer for forming an offset region. After the formation of the sidewall spacers, as shown in FIG. 11D, an n @ + layer is formed by ion implantation as in the case of the conventional MOS transistor. In the case of the LDD structure, n-
Phosphorus (P) for layer formation, Critical (As) for n + layer formation
Is usually used, but the same kind of element may be used.

In this manner, a MOS transistor having an LDD structure is formed.
Attempting to adopt it in an amplification type MOS image sensor having a D-structure with a high definition leads to a serious problem.

That is, in order to adopt the LDD structure, sidewall spacers are inevitably formed in the process, and since the sidewall spacers are made of SiN, the difference in thermal expansion coefficient from the Si semiconductor substrate causes This will give stress to the Si semiconductor substrate.
In addition, since the MOS image sensor has a very fine cell, an excessive stress is applied to the fine element, and many fatal white flaws such as cracks occur in the image sensor. There was a problem.

If the LDD structure cannot be adopted, it is inevitable that the leak current of the photodiode PD will increase due to the small size of the element, and this will lower the dynamic range.

[0017]

As described above, the conventional M
In an OS-type solid-state imaging device, a photodiode and an MO
Although the S transistor is arranged in the cell, the MOS transistor preferably employs the LDD structure in order to exhibit the original performance without being affected by miniaturization. However, although an adjacent circuit configuration is adopted, the LDD structure is formed of SiN (silicon nitride) for the LDD structure in order to suppress the leakage of the photodiode. Therefore, the coefficient of thermal expansion of the semiconductor substrate Sub is greatly different. In the case of miniaturization, there has been a problem that many fatal white flaws occur for the image sensor, for example, cracks occur everywhere due to generation of thermal stress of the material.

Therefore, there is a demand for the development of a technology capable of improving this and adopting the LDD structure to promote further miniaturization of the MOS image sensor.
Therefore, an object of the present invention is to adopt the LDD structure to a high-resolution MOS solid-state imaging device,
It is an object of the present invention to provide a high-quality and high-definition MOS solid-state imaging device having a wide dynamic range and having no fear of white scratches and a method of manufacturing the same.

[0019]

In order to achieve the above object, the present invention is configured as follows. That is, although the present invention is firstly a MOS transistor having an LDD structure,
The material of the gate sidewall spacer was changed from SiN (silicon nitride) to Poly-Si (polycrystalline silicon).

Secondly, a MOS transistor having an LDD structure, which has no sidewall spacer remaining on the gate electrode, is employed.
Also, in connection with the above, the MO of the portion related to the pixel is
In the S transistor, a MOS transistor configuration in which a sidewall spacer does not remain at the gate was employed.

According to the present invention having the above-described structure, the generation of stress due to the sidewall spacer can be suppressed by using Poly-Si for the sidewall spacer. Further, in the case where the structure is such that the sidewall spacer is not provided in the gate electrode of the transistor, there is an advantage that stress due to the sidewall spacer is not generated in the photodiode portion.

The reduction or elimination of these stresses leads to the elimination of microdefects in the photodiode because the limit stress for the generation of silicon dislocations in the photodiode is reduced by ion implantation. In this regard, in the CCD imaging device which is a well-known solid-state imaging device, the photodiode portion is formed under the thick oxide film, and thus is not affected by the above-described stress.

However, in the case of the amplification type MOS sensor, the MO
Since the S-transistor exists adjacent to the photodiode and the thickness of the oxide film on the photodiode is about the same as the oxide film of the gate, the amplification type MOS image sensor is easily affected by the stress due to the sidewall spacer.

In this regard, the above-mentioned problems and the present invention for solving the problems can be said to be unique to the amplification type MOS image sensor. The reduction or elimination of minute defects in the photodiode PD described above is effective in suppressing the leakage current of the photodiode PD to a low level, thereby achieving a high dynamic range as an image. Further, the use of the means for eliminating the sidewall leads to a reduction in the parasitic capacitance of the gate, so that there is a merit that the sensitivity is increased.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a unit cell of an amplification type solid-state imaging device (amplification type MOS image sensor) according to an exemplary embodiment of the present invention. FIG. 1 shows a configuration of three unit cells, which is a MOS solid-state imaging device having one pixel and one unit cell. Although only three unit cells are shown in the figure, a large number of unit cells of the MOS type solid-state imaging device of the present embodiment, for example, those of the order of tens or hundreds of thousands It is assumed that they are arranged in an orderly manner.

In FIG. 1, 1 is a signal line, 10a, 10a
b and 10c are unit cells, respectively. As shown in FIG. 1, for example, the unit cell 10a includes a photodiode 5 for converting light into a charge, a read transistor 8 for reading the charge stored in the photodiode 5 to a detection unit (not shown), and a line for reading a signal charge. It comprises an address capacitor 9 to be selected, an amplifying transistor 4 for amplifying the detection signal of the photodiode 5 and outputting it to the signal line 1, and a reset transistor 6 for resetting the electric charge accumulated in the detecting section.

The transistors 4, 6, and 8 shown here have M
It is composed of an OS transistor. Although the unit cell 10a has been described, the other unit cells 10b, 10b
The same configuration is adopted for c.

In the present embodiment, the MOS transistors 4, 6, and 8 have the LDD structure, and the gate electrode has the sidewall spacer Sws formed therein.
Po is used as a material for the side wall spacer of the gate electrode.
ly-Si (polycrystalline silicon) was used. That is, a sidewall spacer made of Poly-Si was used instead of the conventional sidewall spacer made of SiN.

Poly-Si is composed of unit cells 10a, 10b, 1
0c... Are substantially the same as the thermal expansion coefficient of the Si semiconductor substrate, and no stress is applied to the semiconductor substrate by the sidewall spacer Sws even if heat is applied or cooled in the manufacturing process of the MOS image sensor.

Next, a process flow for fabricating an MOS transistor having an LDD structure in which a Poly-Si sidewall spacer Sws is formed on a gate electrode will be described with reference to FIG.

For example, after a gate electrode G is formed on a first conductive semiconductor substrate made of Si, for example, a p-type semiconductor substrate Sub made of Si, n− as a second conductive region serving as a source S and a drain D is formed. Ion implantation for forming a layer is performed (FIG. 2A), and thereafter, the semiconductor substrate Sub
A Poly-Si film of about 200 to 500 [nm] is deposited thereon (FIG. 2B).

Then, when this Poly-Si film is etched by anisotropic etching by REI, the POLY-Si film remains only on the side surface of the gate electrode G (FIG. 2).
(C)). This remaining Poly-Si film becomes a sidewall spacer Sws for forming an offset region.
After the formation of the sidewall spacer Sws, an n @ + layer is formed by ion implantation in the same manner as in the conventional structure MOS transistor (FIG. 2D).

In the case of this LDD structure as well, phosphorus is usually used for forming the n− layer and ion implantation of criterion is usually used for forming the n + layer, but the same kind of element may be used. The amplifying MOS of the present invention manufactured by the above process
3 and 4 show a structure including the photodiode 5 and the readout transistor 8 of the image sensor. FIG. 3 shows an example in which an LDD structure exists below the read transistor (Tr) 8, and FIG.
This is an example in the case where no LDD structure exists below the reference numeral 8. The extended LDD structure of the photodiode is appropriately formed in relation to the drive voltage of the photodiode.

Next, FIG. 5 shows a simple process flow for fabricating a MOS transistor in which the sidewall spacer Sws does not remain on the gate electrode G. After forming the gate electrode G as shown in FIG. 5A, ion implantation for forming an n @-layer is performed, and thereafter, as shown in FIG. 500 [n
[m] is deposited.

Then, as shown in FIG. 5C, when this Poly-Si film is etched by anisotropic etching by reactive ion etching (RIE), the Poly-Si film is formed only on the side surface of the gate electrode G. Remains. Then, this P0LY-Si film becomes a sidewall spacer Sws for forming an offset region.

After the formation of the sidewall spacer Sws, an n + layer is formed by ion implantation in the same manner as in the conventional MOS transistor (FIG. 5D). Thereafter, Poly-Si in the sidewall space Sws is removed by using a CDE (Chemical Dry Etching) method (FIG. 5E). The presence of the step of FIG. 5E is different from the previous step.

In the case of this LDD structure, phosphorus is usually used for forming the n− layer and ion implantation of criterion is usually used for forming the n + layer. However, the same kind of element may be used. FIG. 6 shows a structure including a photodiode and a readout transistor of the amplification type MOS sensor of the present invention manufactured by the above-described process. FIG. 6 shows that the LDD structure exists below the read transistor, but the LDD structure in which the n + layer of the photodiode PD extends toward the channel region of the gate electrode G is appropriately formed in relation to the drive voltage of the photodiode PD. Is done. Further, the effects of the present invention can be obtained even on n patterns in a unit cell.

An embodiment will be described with reference to the unit cell shown in FIG. As shown in FIG. 1, the gate width of the reset transistor 6a is small within one pixel. In this case, in order to make the transistor characteristics of the reset transistor 6 the same as those of the transistors in the other unit cells, only the reset transistor 6 needs an LDD structure, and the gate electrode G of the transistor 6 has a sidewall spacer. Sws is required.

The steps for realizing the cell having such a structure will be described below. After the gate electrode G is formed, ion implantation for forming an n @-layer is performed.
SiN film or Poly-Si with a thickness of about 00 [nm]
Deposit the film. Then, the resist is left in the hatched area in the drawing of FIG.
-Remove Si.

Next, the resist is removed. And
When this insulating film is etched by anisotropic etching by RIE, the SiN or Poly-Si film remains only on the side surface of the gate electrode of the reset transistor 6a. This SiN or Poly-Si film becomes a sidewall spacer for forming an offset region.

After the formation of the sidewall spacer,
An n @ + layer is formed by ion implantation in the same manner as in a conventional MOS transistor. In the case of this LDD structure as well, phosphorus ion implantation is usually used for forming the n − layer and critical ion implantation is usually used for forming the n + layer, but the same kind of element may be used.

From the above steps, a MOS transistor having a sidewall in only a part of the cell as shown in FIG. 7 becomes possible. Although the present embodiment is limited to the reset transistor, the effects of the present invention can be obtained within the scope of application of the present embodiment also in the configuration of a MOS transistor in which only the other transistors in the cell have sidewalls.

Next, the effects of the present invention can be obtained even on a pattern in a chip. An embodiment will be described using the layout on the chip 81 shown in FIG. In FIG. 8, 8
2 is a pixel section in which a number of pixels are arranged in a matrix, 8
Reference numeral 3 denotes a driving unit for driving the pixel unit 82, and reference numeral 84 denotes a driving unit 8
3 is a signal processing unit for controlling the signal processing of the pixel unit 82 and processing the signal extracted from the pixel unit 82.

As shown in FIG. 8, it is necessary to use a highly reliable MOS transistor as a circuit constituting the driving section 83 and the signal processing section 84 in some cases. In this case, a transistor used for a circuit forming the driving unit 83 or the signal processing unit 84 needs to have an LDD structure capable of suppressing leakage, and a gate electrode G of this transistor needs a sidewall. The steps for realizing such a cell are described below.

After the gate electrode G is formed on the semiconductor substrate, ion implantation is performed to form an n @-layer.
A SiN film or a Poly-Si film of about 500 [nm] is deposited. Then, in FIG. 7, a resist pattern is formed with the resist left in the hatched area, and the resist pattern is used as a mask to remove other portions using Poly-Electrode (CDE).
Remove Si.

Next, the resist is removed. And
This insulating film (S) is anisotropically etched by RIE.
When the iN film or the Poly-Si film is etched, the SiN film or the PoN
The ly-Si film remains.

This SiN film or Poly-Si film serves as a sidewall spacer for forming an offset region. After the formation of the sidewall spacers, an n @ + layer is formed by ion implantation in the same manner as in the conventional structure MOS transistor to obtain an LDD structure.

In the case of this LDD structure as well, phosphorus is usually used for forming the n− layer and ion implantation of criterion is usually used for forming the n + layer. However, the same kind of element may be used. From the above steps, only a part of the chip as shown in FIG.
It becomes possible to configure a MOS transistor having a sidewall. Further, in the present embodiment, the circuits are limited to those constituting the driving section and the signal processing section. However, the present invention is also applicable to the configuration of a MOS transistor having a sidewall only in the other transistors in the chip within the scope of application of the present embodiment. The effects of the invention can be obtained.

As described above, the present invention relates to an LD of a MOS transistor.
Poly-Si (polycrystalline silicon) is used instead of conventional SiN for the sidewall spacer required to obtain the D structure.
It is made to form by. And this Po
Since the expansion coefficient of the material of the ly-Si side wall spacer is almost the same as the expansion coefficient of the Si semiconductor substrate forming the element, the side wall spacer beside the gate electrode of the MOS transistor formed on the Si semiconductor substrate is used. Since no expansion and contraction due to heat change is the same as that of the semiconductor substrate, no stress is applied.

Further, after the formation of the LDD structure, unnecessary sidewall spacers were removed from the gate electrode of the MOS transistor having the LDD structure by a removing step, so that there was no sidewall spacer.

In this case, since there is no sidewall spacer, there is an advantage that no stress is generated by the sidewall spacer in the photodiode portion. In other words, the sidewall spacer is made of Poly-Si to suppress the generation of stress due to the sidewall spacer, or the gate electrode of the transistor has no sidewall spacer, so that the sidewall in the photodiode portion is According to the present invention, which has a structure in which no stress is generated by the spacer, the reduction or elimination of this stress lowers the critical stress for silicon dislocation generation in the photodiode portion at the time of ion implantation. Eliminate the occurrence of

In this respect, in the CCD imaging device which is a well-known solid-state image pickup device, the photodiode portion is formed under the thick oxide film, and thus is not affected by the above-mentioned stress. But,
In the case of an amplification type MOS image sensor, a MOS transistor exists adjacent to a photodiode, and the thickness of an oxide film on the photodiode is about the same as that of a gate. Therefore, the amplification type MOS image sensor is easily affected by stress due to the sidewall spacer.

In this respect, the above-mentioned problems and the method of the present invention for solving the problems can be said to be unique to the amplification type MOS image sensor. The reduction or elimination of minute defects in the photodiode PD described above is effective in suppressing the leakage current of the photodiode PD to a low level, thereby achieving a high dynamic range as an image. Also,
Furthermore, the use of the means for eliminating the sidewall leads to a reduction in the parasitic capacitance of the gate, so that there is an advantage that the sensitivity is increased.

Therefore, according to the present invention, the LDD structure can be employed in a high-definition MOS type solid-state image pickup device, and therefore, there is no fear of white flaws. Thus, a high-quality and high-definition MOS solid-state imaging device that can secure a wide dynamic range can be obtained.

[0055]

As described above in detail, according to the present invention, the LDD structure can be employed in a high-resolution MOS solid-state image pickup device, and therefore, there is no fear of white scratches.
Since the DD structure can be used, there is little leakage, so that a high-quality, high-definition MOS solid-state imaging device with a wide dynamic range can be provided.

[Brief description of the drawings]

FIG. 1 is a view for explaining the present invention, and is a plan view showing a main part structure as one specific example of an image sensor of the present invention.

FIG. 2 is a view for explaining the present invention, showing a process flow of manufacturing an LDD structure as a specific example in the image sensor of the present invention.

FIG. 3 is a diagram for explaining the present invention, and is a cross-sectional view showing a structure example of a photodiode and a MOS transistor portion connected to the photodiode as a specific example in the image sensor of the present invention.

FIG. 4 is a diagram for explaining the present invention, and is a cross-sectional view showing an example of the structure of a photodiode and a MOS transistor portion connected to the photodiode as a specific example in the image sensor of the present invention.

FIG. 5 is a view for explaining the present invention, showing a process flow of manufacturing an LDD structure as a specific example in the image sensor of the present invention.

FIG. 6 is a view for explaining the present invention, and is a cross-sectional view showing a structural example of a photodiode as a specific example in the image sensor of the present invention and a MOS transistor portion connected thereto.

FIG. 7 is a diagram illustrating the present invention.

FIG. 8 is a diagram for explaining another example of the present invention.

FIG. 9 is a plan view showing a structural example of an amplification type MOS image sensor.

FIG. 10 is a cross-sectional view showing a structure example of a photodiode as a conventional example and a MOS transistor portion connected to the photodiode.

FIG. 11 illustrates an exemplary LDD structure fabrication process flow.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Signal line 4 ... Amplification transistor 5, PD ... Photodiode 6 ... Reset transistor 8 ... Readout transistor 9 ... Address capacity 10a, 10b, 10c ... Unit cell Sws ... Side wall spacer G ... Gate electrode S ... Source D ... Drain

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Nobuo Nakamura, No. 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba R & D Center (72) Inventor Tetsuya Yamaguchi Toshiba Komukai, Kochi-ku, Kawasaki-shi, Kanagawa (72) Inventor Hidetoshi Nozaki 1 Tokoba-Toshiba-cho, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa

Claims (4)

[Claims] A second conductive region for a source region and a drain region having a polarity different from that of the semiconductor substrate on a semiconductor substrate having a first conductivity; and a second conductive region for the source region on the semiconductor substrate. A gate electrode is formed in a region extending between the second conductive region and the second conductive region for the drain region, and a sidewall spacer is formed beside the gate electrode to remove the second conductive impurity. By implanting into the second conductive region, a high-concentration impurity region was formed in the second conductive region, and a low-concentration impurity region extending from the high-concentration impurity region toward the channel region was formed below the sidewall spacer. A semiconductor device comprising a MOS transistor having an LDD structure, wherein the sidewall spacer is formed of polycrystalline silicon. . 2. A semiconductor device having a first conductivity, wherein a second conductivity region for a source region and a drain region having a polarity different from that of the semiconductor substrate is formed, and the second conductivity region for the source region on the semiconductor substrate is formed. A gate electrode is formed in a region extending between the second conductive region and the second conductive region for the drain region, and a sidewall spacer is formed beside the gate electrode to remove the second conductive impurity. By implanting into the second conductive region, a high-concentration impurity region was formed in the second conductive region, and a low-concentration impurity region extending from the high-concentration impurity region toward the channel region was formed below the sidewall spacer. In a semiconductor device having a MOS transistor having an LDD structure, the sidewall spacer is formed of polycrystalline silicon and a second conductive impurity is formed. Is implanted into the second conductive region to form a high-concentration region. 3. A second conductive region for a source region and a drain region having a polarity different from that of the semiconductor substrate is formed on a semiconductor substrate having a first conductivity, and a second conductive region for the source region on the semiconductor substrate is formed. A gate electrode is formed in a region extending between the second conductive region and the second conductive region for the drain region, and a sidewall spacer is formed beside the gate electrode to remove the second conductive impurity. By implanting into the second conductive region, a high-concentration impurity region was formed in the second conductive region, and a low-concentration impurity region extending from the high-concentration impurity region toward the channel region was formed below the sidewall spacer. In a semiconductor device having a MOS transistor having an LDD structure, the sidewall spacer is formed of polycrystalline silicon and a second conductive impurity is formed. Is implanted into the second conductive region to form a high-concentration region, and then the sidewall spacer is removed. 4. An imaging region in which unit cells each including a photoelectric conversion unit formed by a photodiode and a signal scanning circuit are arranged in a two-dimensional matrix on a semiconductor substrate, and a signal line for reading a signal from each cell in the imaging region. A solid-state imaging device which is arranged in a region different from the imaging region and forms a peripheral circuit at least partially constituted by a MOS transistor, wherein a unit cell of the imaging region includes a photodiode forming a photoelectric conversion unit and a photodiode A solid-state imaging device comprising: an adjacent MOS transistor; and the MOS transistor has an LDD structure formed by using a sidewall spacer made of polycrystalline silicon for a gate electrode.