KR20040044725A - Sample for measuring a resistance of lightly doped silicon and method for fabricating thereof - Google Patents

Abstract

PURPOSE: A sample for measuring a lightly doped silicon resistance and a fabricating method thereof are provided to enhance an electric characteristic of a TFT having an LDD(Lightly Doped Drain) structure or an offset structure by measuring a lightly doped silicon thin film. CONSTITUTION: A sample for measuring a silicon resistance doped with low density of ions includes a base substrate, a silicon thin film, and a plurality of conductive resistance measurement pads. The silicon thin film is formed on the base substrate(100). The silicon thin film includes a lightly doped region(112) and a couple of heavily doped regions(113,115). The conductive resistance measurement pads(122,125) are formed on the heavily doped regions.

Description

SAMPLE FOR MEASURING A RESISTANCE OF LIGHTLY DOPED SILICON AND METHOD FOR FABRICATING THEREOF}

The present invention relates to a sample for measuring low concentration ion doped silicon resistance and a method of manufacturing the same.

In recent years, the development of semiconductor devices has been actively conducted, and as a result, the performance of the semiconductor devices has been greatly improved while the size of the semiconductor devices has become smaller. The semiconductor device can be manufactured in a very small size of only μm, and has the characteristic of amplifying or switching an electrical signal.

Semiconductor devices have a wide variety of properties depending on the material forming the channel layer. For example, the channel layer can be made of monocrystalline silicon, polycrystalline silicon or amorphous silicon material.

Channel layers using single crystal silicon materials are suitable for high density, high performance semiconductor devices. BACKGROUND Semiconductor devices having a channel layer using a single crystal silicon material are used for components requiring very high operating speed, for example, a RAM or a central processing unit (CPU).

On the other hand, the channel layer using the polycrystalline silicon material or amorphous silicon material can be formed at a lower temperature than the channel layer using the polycrystalline silicon material, so that the channel layer can be formed on a glass substrate or the like. BACKGROUND Semiconductor devices having channel layers using polycrystalline silicon materials or amorphous silicon materials are used in organic electroluminescent devices or liquid crystal displays.

Such widely used semiconductor devices have the largest problem of leakage current in a state in which the semiconductor devices are not operating, that is, in an off state. BACKGROUND ART Conventionally, a light emitting doped drain (LDD) structure or an offset (off-set) structure is widely used as a means for preventing leakage current in an off state.

The conventional LDD structure first forms a gate electrode smaller than the silicon layer on the upper surface of the silicon layer. Subsequently, after the sidewalls are formed of photoresist or insulating film on the sidewalls of the gate electrode, high concentration ion doping is performed on the silicon layer that is not blocked by the gate electrode and the sidewall to adjust the threshold voltage. Subsequently, low side ion doping is performed after removing the sidewall. In this case, although the low concentration ions are doped together in the high concentration ion doped region, the low concentration doped ions do not have a great influence on the high concentration ion doped region.

In such an LDD structure, the length of the LDD greatly affects the characteristics and reliability of the semiconductor device, for example, a thin film transistor. In addition, the low-concentration ion doped region in the LDD structure has a large resistance on the characteristics of the channel layer because the resistance is changed according to the ion concentration.

Therefore, although the characteristic of the resistance change according to the ion doping concentration in the low concentration ion doping region is very important, the resistance change of silicon according to the low concentration ion doping concentration has a problem that is very difficult to measure.

In order to measure the resistance of conventional low concentration ion doped silicon, first, a pair of measurement pads made of metal is formed on the top surface of the low concentration ion doped silicon. Then, there is a method of measuring the resistance of low concentration ion-doped silicon by contacting a test probe with a measurement pad.

At this time, there is a very large contact resistance between the measurement pad and the low concentration ion doped silicon. Therefore, the resistance measured through the actual test probe is the resistance in which the intrinsic resistance of the low concentration ion doped silicon, the contact resistance between the measurement pad and the ion doped silicon are added together. After all, the resistance measured in this way is hardly regarded as the inherent resistance of low concentration ion-doped silicon.

Accordingly, the present invention takes into account such a difficulty in measuring resistance of conventional low-concentration ion-doped silicon, and a first object of the present invention is to measure the resistance of low-concentration ion-doped silicon in a low error range, A low concentration ion-doped silicon resistance measurement sample capable of measuring a change in resistance according to concentration is provided.

In addition, the second object of the present invention is to measure the resistance of the low-concentration ion-doped silicon in a low error range to measure the resistance change according to the concentration of the low-concentration doped ions in the silicon, etc. To provide a method for producing a.

1 is a conceptual diagram showing a sample for measuring the low concentration ion-doped silicon resistance according to a first embodiment of the present invention.

FIG. 2A is a flowchart illustrating a silicon thin film formed on a base substrate according to a first embodiment of the present invention.

FIG. 2B is a process chart showing that low concentration ion doping is performed on a silicon thin film. FIG.

FIG. 2C is a process diagram illustrating that high concentration ion doping is performed on a silicon thin film. FIG.

FIG. 2D is a process chart illustrating that a conductive resistance measurement pad is formed in a high concentration ion doped region of a silicon thin film. FIG.

3A is a process diagram illustrating a silicon thin film formed on a base substrate according to a second embodiment of the present invention.

3B is a process chart showing that high concentration ion doping is performed on a silicon thin film.

3C is a process diagram illustrating low concentration ion doping performed on a silicon thin film.

FIG. 3D is a process chart illustrating that a conductive resistance measuring pad is formed in a high concentration ion doped region of a silicon thin film. FIG.

In order to realize the first object of the present invention, the present invention is formed on a base substrate, a base substrate, and a pair of high concentration ion dopings formed on a lightly doped region and a lightly doped region. A sample for measuring low-concentration ion-doped silicon resistance comprising a silicon thin film comprising a region (heavily doped region) and a pair of conductive resistance measurement pads each contacted on a pair of highly doped regions is provided.

The present invention also provides a method for forming a silicon thin film having a first area on a base substrate, and doping impurity ions at a first concentration to form a first ion doped region. Forming a second ion doped region by doping the impurity ions to a second concentration smaller than the first area and having a second area smaller than the first area at two spaced apart portions of the first ion doped region; It provides a method for producing a sample for measuring the low concentration ion-doped silicon resistance comprising the step of forming a conductive resistance measurement pad in the ion doped region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram showing a sample for measuring the low concentration ion-doped silicon resistance according to a first embodiment of the present invention.

Referring to FIG. 1, the low concentration ion-doped silicon resistance measurement sample 200 is generally composed of a base substrate 100, a silicon thin film 110, and conductive resistance measurement patterns 122 and 125.

The base substrate 100 serves as a body in which the low concentration ion-doped silicon resistance measurement sample 200 is formed.

The silicon thin film 110 is formed on the base substrate 100 with a first area. The silicon thin film 110 is an amorphous silicon thin film or a polysilicon thin film. The silicon thin film 110 is formed by a chemical vapor deposition (Chemical Vapored Deposition) facility.

The silicon thin film 110 is further divided into three areas. Specifically, the silicon thin film 110 is composed of a low concentration ion doped region 112 and a pair of high concentration ion doped regions 113 and 115.

Specifically, the pair of high concentration ion doped regions 113 and 115 formed in the silicon thin film 110 are formed spaced apart from each other by a predetermined interval, and impurities are injected into the high concentration ion doped regions 113 and 115.

The impurities are negative ions or positive ions, for example boron (B) or phosphorus (P). Impurities are implanted in the first dose by ion implantation. In this case, the impurities implanted in the first dose amount significantly lower the electrical resistance in the high concentration ion doped regions 113 and 115 to the metal level. Therefore, the electrical resistance in the high concentration ion doped regions 113 and 115 is very low.

The low concentration ion doped region 112 formed in the silicon thin film 110 is formed between the high concentration ion doped regions 113 and 115. The low concentration ion doped region 112 is ion-doped with the same boron or phosphorus as the impurity implanted into the high concentration ion doped regions 113 and 115. However, the amount of impurities injected into the low concentration ion doped region 112 is injected with a second dose smaller than the first dose. At this time, the second dose of impurities implanted into the low concentration ion doped region 112 is significantly smaller than the first doses injected into the high concentration ion doped regions 113 and 115.

Meanwhile, the conductive resistance measuring pads 122 and 125 are formed in the pair of highly-concentrated ion doped regions 113 and 115 described above. In this case, the conductive resistance measuring pads 122 and 125 are disposed so as not to leave the high concentration ion doped regions 113 and 115. When the conductive resistance measuring pads 122 and 125 extend out of the high concentration ion doped region 113 and 115 to the low concentration ion doped region 112, an intrinsic resistance value of the low concentration ion doped region 112 may be affected.

As described above, the test probes 132 and 135 are in contact with the conductive resistance measuring pads 122 and 125 formed in the pair of high concentration ion doped regions 113 and 115 so that the resistance measurement of the low concentration ion doped regions 112 can be performed.

The reason for measuring the resistance of the low concentration ion doped region 112 through one of the high concentration ion doped region 113, the low concentration ion doped region 112, and the high concentration ion doped region 115 is that This is because the contact resistance between the conductive resistance measuring pads 122 and 125 is negligibly small. As such, when the electrical resistance between the conductive resistance measuring pads 122 and 125 and the high concentration ion doped regions 113 and 115 is low, the resistance measured through the two conductive resistance measuring pads 113 and 115 is inherent in the low concentration ion doped region 112. It is almost similar to resistance. Therefore, when forming a pair of high concentration ion doped regions 113 and 115 spaced apart from each other in the silicon thin film 110, and measuring the resistance of the low concentration ion doped regions 112 through the high concentration ion doped regions 113 and 115, the resistance is very low. Inherent resistance in the low concentration ion doped region 112 can be measured in the error range.

Hereinafter, with reference to the accompanying drawings, a method for producing a low concentration ion-doped silicon resistance measurement sample will be described with reference to the accompanying drawings.

<First Embodiment>

FIG. 2A is a flowchart illustrating a silicon thin film formed on a base substrate according to a first embodiment of the present invention.

Referring to FIG. 2A, a silicon thin film 110 is deposited on the base substrate 100 as a first area. The silicon thin film 110 is made of amorphous silicon or polysilicon and is formed by a chemical vapor deposition process.

FIG. 2B is a process chart showing that low concentration ion doping is performed on a silicon thin film. FIG.

Referring to FIG. 2B, impurities formed of positive or negative ions accelerated in an ion implantation facility are implanted into the silicon thin film 110 illustrated in FIG. 2A in a first dose amount. At this time, the impurity is boron or phosphorus. Accordingly, impurities are ion implanted over the entire surface of the silicon thin film 110 shown in FIG. 2A to form the ion doped region 110a.

FIG. 2C is a process diagram illustrating that high concentration ion doping is performed on a silicon thin film. FIG.

Referring to FIG. 2C, an ion blocking layer 117 is formed on the top surface of the ion doped region 110a as shown in FIG. 2B. In this case, the openings 110b and 110c are formed in the ion blocking layer 117 so that two spaced apart portions of the ion doped region 110a are exposed to the outside. At this time, each of the openings 110b and 110c has a second area, and the second area is smaller than the first area.

Subsequently, impurities, for example, boron or phosphorus, are scanned toward the ion blocking layer 117 from the upper portion of the ion blocking layer 117 with a second dose larger than the first dose.

In this case, impurities are ion-implanted at the second dose in the openings 110b and 110c which are not protected by the ion blocking layer 117 of the ion doped regions 110a to form high concentration ion doped regions 113 and 115. Hereinafter, a region formed between the high concentration ion doping regions 113 and 115 among the ion doping regions 110a has a lower dose than the high concentration ion doping regions 113 and 115 and is defined as a low concentration ion doping region 112.

FIG. 2D is a process chart illustrating that a conductive resistance measuring pad is formed in a high concentration ion doped region of a silicon thin film. FIG.

Referring to FIG. 2D, after the high concentration ion doping regions 113 and 115 and the low concentration ion doping region 112 are formed in the ion doping region 110a, the ion blocking layer 117 shown in FIG. 2C is removed. Subsequently, a conductive metal thin film is formed over the entire area in the high concentration ion doped regions 113 and 115 and the low concentration ion doped regions 112.

The conductive metal thin film is patterned again to form conductive resistance measurement pads 122 and 125 in the high concentration ion doped regions 113 and 115. In this case, the conductive resistance measuring pads 122 and 125 do not extend to the low concentration ion doped region in the patterning process.

The test probes 132 and 135 are in contact with the conductive resistance measurement pads 122 and 125 of the low-concentration ion-doped silicon resistance measurement samples manufactured through the above process. Subsequently, a test power supply having a predetermined voltage and current is applied to the test probe 132. The test power is applied to the low concentration ion doped region 112 through the conductive resistance measuring pad 122 and the high concentration ion doped region 113. The test power applied to the low concentration ion doped region 112 is again applied to the test probe 135 via the high concentration ion doped region 115 and the conductive resistance measurement pad 125. At this time, the resistance is calculated by detecting the voltage and current amounts of the two test probes 132 and 135. In this case, the resistance is the resistance of the conductive resistance measuring pads 122 and 125, the contact resistance in the conductive resistance measuring pads 122 and 125, and the high concentration ion doped regions 113 and 115, and the resistance in the high concentration ion doped regions 113 and 115. And the resistance in the low concentration ion doped region 112 is the sum of the resistances.

At this time, the contact resistances in the conductive resistance measuring pads 122 and 125, the conductive resistance measuring pads 122 and 125, and the high concentration ion doped regions 113 and 115 and the resistances in the high concentration ion doped regions 113 and 115 may be ignored. As a result, the summation resistance may be referred to as resistance in the low concentration ion doped region 112.

Second Embodiment

3A is a process diagram illustrating a silicon thin film formed on a base substrate according to a second embodiment of the present invention.

Referring to FIG. 3A, a silicon thin film 110 is deposited on the base substrate 100 as a first area. The silicon thin film 110 is made of amorphous silicon or polysilicon and is formed by a chemical vapor deposition process.

3B is a process chart showing that high concentration ion doping is performed on a silicon thin film.

Referring to FIG. 3B, an ion blocking layer 118 is formed on the top surface of the silicon thin film 110. In this case, the openings 110d and 110e are formed in the ion blocking layer 118 so that two spaced apart portions of the silicon thin film 110 are exposed to the outside. At this time, each of the openings 110d and 110e has a second area, and the second area is smaller than the first area.

Subsequently, impurities, for example, boron or phosphorus, are scanned toward the ion blocking layer 118 from the top of the ion blocking layer 118 in the first dose.

In this case, impurities are ion-implanted at the first dose in the openings 110d and 110e which are not protected by the ion blocking layer 118 of the silicon thin film 110, thereby forming high concentration ion doped regions 113 and 115.

3C is a process diagram illustrating low concentration ion doping performed on a silicon thin film. Referring to FIG. 3C, in the silicon thin film 110 having the high concentration ion doping regions 113 and 115, impurities composed of positive ions or negative ions accelerated in an ion implantation facility over the entire area are filled with a second dough. It is injected in a small amount. At this time, the impurity is boron or phosphorus. At this time, the second dose amount is much smaller than the first dose amount described above.

In the process of FIG. 3C, impurities are implanted into the silicon thin film in a second dose amount into regions other than the high concentration ion doped regions 113 and 115 and the high concentration ion doped regions 113 and 115. However, since a large amount of impurities are already implanted in the high concentration ion doped regions 113 and 115, the electrical properties of the high concentration ion doped regions 113 and 115 are not changed. Get the effect.

Hereinafter, the region doped with the second dose in the silicon thin film 110 will be defined as a low concentration ion doped region.

FIG. 3D is a process chart illustrating that a conductive resistance measuring pad is formed in a high concentration ion doped region of a silicon thin film. FIG.

Referring to FIG. 3D, after the high concentration ion doping regions 113 and 115 and the low concentration ion doping region 112 are formed in the silicon thin film 110, the high concentration ion doping regions 113 and 115 and the low concentration ion doping region 112 are formed over the entire area. A conductive metal thin film is formed.

The conductive metal thin film is patterned again to form conductive resistance measurement pads 122 and 125 in the high concentration ion doped regions 113 and 115. In this case, the conductive resistance measuring pads 122 and 125 do not extend to the low concentration ion doped region in the patterning process.

The test probes 132 and 135 are in contact with the conductive resistance measurement pads 122 and 125 of the low-concentration ion-doped silicon resistance measurement samples manufactured through the above process. Subsequently, a test power supply having a predetermined voltage and current is applied to the test probe 132. The test power is applied to the low concentration ion doped region 112 through the conductive resistance measuring pad 122 and the high concentration ion doped region 113. The test power applied to the low concentration ion doped region 112 is again applied to the test probe 135 via the high concentration ion doped region 115 and the conductive resistance measurement pad 125. At this time, the resistance is calculated by detecting the voltage and current amounts of the two test probes 132 and 135. In this case, the resistance is the resistance of the conductive resistance measuring pads 122 and 125, the contact resistance in the conductive resistance measuring pads 122 and 125, and the high concentration ion doped regions 113 and 115, and the resistance in the high concentration ion doped regions 113 and 115. And the resistance in the low concentration ion doped region 112 is the sum of the resistances.

At this time, the contact resistances in the conductive resistance measuring pads 122 and 125, the conductive resistance measuring pads 122 and 125, and the high concentration ion doped regions 113 and 115 and the resistances in the high concentration ion doped regions 113 and 115 may be ignored. As a result, the summation resistance may be referred to as resistance in the low concentration ion doped region 112.

As described above in detail, it is possible to measure a thin film of low concentration ion-doped silicon, thereby improving the characteristics of a thin film transistor having an LDD structure or an offset structure.

In the detailed description of the present invention described above with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (6)

A base substrate; A silicon thin film formed on the base substrate and including a lightly doped region and a pair of high concentration doped regions spaced apart from each other on the lightly doped region; And And a pair of conductive resistance measurement pads each contacted on said pair of high concentration doped regions. Forming a silicon thin film having a first area on the base substrate; Doping impurity ions at a first concentration to the silicon thin film to form a first ion doped region; Forming a second ion doped region by doping the impurity ions at a second concentration higher than the first concentration and having a second area smaller than the first area at two spaced apart portions of the first ion doped region; And And forming a conductive resistance measuring pad in the second ion doped region. 3. The method of claim 2, wherein the impurity ions are negative ions or positive ions. 3. The method of claim 2, further comprising forming an ion stopper layer in the remaining regions of the silicon thin film except for the portion where the second ion doped region is to be formed before the forming of the second ion doped region. The manufacturing method of the sample for low-concentration ion-doped silicon-resistance measurement made into. Forming a silicon thin film having a first area on the base substrate; Forming a first ion doped region by doping impurity ions at a first concentration in two locations spaced apart from each other with a second area smaller than the first area of the silicon thin film; Forming a second ion doped region by doping the impurity ions to the silicon thin film at a second concentration lower than the first concentration; And And forming a conductive resistance measuring pad in the first ion doped region. The low concentration ion of claim 5, further comprising forming an ion stopper layer in the remaining region of the silicon thin film except for the first ion doped region before forming the first ion doped region. Method for preparing a sample for measuring doped silicon resistance.