JPH0284340U - - Google Patents

Info

Publication number
JPH0284340U
JPH0284340U JP16474688U JP16474688U JPH0284340U JP H0284340 U JPH0284340 U JP H0284340U JP 16474688 U JP16474688 U JP 16474688U JP 16474688 U JP16474688 U JP 16474688U JP H0284340 U JPH0284340 U JP H0284340U
Authority
JP
Japan
Prior art keywords
ground layer
input
pin
ground
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16474688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16474688U priority Critical patent/JPH0284340U/ja
Publication of JPH0284340U publication Critical patent/JPH0284340U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例による半導体パツケ
ージを示す破断斜視図、第2図は本実施例による
ノイズ防止部材を示す破断斜視図、第3図は従来
の半導体パツケージを示す斜視図、第4図は課題
を説明する回路図である。 図において、1はパツケージ、2は入出力ピン
、11はノイズ防止部材、11―1は絶縁板、1
1―2a,11―2bはアースパターン、11―
3はスリツト、を示す。
1 is a cutaway perspective view showing a semiconductor package according to an embodiment of the present invention, FIG. 2 is a cutaway perspective view showing a noise prevention member according to the present embodiment, and FIG. 3 is a perspective view showing a conventional semiconductor package. Figure 4 is a circuit diagram explaining the problem. In the figure, 1 is a package, 2 is an input/output pin, 11 is a noise prevention member, 11-1 is an insulating plate, 1
1-2a, 11-2b are ground patterns, 11-
3 indicates a slit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプを内設したパツケージ1より突出
させて一定ピツチで配列した隣接する各入出力ピ
ン2間に、絶縁体11―1を介してアース層11
―2を該入出力ピン2と平行に配して、該アース
層11―2とアースピンを導通するように構成し
てなることを特徴とする半導体パツケージ。
A ground layer 11 is connected via an insulator 11-1 between adjacent input/output pins 2 that protrude from the package 1 in which a semiconductor chip is installed and are arranged at a constant pitch.
-2 is arranged parallel to the input/output pin 2, and the ground layer 11-2 is electrically connected to the ground pin.
JP16474688U 1988-12-19 1988-12-19 Pending JPH0284340U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16474688U JPH0284340U (en) 1988-12-19 1988-12-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16474688U JPH0284340U (en) 1988-12-19 1988-12-19

Publications (1)

Publication Number Publication Date
JPH0284340U true JPH0284340U (en) 1990-06-29

Family

ID=31450612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16474688U Pending JPH0284340U (en) 1988-12-19 1988-12-19

Country Status (1)

Country Link
JP (1) JPH0284340U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153579A (en) * 2008-12-25 2010-07-08 Denso Corp Lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153579A (en) * 2008-12-25 2010-07-08 Denso Corp Lead frame

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