JPH0273719A - Input buffer circuit - Google Patents

Abstract

PURPOSE:To simplify the design and to reduce the cost by accepting an inputted CMOS level and an inputted TTL level by an input buffer section. CONSTITUTION:An input level detected by a NOR gate 3 is set to a CMOS level and an input level detected by a NAND gate 4 is set to a TTL level respectively. When the CMOS level is used for the input terminal, the signal of the CMOS level is detected by a NOR gate 3 only. When the TTL level is inputted, its high level is detected by the NAND gate 4 and the high level being the TTL level as the intermediate level is not affected on the NOR gate 3 detecting the CMOS level. Thus, two kinds of input buffers are not required and since one kind of the buffer is enough, the design cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input buffer circuit, and particularly to an input buffer circuit for a semiconductor integrated circuit device that handles digital signals.

[Conventional technology]

The input buffer circuit is used in the input section of the semiconductor integrated circuit device to input signals from the outside, and is used to recognize whether the signal level applied from the outside to the input section of the semiconductor integrated circuit device is electrically high level or low level. belongs to.

As conventional technology, when the external circuit is configured at the CMOS level, the circuit threshold level of the input buffer circuit is approximately 1/2 of the power supply voltage VDD, but in actual products, 0.7 V or more is High level, 0.3■D
The low level and standard are set below D, and the threshold value may be between these levels.

However, at present, the signal level that is commonly used as a general-purpose specification is the TTL level, and in order to electrically connect with the general-purpose specification, the electrical conditions of the TTL level, which are the high level worst value 2.0 and the low level Must be able to sufficiently recognize 0.8V. Therefore, in a semiconductor integrated circuit device configured with CMO3, the input buffer circuit to which TTL level is also input has one for CMOS level and one for TTL level.
Two large power buffer sections for the TL level are required.

FIG. 2 is an example of a conventional high-power buffer circuit. an input terminal 1 from an external circuit; a CMOS level manual buffer section 7 that receives an input signal from the input terminal 1;
It has a TTL level buffer section 8 which inputs the input signal from the input terminal 1, and is connected to the transfer gate 11 or the transfer gate 11 by the CMOS level signal 1 which selects CMO 8 or TTL level from the outside and the TTL level selection signal 10. Either one of the gates 12 is turned on, and either the output signal of the CMOS level manual buffer section 7 or the output signal of the TTL level manual buffer section is output to the output terminal 6 of the input buffer circuit.
is output to.

In FIG. 2, when a high level of TTL level is input, in the CMOS level manual buffer section,
Since the CMOS level threshold is close to the TTL high level, a through current flows.

In addition, in conventional large-power buffer circuits that had two types of input buffer sections, by making the circuit so that the external manual buffer can be used at both the CMOS level and the TTL level, two types of input buffers are no longer necessary. Since the design can be carried out, cost reductions can be expected at the time of design.

[Problem to be solved by the invention]

In the input buffer circuit according to the prior art described above, 1
A large buffer section for CMOS level and T for each input.
TL level high-power buffer sections are provided separately, and these are switched by an external selection signal.
When realized in a semiconductor integrated circuit device, the top of the surface becomes large, and when a high level of TTL level is input, CMO3
There is a drawback that a through current flows in the human power buffer section.

[Means to solve the problem]

The input buffer circuit of the present invention is a semiconductor integrated circuit device that receives a first input signal and a second input signal.
It is configured to include an AND gate, an inverter to which the output signal of the NAND gate is input, and a NOR gate to which the first input signal and the output signal of the inverter are input, and the output of the NOR gate is used as an output signal. Ru.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of an input buffer circuit according to the present invention.

In this embodiment, input terminal 1 receives a CMOS level or TTL level signal, input level selection signal 2 selects TTL level input, and gate inputs the signal from input terminal 1 and input level selection signal 2. A NAND gate 4, an inverter 5 whose gate input is the output of the NAND gate 4, a NOR gate 3 whose gate inputs are the signal from the input terminal 1 and the output of the inverter 5, and an input buffer circuit whose output is the output of the NOR gate 3. It is composed of an output terminal 6 for outputting to the outside.

Next, the operation of this embodiment will be explained.

In FIG. 1, it is assumed that the input level that the NOR gate 3 can detect is set to the CMOS level, and the input level that the NAND gate 4 can detect is set to the TTL level.

First, when using a CMOS level as an input terminal, the input level selection signal 4 becomes a high level output, and the input terminal 1
It is not affected by input signals from Therefore, the CMOS level signal input to the input terminal 1 is detected only by the NOR gate 3.

Next, when using a TTL level as an input terminal, the input level selection signal is set to high level. Here, if a high level of TTL level is input to input terminal 1, NOR gate 3 can only detect the CMOS level, so TTL
The high level of the specs can only be judged to be intermediate to the CMOS level. However, NAND gate 4 is TTL
Since the TTL high level is detected and the inverter 5 outputs a low level, the NOR gate 3 is fixed at a low level. That is, when a TTL level is input, the high level is detected by the NAND gate 4, and the CMOS
For the NO, R gate 3 that detects the level, the high level of the TTL level, which is an intermediate level, is not affected.

Further, there is no particular problem when a low level of TTL level is input.

In the input buffer circuit in this embodiment, TTL
There is no through current in the input buffer circuit when a high level is input, and current consumption can be reduced when a semiconductor integrated circuit device is realized. Furthermore, since the circuit configuration is simple, design is easy, and a reduction in design cost can be expected.

〔Effect of the invention〕

As described above, in the input buffer circuit of the present invention, one input buffer unit serves both the input CMOS level and the TTL level, so the design is simple and the design cost can be reduced. Furthermore, since there is no through current when a high level TTL level is input, there is an effect that current consumption can be reduced when implemented in a semiconductor integrated circuit device.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a high-power buffer circuit according to the present invention, and FIG. 2 is an example of an input buffer circuit according to the prior art. 1...Input terminal, 2...Input level selection signal, 3...NOR gate, 4...
NAND gate, 5... Inverter, 6...
...Output terminal.

Claims (1)

[Claims] In a semiconductor integrated circuit device, a NAND gate receives a first input signal and a second input signal;
an inverter that inputs the output signal of the gate, and an NO input that inputs the first input signal and the output signal of the inverter.
An input buffer circuit comprising: an R gate, the output of the NOR gate being an output signal.