JPH0443712A - Semiconductor output circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by inputting complementary gate signals to the gates of two p-channel MISFETs and controlling an output bipolar transistor (TR). CONSTITUTION:In the case of an input signal IN from an input terminal 13 at a high level, a p-channel MISFET2 is turned off and a p-channel MISFET3 is turned on, the base level of an output bipolar TR 1 is Vref and an output signal OUT at a low level in ECL (Emitter Coupled Logic) is outputted from an output terminal 10. On the other hand, in the case of input signal IN at a low level, the p-channel MISFET2 is turned on and the p-channel MISFET3 is turned off and the base level of the output bipolar TR 1 is Vcc and an output signal OUT from the output terminal 10 goes to an ECL high level. Since the p-channel MISFETs 2,3 are operated complementarily, no DC current is consumed. Thus, the power of the ECL output buffer circuit is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an ECL (Emitter Coupled
(Logic) This relates to a semiconductor output circuit that outputs a signal at a logic level.

[Conventional technology]

In recent years, in semiconductor circuits, B i -CMOS circuits in which bipolar elements and CMO5 elements are mixed on one chip and have the characteristics of each have come to be frequently used.

1-In a CMOS circuit, ECL (Emitter Coupled
A high-speed, low-power consumption logic circuit can be realized by combining a low-power consumption CMOS circuit with a low-power consumption CMOS circuit. Among these LSIs based on B1CMOS elements, high-speed ones have LSIs on the board.
In order to perform high-speed signal transmission of S If, the ECL level (high level is Vcc) is applied to the input/output interface.
(Power supply voltage) -0.8V or so, low level is Vccl
On the other hand, in order to suppress current consumption, the internal circuit of the chip uses CMOS level (high level is about Vcc (power supply voltage), low level is about Vcc (power supply voltage)).
Therefore, the input/output interface section of such a chip requires ECL-CMOS logic level conversion at the input section and CMOS-ECL logic level conversion at the output section.

The input/output interface section at the ECL level uses "Bipolar Integrated Circuit" 1 written by Ikoma and Ichise and published by Kindai Kagakusha.
A conventional current switching type logic circuit as shown on page 00 is used. A conventional example of an ECL output buffer circuit utilizing this is shown in FIG. The circuit in the same figure is C
CMOS-ECL level conversion is performed for the MOS level signal IN, and a current switching type logic circuit is used to
Drives the output bipolar transistor 1.

[Problem to be solved by the invention]

In the conventional circuit shown in FIG. 5, the CMOS-ECL level conversion section and the ELC output buffer circuit section
．． A constant current source such as 8.9 is required and DC current is consumed. Therefore, for semiconductor chips with many output pins, such as recent high-performance microprocessors, if the circuit shown in Figure 5 is used, the current consumption will increase in proportion to the number of bins, and if the output is around 100 pins, the current consumption will increase. , the output buffer section alone requires a current of 2 to 3 W.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor output circuit that outputs ECL logic level signals with reduced power consumption.

[Means to solve the problem]

The semiconductor output circuit of the present invention is an ECL logic ratio buffer circuit, and includes an output bipolar transistor that outputs a signal at an ECL logic level on one semiconductor chip, and a midpoint of the cascade connection connected to the base of the output bipolar transistor. Two p-channel MISFETs are provided,
The configuration is such that complementary gate signals are input to the gates of each of the two p-channel MISFETs to control the output bipolar transistor.

Further, in the above configuration, the two p-channel MISFs
Means for controlling the timing of the complementary gate signals is provided at each gate of the ET, and the two p-channel M
A configuration may be adopted in which control is performed so that the ISFETs are not turned on at the same time.

[Effect]

In the present invention, a bipolar element is controlled by a MISFET such as a CMOS, so that DS current consumption is not necessary, and the reference voltage source can ensure an output level that satisfies the ECL standard. Also, the circuit is mainly MISFET
Since it is composed of elements, it uses a smaller area than a conventional circuit composed of bipolar elements and resistors.

As a result, in the ECL multi-bin output chip, the DC power consumption of the output buffer section can be reduced, and the area occupied by the ratio buffer can be reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.6 The semiconductor output circuit of this embodiment includes an output bipolar transistor 1 that outputs a signal at the ECL level, and a series-connected transistor 2 that controls the base potential of the output bipolar transistor 1. 2 p-channel MISFETs
．． 3 and the CMOS level input signal input to the gate of p channel MISFET2.
An inverter 4 input to the gate of channel MISFET 3 is provided on the same semiconductor chip.

A resistor 5 (50Ω) connected to the output terminal 10 is a termination resistance of ECL, and is connected to a −2V termination reference voltage source. A high power supply voltage (Vcc) and a low power supply voltage (VEE) are supplied from power supply terminals 11 and 12, respectively. A load capacitor 6 is connected between the output terminal 10 and the power supply terminal 12.
is connected. Further, the train terminal of the p-channel MISFET 3 is connected to the reference voltage terminal 14. 0garaE
A reference voltage (V, er) smaller by the output amplitude of CL is applied.

Next, the operation will be explained.

When the input signal IN from the input terminal 13 is at high level,
p-channel MISFET2 is off, p-channel MISFET2
5FET3 is on, the base potential of the output bipolar transistor 1 becomes V r e f, and the output terminal 10 becomes E
A low level output signal OUT of CL is output. on the other hand,
When the input signal IN is low level, the p-channel MIS
FET2 is on, p-channel MISFET3 is off,
The base potential of the output bipolar transistor 1 is Vcc (
OV), and the output signal OUT of output terminal 10 is ECL.
becomes a high level. The operating waveforms of this circuit are shown in FIG.

Note that at this time, p-channel MISFET 2.3 performs complementary operations and therefore does not consume DC current. Furthermore, since MISFET elements are used except for the output bipolar transistor l, the area occupied by the elements can be smaller than in a conventional circuit configuration using bipolar elements and resistors.

FIG. 3 shows another embodiment of the present invention, showing a semiconductor output circuit according to claim 2, in which two NAND4
0 and an even number of inverters 4 connected in series to delay the signal.
Timing control circuits 22 and 32 consisting of 1 and 1 are connected to each other.

In the circuit shown in FIG. 3, in response to the input signal IN, the gate terminals 21 and 31 receive signals A and 31, respectively, as shown in FIG.
B is generated. With these A and B signals, p channel M
In order for ISFET2.3 to be controlled, the P-channel MI
Since the SFETs 2.3 are not turned on at the same time and no through current flows through the p-channel MISFET 2.3, power consumption can be reduced.

〔Effect of the invention〕

The semiconductor integrated circuit of the present invention controls the output bipolar transistor with a p-channel MISFET, so that the E
The power consumption of the CL output buffer circuit can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram illustrating another embodiment of the present invention; FIG. 4 is a timing diagram illustrating an outline of the operation of the circuit in FIG. 3; The figure is a circuit diagram showing a conventional ECL output buffer circuit. 1... Output bipolar transistor, 2, 3...p
Cha! Channel MISFET, 4... Inverter, 5...
Resistor, 6...Load capacitor, 7-9... Constant current source, 10... Output terminal, 11.12... Power supply terminal, 1
3...Input terminal, 14...Reference voltage terminal, 2131
...Timing control circuit, 40...2 manual NAND
, 41... Inverter.

Claims (1)

[Claims] 1. In an ECL logic output buffer circuit, an output bipolar transistor that outputs a signal at an ECL logic level is provided on one semiconductor chip, and a midpoint of the cascade connection is connected to the base of the output bipolar transistor. two p-channel MISFETs are provided, and the two p-channel MISFETs are provided.
A semiconductor output circuit characterized in that complementary gate signals are input to each gate of an ISFET to control the output bipolar transistor. 2. Means for controlling the timing of the complementary gate signals is provided at each gate of the two p-channel MISFETs, and control is performed so that the two p-channel MISFETs are not turned on at the same time.
The semiconductor output circuit described.