JPS63107225A - Complementary inverter circuit - Google Patents

Abstract

PURPOSE:To vary the response time of an inverter by controlling a series- connected transistor (TR) added to the inverter in parallel. CONSTITUTION:When a signal with a logic level '1' is inputted to an input terminal B and a TR QP2 is off, the input of a signal with a logic level '0' to an input terminal A turns off a TR QN1 on condition that a TR QP1 is on, and the time from the input terminal A to an output terminal OUT is t1. On the other hand, when the signal with the logic level '0' is inputted to the input terminal B and the TR QP2 is on, the input of the signal with the logic level '0' to the input terminal A turns on all of TRs QP1, QP2 and QP3 and turns off a TR QN1, and the time from the input terminal A to the output terminal OUT is t2 shorter than the t1. Thus, the response time of the inverter can be varied by varying the threshold level of a 1st inverter with the logic level signal from the input terminal B.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to complementary inverter circuits.

[Conventional technology]

Conventionally, this type of inverter circuit is comprised of a P-channel MOS transistor Q2 and an N-channel MOS transistor QN+, as shown in FIG. The operational response time of this inverter circuit is determined by the size of each transistor and the capacitance of the load connected to the output terminal OUT.

[Problem that the invention seeks to solve]

However, in such an inverter circuit, the response time is uniformly determined by the capacity of the transistor and the capacitance of the load connected to the output terminal, and it is impossible to adjust the response time.

[Means for solving problems]

The complementary inverter circuit of the present invention has a common gate between a drain of an inverter transistor having a first signal as a gate input and a power supply and a first transistor having a second signal as a gate input and a transistor of the inverter. The inverter is connected in series with a second transistor having the inverter, and the threshold level of the inverter is changed by the second signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2 showing an embodiment of the present invention, a P-channel MOS transistor QP21 is connected in series to a first inverter composed of a P-channel MOS transistor Qp+ and an N-channel MOS transistor QNI. QP3 is connected, the gate of transistor QP3 is shared with 1 to transistor Qpz of the first inverter, and the gate of transistor QP2 is connected to data input terminal B.
As such, second and third inverters are further connected to the output of the first inverter. The second inverter is P
It is composed of a channel MOS transistor QP4 and an N-channel MOS transistor QN2. Also, the third
The inverter is a P-channel MOS) transistor Qp5.
and an N-channel MOS transistor QN3.

In this configuration, the logic level “1” is applied to the data input terminal B.
When a signal of 0 point is input and transistor Q2□ is off, if a signal of logic level ``0'' is input to data input terminal A, transistor QPI turns on and transistor QNI turns off, and at 0 point. The output waveform of is shown in Figure 2 (
a>.

At that time, the time from input terminal A to output terminal OUT is 1
It becomes 1. On the other hand, data input terminal B has logic level “0”.
When a signal of 0 is input and transistor QP2 is on, when a signal of logic level ゛°O゛' is input to data input terminal A, transistors QPI and QP21Qps are all on, and transistor QNI is off, and the output becomes 0.
The output waveform at the point will be as shown in Figure 2 (b), at this time,
The time from the input terminal A to the output terminal OUT is t, which is shorter than t2. In this way, the threshold level of the first inverter whose gate is input terminal A can be changed by the logic level signal of input terminal B, and the response time of this inverter can be changed.

In the embodiment described above, P-channel MOS transistors QP21 to QP3 are used, but as shown in FIG. 3, it is also possible to replace transistor QP2 with an N-channel MOS transistor QN4. Furthermore, as shown in FIG. 4, the same implementation can be achieved by connecting the series connection of N-channel MOS transistors QN51 to QN6 to the output of the first inverter.

Note that the second and third inverters are provided for waveform rounding correction and waveform rise and fall time adjustment, and may be omitted. Also, FIG.

In FIGS. 3 and 4, VC and V are power supplies.

〔Effect of the invention〕

As explained above, according to the present invention, the response time of the inverter can be changed by controlling the series-connected transistors added in parallel to the inverter.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is an operation waveform diagram, Figs. 3 and 4 are block diagrams showing other embodiments of the present invention, and Fig. 5 is a conventional example. FIG. Qp1 to Qps...P channel MOS transistor, QNI to QN6...N channel MOS transistor, A, B...data input terminal, OUT...output terminal. Bud 1 time (a) C1,,) Tei 2 Kokusho 3 Concave peg 4 Ment Certain 51! r

Claims (4)

[Claims] (1) A first transistor that receives a second signal as a gate input and a second transistor that has a common gate with the inverter transistor between the drain of the inverter transistor that receives the first signal as a gate input and the power supply. A complementary inverter circuit, characterized in that a transistor is connected in series and a threshold level of the inverter is changed by the second signal. (2) The complementary inverter circuit according to claim 1, wherein the first transistor and the second transistor are P-channel MOS transistors. (3) The complementary inverter circuit according to claim 1, wherein the first transistor is an N-channel MOS transistor, and the second transistor is a P-channel MOS transistor. (4) The complementary inverter circuit according to claim 1, wherein the first transistor and the second transistor are N-channel MOS transistors.