JPH10154027A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent current consumption from increasing since large current continues to flow in an input circuit part during an input state when an input signal is indeterminate and in a high impedance state at the time of inputting data from an input-output shared terminal and when the value of power voltage is different from other semiconductor integrated circuit that is connected to the input-output shared terminal. SOLUTION: A CPU 12, an input-output data latch 13, an output data latch 14 and a bus buffer 15 are connected to a data bus 11. A clocked inverter 17 is connected between the latch 14 and an input-output shared terminal 16. The latch 13 latches data that controls the operation of the inverter 17. Data that is inputted from the terminal 16 is supplied to one input terminal of a CMOS type NOR circuit 18. An input bus output signal of a pulse-shaped 'L' which is outputted from the CPU 12 is inputted to the other input terminal of the circuit 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an input / output terminal, and more particularly to an improvement for reducing current consumption in an input circuit when the input / output terminal is used as an input terminal. .

[0002]

2. Description of the Related Art In a semiconductor integrated circuit such as a one-chip microcomputer, the number of external terminals must be reduced as much as possible in order to reduce the chip size as much as possible and reduce the manufacturing cost. Therefore, an input / output terminal is used as a part of the terminal.

FIG. 7 shows a conventional one using an input / output terminal.
FIG. 2 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit for a chip microcomputer. In the figure, a data bus 11 is connected to a CPU 12, an input / output data latch 13, an output data latch 14, and a bus buffer 15.

The CPU 12 outputs data to be output to the outside of the semiconductor integrated circuit and various control signals for controlling the operations of the input / output data latch 13, the output data latch 14, and the bus buffer 15. The data from the CPU 12 is latched by the output data latch 14. A clocked inverter 17 is connected between the output data latch 14 and the input / output terminal 16.

[0005] The input / output data latch 13 provides a control signal for controlling the operation of the clocked inverter 17.
Latching is performed based on a control signal from the CPU 12. During the data output period, the input / output data latch 13
The clocked inverter 17 operates according to the output of
The data latched by the output data latch 14 is inverted by the clocked inverter 17 and output from the terminal 16 to the outside of the integrated circuit.

A signal input from a terminal 16 is supplied to a bus buffer 15 via two inverters 22 and 19. The output of the bus buffer 15 is transmitted to the data bus 11. Then, during the period of inputting a signal from the terminal 16, the clocked inverter 17 does not operate, the output is brought into a high impedance state, and the terminal 16 is used as an input terminal.

[0007]

By the way, in the above-mentioned conventional semiconductor integrated circuit, when the terminal 16 is in the input state, the input signal is indefinite or in the high impedance state, When the value of the power supply voltage of the other semiconductor integrated circuit connected to the terminal 16 differs from that of the terminal 16, a large through current may flow through the first-stage inverter 22.

FIG. 8 shows a CM in which the inverters 22 and 19 are composed of N-channel and P-channel MOS transistors.
5 shows an input voltage (gate voltage) -current characteristic in the case of an OS inverter. In the figure, Vth (N) and | Vth (P) | are threshold voltages of N-channel and P-channel MOS transistors, and I (N) and I (P) are current characteristics of N-channel and P-channel MOS transistors alone. Yes, I (cmos)
Is a current characteristic of the entire inverter obtained by combining I (N) and I (P).

As shown in the figure, the current consumption of the inverter is small in a region where the input voltage is smaller than Vth (N) and in a region larger than VDD (power supply voltage) − | Vth (P) |. However, when the input voltage becomes a value in the range between Vth (N) and VDD− | Vth (P) |, the current consumption increases, and the input voltage becomes the largest at half the power supply voltage VDD. I have. As described above, in the conventional semiconductor integrated circuit, the current consumption of the first-stage inverter 18 greatly changes depending on the value of the input voltage.

Since the current as described above continues to flow during the period when the terminal 16 is in the input state, when the input signal is unstable or in the high impedance state as described above, or when the terminal 16 is connected to the terminal 16, Further, when the value of the power supply voltage is different from that of other semiconductor integrated circuits, the current consumption is disadvantageously increased.

Further, in the related art, an input / output terminal is also used for inputting an analog signal. FIG.
FIG. 2 is a block diagram showing a schematic configuration thereof. This semiconductor integrated circuit is different from that shown in FIG.
An A / D converter 23 for converting an analog signal input from the terminal 16 into a digital signal and an analog use permission latch 24 for latching a control signal for permitting the input of the analog signal from the terminal 16 are newly added. Point that
The point is that a NOR circuit 25 is provided instead of the inverter 22. The data input to the terminal 16 and the output from the analog use permission latch 24 are supplied to the NOR circuit 22.

In such a configuration, when data is input from the terminal 16, the output from the analog use permission latch 2421 is set to "L". At this time, the output of the NOR circuit 25 changes according to the input data from the terminal 16. That is, when the input data is “H”, the output of the NOR circuit 25 is “L”, and when the input data is “L”, the NOR circuit 25 is
Becomes "H", and data corresponding to the input data from the terminal 16 is transmitted to the data bus 11 via the bus buffer 15.

On the other hand, when an analog signal is input from the terminal 16, the output from the analog use permission latch 24 is set to "H". At this time, the output of the NOR circuit 25 is fixed at "L". Then, the analog signal input from the terminal 16 is converted into a digital signal by the A / D converter 23 and transmitted to the data bus 11.

As described above, even in the conventional semiconductor integrated circuit in which the terminal 16 is also used for inputting an analog signal, when the CMOS type NOR circuit composed of N-channel and P-channel MOS transistors is used as the NOR circuit 25, 16
The input state is set when the input signal is undefined or high impedance when data is input from or when the value of the power supply voltage is different from that of another semiconductor integrated circuit connected to the terminal 16. During the period, there is a disadvantage that a large current continues to flow in the NOR circuit 25 and the current consumption increases.

Further, the semiconductor integrated circuit of FIG. 9 requires the analog use permission latch 24, which has a drawback that miniaturization of the chip size is hindered accordingly. The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a semiconductor integrated circuit capable of reducing current consumption when an input / output terminal is used as an input terminal.

Another object of the present invention is to provide a semiconductor integrated circuit which can be made smaller in chip size than the conventional one when not only using the input / output terminal as an input terminal but also sharing an analog signal. To provide.

[0017]

A semiconductor integrated circuit according to the present invention comprises an input / output terminal, a data holding circuit for holding data to be output from the terminal, and a data holding circuit provided between the data holding circuit and the terminal. A data output circuit that outputs data corresponding to the data held by the data holding circuit during the data output period, and a data output circuit whose output is set to a high impedance state during other periods; A data acquisition circuit for outputting data corresponding to the data supplied to the terminal while the pulse-shaped signal is supplied.

A semiconductor integrated circuit according to the present invention is provided with an input / output terminal, a data holding circuit for holding data to be output from the terminal, and a data output period between the data holding circuit and the terminal. A data output circuit that outputs data corresponding to the data held in the data holding circuit, and in other periods, a data output circuit whose output is set to a high impedance state, and a pulse signal are supplied. A data capture circuit for internally outputting data corresponding to the data supplied to the terminal during a period in which the signal is supplied, and converting an analog signal supplied to the terminal to digital data and outputting it internally. An A / D conversion circuit. And, as the above-mentioned data acquisition circuit, C
A MOS NAND circuit or a CMOS NOR circuit is used.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 illustrates the present invention in one chip.
The first implemented on semiconductor integrated circuits for microcomputers
It is a block diagram showing a schematic structure by an embodiment. In the figure, a data bus 11 includes a CPU 12, an input / output data latch 13, an output data latch 14, and a bus buffer.
15 are connected.

The CPU 12 outputs data to be output to the outside of the semiconductor integrated circuit and various control signals for controlling operations of the input / output data latch 13, the output data latch 14, the bus buffer 15, and the like. Then, the data from the CPU 12 is supplied to the output data latch 14 via the data bus 11, where it is latched. This output data latch 14
And a clocked inverter 17 between the
Is connected.

The input / output data latch 13 stores data for controlling the operation of the clocked inverter 17 into C / C.
Latch is performed based on an input / output latch signal from PU12.
During the data output period, the clocked inverter 17 is activated according to the output of the input / output data latch 13, and the data latched by the output data latch 14 is inverted by the clocked inverter 17. Output from terminal 16 to the outside.

The data input from the terminal 16 is supplied to one input terminal of a CMOS NOR circuit 18. The other input terminal of the NOR circuit 18 is supplied with the same control signal as the input bus output signal for controlling the operation of the bus buffer 15 which is output from the CPU 12. This NO
The output of the R circuit 18 is supplied to the bus buffer 15 via the inverter 19.
Supplied to Further, the output of the bus buffer 15 is transmitted to the data bus 11.

In such a configuration, during a period in which data is output from the terminal 16, the clocked inverter 17 is activated according to the output of the input / output data latch 13, and the data latched by the output data latch 14 The signal is inverted by the clocked inverter 17 and output from the terminal 16 to the outside. During this period, the input bus output signal input to the bus buffer 15 and the NOR circuit 18 is kept at “H”,
The output of the circuit 18 is fixed at "L" and the bus buffer 15
Is inactive.

On the other hand, during a period in which data is input from the terminal 16 to the inside, the clocked inverter 17 is deactivated in accordance with the output of the input / output data latch 13 and its output is brought into a high impedance state, Is enabled.

During this data input period, the CPU
A pulse input bus output signal of “L” is input to the bus buffer 15 and the NOR circuit 18 from 12. The output of the NOR circuit 18 changes in accordance with the input data from the terminal 16 only during the period in which the "L" pulse signal is input. That is, when the input data is "H", the NOR circuit 18
Is "L", and when the input data is "L", NO
The output of the R circuit 18 becomes “H”, and data corresponding to the input data from the terminal 16 is transferred to the bus buffer via the inverter 19.
Supplied to 15. The bus buffer 15 operates only while the above-mentioned "L" pulse signal is input, and the inverter 19
Is transmitted on the data bus 11.

Incidentally, the CMOS NOR circuit shown in FIG.
In FIG. 18, as shown in FIG. 2, between the source and drain of the two P-channel MOS transistors 31 and 32 are inserted in series between the power supply voltage VDD and the output OUT, and between the output OUT and the ground voltage. The two N-channel MOS transistors 33 and 34 have a configuration in which the source and the drain are inserted in parallel. Then, each of the two P-channel MOS transistors 3
Input data from terminal 16 and CPU 1
2 and the input bus output signals from the CPU 12 are also supplied to the gates of the two N-channel MOS transistors 33 and 34, respectively.

Here, it is assumed that "L" data is input from terminal 16 during the data input period, and that the "L" level voltage is higher than the ground voltage by at least the threshold voltage of the N-channel MOS transistor. . It is assumed that this data is supplied to the gates of one P-channel MOS transistor 31 and one N-channel MOS transistor 33 in FIG. At this time, the P-channel MOS transistor 31 conducts sufficiently, but the N-channel MOS transistor 33, which should be non-conductive, also conducts slightly. Therefore, the input bus output signal is set to “L”,
During the period when the other P-channel MOS transistor 32 is conducting, a through current flows between the power supply voltage VDD and the ground voltage. However, even during the data input period, when the input bus output signal is "H", the other P-channel MOS transistor 32 is non-conductive, so that a through current does not flow between the power supply voltage VDD and the ground voltage. It stops flowing.

That is, in the semiconductor integrated circuit according to the first embodiment, the NOR circuit 18 is controlled by a pulse signal, and during the period in which the pulse signal is supplied, depending on the state of the input signal. Since a through current flows, current consumption can be reduced as compared with a conventional circuit in which a through current may flow during the entire data input period.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a schematic configuration when the present invention is applied to a semiconductor integrated circuit for a one-chip microcomputer as in the case of FIG. The semiconductor integrated circuit shown in FIG. 3 is different from the semiconductor integrated circuit of the first embodiment shown in FIG.
The point where the MOS type NAND circuit 20 is provided, and the pulse-shaped input bus output signal of “H” from the CPU 12 during the data input period is supplied to the bus buffer 15 and the NAND circuit 20.
Is input to the

As shown in FIG. 4, the CMOS type NAND circuit 20 has two P-type switches between the power supply voltage VDD and the output OUT.
The configuration is such that the sources and drains of the channel MOS transistors 35 and 36 are inserted in parallel, and the sources and drains of two N-channel MOS transistors 37 and 38 are inserted in series between the output OUT and the ground voltage. ing. And
Input data from the terminal 16 and an input bus output signal from the CPU 12 are supplied to the gates of the two P-channel MOS transistors 35 and 36, respectively. Also the terminal
Input data from 16 and an input bus output signal from the CPU 12 are supplied.

In the semiconductor integrated circuit according to the second embodiment, "H" data is input from terminal 16 during the data input period, and the "H" level voltage is higher than the power supply voltage by the threshold voltage of the P-channel MOS transistor. Assume that the value is lower than the voltage. Then, this data is applied to one P-channel MOS transistor 35 and one N-channel MOS transistor 35 in FIG.
It is assumed that the power is supplied to the gate of the channel MOS transistor 38. At this time, the N-channel MOS transistor 38 sufficiently conducts, but the P-channel MOS transistor 35, which should be non-conductive, also slightly conducts.

Therefore, during the period when the input bus output signal is at "H" and the other N-channel MOS transistor 37 is conducting, a through current flows between the power supply voltage VDD and the ground voltage. However, even during the data input period, the other N-channel MOS transistor 37 is non-conductive during the period when the input bus output signal is "L".
No through current flows between the power supply voltage VDD and the ground voltage.

That is, also in the semiconductor integrated circuit according to the second embodiment, the NAND circuit 20 is controlled by the pulse signal, and during the period in which the pulse signal is supplied, the NAND circuit 20 is controlled by the state of the input signal. Since the through current is caused to flow, the current consumption can be reduced as compared with the conventional circuit in which the through current may flow during the entire data input period.

In the semiconductor integrated circuits according to the first and second embodiments, a tri-state buffer circuit can be used instead of the clocked inverter 17. Of course, the operation of the tristate buffer circuit is controlled based on the output of the input / output data latch 13.

FIG. 5 is a block diagram showing a schematic configuration of a one-chip microcomputer semiconductor integrated circuit according to a third embodiment of the present invention. In this semiconductor integrated circuit, an A / D converter 21 is added to the one shown in FIG. 1 in order to use the input / output terminal also for inputting an analog signal.

The A / D converter 21 converts an analog signal input from the terminal 16 into a digital signal and outputs the digital signal to the data bus 11. The conversion operation is performed by the A / D converter output from the CPU 12. It is controlled based on the D conversion signal.

Also in the semiconductor integrated circuit according to the third embodiment, the same reason as in the first embodiment shown in FIG. 1, that is, the NOR circuit 18 is controlled by a pulse signal, and Since a through current flows depending on the state of the input signal during the period in which the pulse signal is supplied, compared with the conventional circuit in which the through current may flow during the entire data input period. Current consumption can be reduced.

Further, in the semiconductor integrated circuit according to the third embodiment, during the period when data is input from the terminal 16,
An "L" pulse input bus output signal is supplied to the NOR circuit 18. When the input bus output signal is "H", no data is supplied from the bus buffer 15 to the data bus 11.

Therefore, when the input bus output signal is at "H", the CPU 12 supplies the A / D converter 21 with the A / D signal.
By providing a conversion signal, A / D conversion of an analog signal input from the terminal 16 can be performed.

As described above, in the semiconductor integrated circuit according to the third embodiment, the analog use permission latch as in the conventional circuit shown in FIG. 9 is not required, and the chip size can be reduced accordingly. .

FIG. 6 is a block diagram showing a schematic configuration of a semiconductor integrated circuit for a one-chip microcomputer according to a fourth embodiment of the present invention. In this semiconductor integrated circuit, an A / D converter 21 is added to the one shown in FIG. 3 similarly to FIG. 5 in order to use the input / output terminal also for inputting an analog signal.

Also in the semiconductor integrated circuit according to this embodiment, for the same reason as that of the third embodiment shown in FIG. 5, the current consumption can be reduced as compared with the conventional circuit, and FIG. The analog use permission latch as in the conventional circuit shown is unnecessary, and the chip size can be reduced accordingly.

In the semiconductor integrated circuits according to the third and fourth embodiments, a tri-state buffer circuit can be used instead of the clocked inverter 17.

[0044]

As described above, according to the present invention,
It is possible to reduce current consumption when the input / output terminal is used as an input terminal. Furthermore, when the input / output terminal is used not only as an input terminal but also for inputting an analog signal, the chip size can be made smaller than in the conventional case.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration according to a first embodiment in which the present invention is applied to a semiconductor integrated circuit for a one-chip microcomputer.

FIG. 2 is a detailed circuit diagram of a CMOS NOR circuit used in the semiconductor integrated circuit of FIG. 1;

FIG. 3 is a block diagram showing a schematic configuration according to a second embodiment in which the present invention is applied to a semiconductor integrated circuit for a one-chip microcomputer;

FIG. 4 is a detailed circuit diagram of a CMOS type NAND circuit used in the semiconductor integrated circuit of FIG. 3;

FIG. 5 is a block diagram showing a schematic configuration according to a third embodiment in which the present invention is applied to a semiconductor integrated circuit for a one-chip microcomputer.

FIG. 6 is a block diagram showing a schematic configuration according to a fourth embodiment in which the present invention is applied to a semiconductor integrated circuit for a one-chip microcomputer.

FIG. 7 is a block diagram showing a schematic configuration of a conventional one-chip microcomputer semiconductor integrated circuit using input / output terminals.

FIG. 8 is a diagram showing input voltage-current characteristics of a CMOS inverter used in the semiconductor integrated circuit of FIG. 7;

FIG. 9 is a block diagram showing a schematic configuration of a conventional one-chip microcomputer semiconductor integrated circuit in which an input / output terminal is also used for inputting an analog signal.

[Explanation of symbols]

 11 data bus, 12 CPU, 13 input / output data latch, 14 output data latch, 15 bus buffer, 16 input / output terminal, 17 clocked inverter, 18 CMOS type NOR circuit, 19 inverter , 20 ... CMOS type NAND circuit, 21 ... A / D converter.

Claims (2)

[Claims] An input / output terminal; a data holding circuit for holding data to be output from the terminal; and a data holding circuit provided between the data holding circuit and the terminal. A data output circuit that outputs data corresponding to the held data and outputs are set to a high-impedance state during other periods, and a pulse signal is supplied, and the pulse signal is supplied. A data acquisition circuit for outputting data corresponding to data supplied to the terminal during a certain period. 2. An input / output terminal, a data holding circuit for holding data to be output from the terminal, and a data holding circuit provided between the data holding circuit and the terminal. A data output circuit that outputs data corresponding to the held data and outputs are set to a high-impedance state during other periods, and a pulse signal is supplied, and the pulse signal is supplied. A data capture circuit for internally outputting data corresponding to the data supplied to the terminal during a certain period; an A / D conversion circuit for converting an analog signal supplied to the terminal to digital data and outputting the digital data to the inside; A semiconductor integrated circuit characterized by comprising: