JPH0268871A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0268871A JPH0268871A JP63218513A JP21851388A JPH0268871A JP H0268871 A JPH0268871 A JP H0268871A JP 63218513 A JP63218513 A JP 63218513A JP 21851388 A JP21851388 A JP 21851388A JP H0268871 A JPH0268871 A JP H0268871A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- integrated circuit
- hybrid integrated
- lead pins
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明はデュアル・イン・ライン（以下ＤＩＰという）
型の混成集積回路装置に係り、特に、リードピンを数層
して薄形化を図った混成集積回路装置に関する。[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention is a dual-in-line (hereinafter referred to as DIP)
The present invention relates to a type of hybrid integrated circuit device, and particularly to a hybrid integrated circuit device in which several layers of lead pins are used to reduce the thickness of the device.
（従来の技術）
従来、この種のＤＩＰ型の混成集積回路装置は第２図（
Ａ）〜（Ｅ）に示す製造工程により製造され、まず第２
図（Ａ）に示すように、絶縁基板１の表裏両面に図示し
ない配線層を形成し、この配線層の所要箇所上に抵抗や
コンデンナ等の電子回路素子２．２・・・をそれぞれ載
置し、ハンダ３により固着して所要の電子回路を構成す
る。(Prior Art) Conventionally, this type of DIP type hybrid integrated circuit device is shown in Fig. 2 (
Manufactured by the manufacturing steps shown in A) to (E), first the second
As shown in Figure (A), a wiring layer (not shown) is formed on both the front and back surfaces of the insulating substrate 1, and electronic circuit elements 2, 2, such as resistors and capacitors, etc. are placed on the required parts of this wiring layer, respectively. Then, it is fixed with solder 3 to form a required electronic circuit.
次に第２図（Ｂ）に示すように、絶縁基板１の図中左右
端部のランド（図示せず）に、Ｆ形りリップ状の所要数
のリードピン４．４・・・のＦ形頭部の開口を嵌入し、
この嵌入部をハンダ３により固着する。Next, as shown in FIG. 2(B), a required number of F-shaped lip-shaped lead pins 4. Insert the opening in the head,
This fitted portion is fixed with solder 3.
この侵第２図（Ｃ）に示すように、各リードピン４．４
・・・の軸方内申局部を軸直角方向両側（図中左右両側
）から左右一対の挟持治具５ａ、５ｂの複数対によりそ
れぞれ挟持し、第２図（Ｄ）に示すように、各リードピ
ン４，４・・・の先端部４ａ。As shown in Figure 2 (C), each lead pin 4.4
... are held by a plurality of pairs of left and right holding jigs 5a and 5b from both sides in the direction perpendicular to the axis (left and right sides in the figure), and as shown in FIG. 2(D), each lead pin 4, 4... tip portion 4a.
４ａを外向きの１−字状にそれぞれ折曲する。4a are bent outward in a 1-shape.
そして、第２図（Ｅ）に示すように各リードピン４．４
のＬ字状折曲先端部４ａ、４ａをマザー基板６上に載置
し、ハンダ３により固着して立設している。Then, as shown in FIG. 2(E), each lead pin 4.4
The L-shaped bent end portions 4a, 4a of are placed on the motherboard 6 and fixed with solder 3 so as to stand upright.
（発明が解決しようどする課題）
しかしながら、このような従来の混成集積回路装置では
第２図（［））に示すように各リードピン４，４・・・
の先端部を外向きＬ字状にそれぞれ折１１１するために
、同図（Ｃ）に示すように一対の挟持治具５ａ、５ｂの
一方例えば５ｂ・・・を絶縁基板１の裏面（図中下面）
下方に挿入して固定しなければならず、その結果、同図
（Ｄ）に示すように、絶縁基板１の裏面に固着した電子
回路素子２，２・・・の図中下面下方にて、一方の挟持
治具５ｂ、５ｂ・・・を挿入せしめる対向間隙ｈａを最
低限確保する必要があり、混成集積回路装置の薄形化を
妨げている。(Problems to be Solved by the Invention) However, in such a conventional hybrid integrated circuit device, as shown in FIG. 2 ([)], each lead pin 4, 4...
In order to fold 111 the tips of the insulating substrate 1 into an outward L-shape, one of the pair of clamping jigs 5a, 5b, for example 5b, is placed on the back side of the insulating substrate 1 (in the figure), as shown in FIG. bottom surface)
As a result, as shown in the figure (D), below the bottom surface of the electronic circuit elements 2, 2, etc. fixed to the back surface of the insulating substrate 1, as shown in FIG. It is necessary to ensure at least the opposing gap ha into which one of the holding jigs 5b, 5b, .
（こで本発明は上記事情を考慮してなされたもので、そ
の目的は薄形化を図ることができる混成集積回路装置を
提供することにある。(The present invention has been made in consideration of the above circumstances, and its object is to provide a hybrid integrated circuit device that can be made thinner.
（課題を解決するための手段）
本発明は、上記従来例の課題が、Ｆ形のり−ドピンの脚
部を絶縁基板の板厚方向に延出させているために、リー
ドピンを含む絶縁基板全体の厚さが厚くなることに着目
してなされたものである。(Means for Solving the Problems) The present invention solves the problem of the above-mentioned conventional example in that the leg portions of the F-shaped glued pins extend in the thickness direction of the insulating substrate. This was done by focusing on the fact that the thickness of the material becomes thicker.
すなわち本発明は、電子回路素子を絶Ｒ基板の表裏両面
に実装し、この絶縁基板をそのランドに固着されたリー
ドピンを介してマザー基板上に立設する混成集積回路装
置において、上記リードピンは、その脚部を上記絶Ｒ基
板の表裏面に平行方向外方に延出させると共に、その脚
部先端部を上記マザー基板上に立設自在に折曲してなる
ことを特徴とする。That is, the present invention provides a hybrid integrated circuit device in which electronic circuit elements are mounted on both the front and back sides of an insulating board, and this insulating board is erected on a motherboard via lead pins fixed to the lands thereof, wherein the lead pins are The leg portion extends outward in a direction parallel to the front and back surfaces of the above-mentioned round board, and the tip end of the leg portion is bent so as to be freely erected on the mother board.
（作用）
リードピンはその脚部を絶縁基板の表裏面に対して、平
行方向外方に延出させ１絶縁基板の板厚方向には延出さ
せないので、このリードピンを含む絶縁基板全体の厚さ
の薄形化を図ることができる。(Function) The leg of the lead pin extends outward in the parallel direction to the front and back surfaces of the insulating substrate, and does not extend in the thickness direction of the insulating substrate, so the overall thickness of the insulating substrate including this lead pin can be made thinner.
したがって、本発明によれば、この薄形化した絶縁基板
をマザー基板上に立設させてなる混成集積回路装置の全
体の厚さを減厚し、薄形化を図ることができる。Therefore, according to the present invention, it is possible to reduce the overall thickness of a hybrid integrated circuit device in which the thinned insulating substrate is placed upright on a motherboard, thereby achieving thinning.
（実施例）
以下本発明の一実施例を第１図（Ａ）〜（Ｅ）に基づい
て説明する。(Example) An example of the present invention will be described below based on FIGS. 1(A) to (E).
まず、第１図（Ａ）に示すように、第２図（Ａ）と同様
に絶縁基板１の表裏両面に図示しない配線層を形成し、
この配線層の所要箇所上に抵抗やコンデンサ等の電子回
路素子２，２・・・を載置し、その載置箇所をハンダ３
により固着して所要の電子回路を構成する。First, as shown in FIG. 1(A), wiring layers (not shown) are formed on both the front and back surfaces of the insulating substrate 1 in the same manner as in FIG. 2(A).
Electronic circuit elements 2, 2, etc. such as resistors and capacitors are placed on the required locations of this wiring layer, and the placement locations are covered with solder 3.
to form the required electronic circuit.
次に第１図（Ｂ）に示すようにほぼユ字形のリードピン
１０のほぼユ字形の頭部開口を絶縁基板１の図中左右端
部のランドに外側方からそれぞれ嵌入させ、そのに入部
をそれぞれハンダ３により固着している。Next, as shown in FIG. 1(B), the approximately U-shaped head openings of the approximately U-shaped lead pins 10 are fitted into the lands at the left and right ends of the insulating substrate 1 from the outside, respectively, and the openings are inserted into the lands at the left and right ends of the insulating substrate 1 in the figure. Each is fixed with solder 3.
各リードピン１０．１０・・・はそのユ字形横棒の脚部
１０ａ、１０ａ・・・を絶縁基板１の表裏面に対して平
行方向、すなわち、図中水平方向外方へ所要長それぞれ
延出させ、絶縁基板１の板厚方向には延出させていない
。Each lead pin 10, 10... has its U-shaped horizontal bar leg portions 10a, 10a... extending in a direction parallel to the front and back surfaces of the insulating substrate 1, that is, horizontally outward in the figure, for a required length. and does not extend in the thickness direction of the insulating substrate 1.
したがって、第１図（Ｃ）に示すように各り一ドピン１
０．１０・・・の脚部１０ａ、１０ａ・・・の先端部を
外向きＬ字状に折曲する３１合には上下一対の挟持治具
５ａ、５ｂの複数対により、各リードピン１０．１０・
・・の脚部１０ａ、１０ａを図中上下方向から挟持する
ことができると共に、例えば上下一対のブレス治具１１
ａ、１１ｂの複数対の上下方向のプレス操作により、ク
ランク状に折曲することができる。Therefore, as shown in FIG. 1(C), each doping pin 1
When the tips of the leg portions 10a, 10a, . . . 0.10. 10・
The legs 10a, 10a of .
By pressing multiple pairs of a and 11b in the vertical direction, it can be bent into a crank shape.
その結果、第１図（Ｄ）に示すように各リードピン１０
．１０・・・の折曲先端部１０ａ、１０ａ・・・の底面
と、絶縁基板１の裏面（図中下面）に実装した電子回路
素子２の下面との対向間ｌ！！Ｉｈｂを、第２図で示す
従来の混成集積回路装置の対向間隙ｈａに対して大幅に
狭隘化することができ、リードピン１０．１０・・・を
含む絶縁基板１全体の厚さを減厚し、薄形化することが
できる。As a result, as shown in FIG. 1(D), each lead pin 10
．． 10... and the bottom surface of the electronic circuit element 2 mounted on the back surface (lower surface in the figure) of the insulating substrate 1 (l!)! ! Ihb can be made significantly narrower than the opposing gap ha of the conventional hybrid integrated circuit device shown in FIG. , it can be made thinner.
したがって、このように薄形化された絶縁基板１を第１
図（Ｅ）に示すようにマ１ｆ−Ｕ板６上に起立させ、そ
の起ひ箇所をハンダ３により固着することにより、この
混成集積回路装置全体の厚さを、第２図で示す従来例の
ものに比して、対向間隙ｈａを同ｈｂに狭隘化した分だ
け、薄形化を図ることができる。Therefore, the insulating substrate 1 thinned in this way is
As shown in FIG. 2, the thickness of the entire hybrid integrated circuit device can be reduced by raising it up on the 1f-U board 6 and fixing the raised portion with solder 3, as shown in FIG. Compared to the above, it is possible to reduce the thickness by narrowing the facing gap ha to the same hb.
以上説明したように本発明は、絶縁基板をマザー基板上
に立設じしめるリードピンの脚部を、上記絶縁基板の表
裏面に対して平行方向外方に延出させ絶縁基板の板厚方
向には延出させないので、このリードピンを含む絶縁基
板全体の厚さの薄形化を図ることができる。As explained above, the present invention extends the leg portions of the lead pins that erect the insulating substrate on the motherboard in a direction parallel to the front and back surfaces of the insulating substrate in the thickness direction of the insulating substrate. Since the lead pins are not extended, it is possible to reduce the thickness of the entire insulating substrate including the lead pins.
したがって本発明によれば、この薄型化した絶縁基板を
マザー基板に立設せしめる混成集積回路装置全体の厚さ
の薄型化を図ることができる。Therefore, according to the present invention, it is possible to reduce the thickness of the entire hybrid integrated circuit device in which the thinned insulating substrate is placed upright on the motherboard.
第１図（Ａ）〜（Ｅ）は本発明に係る混成集積回路装置
の一実施例の製造工程の一部を示す工程図、第２図（Ａ
）〜（Ｅ）は従来の混成集積回路装置の製造工程の一部
を示す工程図である。1(A) to (E) are process diagrams showing a part of the manufacturing process of an embodiment of the hybrid integrated circuit device according to the present invention, and FIG.
) to (E) are process diagrams showing a part of the manufacturing process of a conventional hybrid integrated circuit device.
１・・・絶縁基板、２・・・電子回路素子、３・・・ハ
ンダ、５ａ、５ｂ・・・挟持治具、６・・・マザー基板
、１０・・・リードピン、１０ａａ・・・脚部、ｈａ、
ｈｂ・・・対向間隙。DESCRIPTION OF SYMBOLS 1... Insulating board, 2... Electronic circuit element, 3... Solder, 5a, 5b... Holding jig, 6... Motherboard, 10... Lead pin, 10aa... Leg part ,ha,
hb...Opposing gap.
出願人代理人 波 多 野 久Applicant's agent Hisashi Hatano
Claims (1)
基板をそのランドに固着されたリードピンを介してマザ
ー基板上に立設する混成集積回路装置において、上記リ
ードピンは、その脚部を上記絶縁基板の表裏面に平行方
向外方に延出させると共に、その脚部先端部を上記マザ
ー基板上に立設自在に折曲してなることを特徴とする混
成集積回路装置。In a hybrid integrated circuit device in which electronic circuit elements are mounted on both the front and back surfaces of an insulating substrate, and this insulating substrate is installed upright on a motherboard via lead pins fixed to the lands, the lead pins have their legs connected to the insulating substrate. 1. A hybrid integrated circuit device, characterized in that the legs extend outward in a direction parallel to the front and back surfaces of a substrate, and the tips of the legs are bent so as to be freely erected on the mother substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63218513A JPH0268871A (en) | 1988-09-02 | 1988-09-02 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63218513A JPH0268871A (en) | 1988-09-02 | 1988-09-02 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0268871A true JPH0268871A (en) | 1990-03-08 |
Family
ID=16721105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63218513A Pending JPH0268871A (en) | 1988-09-02 | 1988-09-02 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0268871A (en) |
-
1988
- 1988-09-02 JP JP63218513A patent/JPH0268871A/en active Pending
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