JPH09274065A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which can prevent the short circuit between lead terminals when electric-characteristic test is performed. SOLUTION: A plurality of outlet ports 3 are formed in the zigzag pattern in a package 1 of an LSI. A checking terminal 4 for contact with an inspecting probe is drawn out through the outlet port 3. The checking terminal 4 is approximately flush with an upper surface part 1e of the package 1, and the tip of the terminal forms a hook shape. Therefore, the special allowance is formed between the respective checking terminals, and the erroneous contact of the probe can be prevented. Furthermore, the dimensions of the outer shape of the LSI, when the checking terminals are not provided, are not changed, and the extra mounting space for the checking terminal is not required. Furthermore, since the tip is formed in the hook shape, the probe can be brought into contact with the checking terminal readily and securely and becomes hard to be disengaged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called IC (Integrated Circuit) in which a semiconductor chip to which a plurality of lead terminals are connected is sealed with a resin package so that a part of the lead terminals is exposed to the outside. LSI (Large Scale)
IC) and other semiconductor devices.

[0002]

2. Description of the Related Art ICs are subjected to various characteristic tests to ensure reliability. One of them is an electrical characteristic test. The electrical characteristic test is usually performed by bringing an inspection probe connected to a logic analyzer into contact with a lead terminal and observing an input / output signal value of the IC in the logic analyzer.

However, the distance between the lead terminals of the IC is narrow, and the metal surface of each lead terminal is exposed. Therefore, when trying to bring the inspection probe into contact with a certain lead terminal, the inspection probe is likely to accidentally make contact with the adjacent lead terminal. As a result, the lead terminals are often short-circuited, and the electrical characteristic values cannot often be accurately observed.

Further, each lead terminal of the IC has a small exposed portion when the IC is mounted on the wiring board. Therefore, it is difficult to bring the inspection probe into contact with the lead terminal, and the burden on the tester is large. Therefore,
In Japanese Utility Model Laid-Open No. 4-77248, as shown in FIG. 11, a configuration is proposed in which a check terminal 201 extending upward from each lead terminal 200 is provided for an electrical characteristic test.

[0005]

However, in the technique disclosed in the above publication, a plurality of check terminals 201 are provided.
Are placed close to each other as they are exposed,
The inconvenience that the inspection probe easily contacts the lead terminal adjacent to the target lead terminal remains.

In addition, recently, the spacing between the lead terminals 200 is becoming narrower, such as 1.0 (mm), in response to the demand for higher board mounting density. When the spacing between the lead terminals 200 becomes narrower, the spacing between the check terminals 201 also becomes narrower. Therefore, erroneous contact of the probe may occur more frequently. Further, if the interval between the check terminals 201 becomes narrower, it is necessary to make the check terminals 201 thinner accordingly. In such a case, the check terminal 201 is deformed when the probe is brought into contact with the check terminal 201,
The check terminals 201 may be short-circuited to each other. As a result, not only the electrical characteristic value cannot be accurately observed, but also the circuit operation may be hindered.

Further, the tester needs to work while concentrating his nerves so that a short circuit does not occur between the lead terminals 200, which places a heavy burden on the tester. Therefore, there has been a demand for a technique capable of preventing a short circuit between the lead terminals 200 during the test. Therefore, an object of the present invention is to solve the above technical problems and to provide a semiconductor device capable of preventing a short circuit between lead terminals during an electrical characteristic test.

[0008]

According to a first aspect of the invention for achieving the above object, a semiconductor component, a lead terminal connected to the semiconductor component, and a part of the lead terminal are exposed to the outside. Insulating container which has sealed the semiconductor component as described above, and a lead connecting portion connected to the lead terminal,
And an electrical characteristic that has a probe contact portion to be brought into contact with the inspection probe, and is drawn out through a component of the container so that the inspection probe can access the probe contact portion from outside the container. A semiconductor device including a check terminal for testing.

In this structure, the check terminal connected to the lead terminal is, so to speak, in a state of being implanted in the component of the container. Therefore, when the inspection probe is brought into contact with the probe contact portion of the check terminal, the check terminal can be prevented from being deformed by the reinforcing action of the container even if the check terminal is thin. Therefore, contact between the check terminals can be prevented. As a result, a short circuit between the lead terminals can be prevented.

The invention according to claim 2 is the semiconductor device according to claim 1, wherein the check terminals of the adjacent lead terminals are drawn out at positions displaced from each other in the longitudinal direction of the lead terminals. In this configuration, the check terminals of the adjacent lead terminals are drawn out at positions displaced from each other in the longitudinal direction of the lead terminals. Therefore, even if the space between adjacent check terminals is small,
There is sufficient space between adjacent check terminals. As a result, the inspection probe can be easily brought into contact with the target check terminal, and the lead terminals are not short-circuited.

According to a third aspect of the present invention, the probe contact portion of the check terminal is a hook portion which is provided at a tip portion of the check terminal and on which the inspection probe can be hooked. The semiconductor device according to claim 2. In this configuration, the tip of the check terminal is a hook. Therefore, the inspection probe can be brought into contact with the check terminal easily and surely. In addition, the inspection probe is less likely to come off the check terminal.

According to a fourth aspect of the present invention, the container is formed with a lead-out hole through which the check terminal can pass, and the check terminal passes through the lead-out hole to a position where it does not project from the surface of the container. The semiconductor device according to claim 1, 2 or 3, wherein the semiconductor device is drawn out. In this configuration, the check terminal is drawn out through the drawing hole formed in the container. Therefore, if the inspection probe is inserted into the extraction hole, the inspection probe can be brought into contact with the check terminal easily and surely.

Further, since the check terminal does not protrude from the container surface, it has the same external dimensions as a normal semiconductor device not including the check terminal. Therefore, even when this semiconductor device is mounted on the substrate, an extra mounting space for the check terminals is unnecessary.

[0014]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a plan view of an LSI according to an embodiment of the present invention. This L
The SI is a flat package type and includes a package 1 having a substantially square shape in a plan view. From the side surfaces 1a, 1b, 1c, 1d corresponding to the sides of the square, a plurality of lead terminals 2 are drawn out substantially in parallel. The lead terminal 2 includes an exposed portion 2a and a board mounting portion 2b on the tip side of the exposed portion 2a. When this LSI is mounted on a wiring board, the board mounting portion 2b is mounted on the wiring board by soldering or the like.

A plurality of extraction holes 3 are formed in the upper surface 1e of the package 1. The lead-out hole 3 is for pulling out the check terminal 4 toward the upper surface 1e of the package 1, and is provided for each lead terminal 2. More specifically, each lead terminal 2 includes the exposed portion 2a and the board mounting portion 2b, and a sealed portion 2c sealed inside the package 1. The check terminal 4 is for contacting the inspection probe during the electrical characteristic test of the LSI, and branches from the sealed portion 2c toward the upper surface 1e of the package 1. The extraction hole 3 is the upper surface 1e of the package 1.
The cross-sectional shape is substantially circular and uniform from the position to the sealed portion 2c.

The lead-out holes 3 are arranged in zigzag.
More specifically, the extraction holes 3 corresponding to the lead terminals 2 adjacent to each other are formed at positions displaced from each other in the longitudinal direction of the lead terminals 2. For example, the extraction holes 31 and 32 adjacent to each other are offset from each other in the direction A along the direction A orthogonal to the side surface 1 a of the package 1. More specifically, the drawing hole 31 is formed closer to the side surface 1a than the drawing hole 32.

FIG. 2 is a sectional view taken along the line II-II of the LSI shown in FIG. The package 1 includes an upper package portion 11 and a lower package portion 12, and is made of an insulating plastic resin such as epoxy resin. A concave portion is formed on the side of the upper package portion 11 facing the lower package portion 12. The package 1 has an internal space 13 surrounded by the recess and the lower package portion 12. The LSI chip 5 is housed in the internal space 13. The sealed portion 2c of the lead terminal 2 is connected to the LSI chip 5 via a bonding wire 6. The lead terminal 2 includes an upper package portion 11 and a lower package portion 12
It is pulled out to the outside through the space between.

As described above, the check terminal 4 branches from the middle of the sealed portion 2c of the lead terminal 2 toward the upper surface 1e of the upper package portion 11. This is because the lower surface portion 1f of the lower package portion 12 is mounted when the LSI is mounted on the wiring board.
This is because it is mounted with facing down. The tip of the check terminal 4 is pulled out to a position substantially flush with the upper surface 1e of the upper package portion 11. That is, the check terminal 4 is pulled out from the package 1 to a position where it does not project.

FIG. 3 is a diagram for explaining the structure of the check terminal 4 in more detail. The check terminal 4 includes a connecting portion 4a and a standing portion 4b. The check terminal 4 is connected to the sealed portion 2c of the lead terminal 2 via the connection portion 4a in a state where the upright portion 4b is upright with the base point portion 4c as a base point. Probe contact portion 4 corresponding to the tip of the upright portion 4b
d is formed in a hook shape. The hook is oriented in the same direction as the probe contact portion 4d of the adjacent check terminal 4 which is orthogonal to the longitudinal direction of the lead terminal 2. That is, the hook is oriented in the direction of the arrow B in FIG.

As described above, the check terminal 4 is, so to speak, in a state of being embedded in the package 1. Therefore, when the inspection probe is brought into contact with the probe contact portion 4d of the check terminal 4, even if the check terminal 4 is thin, the check terminal 4 can be prevented from being deformed. Therefore, no short circuit occurs between the check terminals 4.
Also, the adjacent check terminals 4 are drawn out at positions displaced from each other in the longitudinal direction of the lead terminal 2. Moreover, the probe contact portion 4d corresponding to the tip of the check terminal 4 is orthogonal to the longitudinal direction of the lead terminal 2 and faces the same direction as the probe contact portion 4d of the adjacent check terminal 4. Therefore, even if the space between the adjacent check terminals 4 is narrow, a sufficient space can be provided between the adjacent check terminals 4. As a result, the inspection probe can be easily brought into contact with the target check terminal 4, and a short circuit between the lead terminals 2 can be prevented.

Furthermore, since the check terminal 4 does not protrude from the upper surface of the package 1, the external dimensions of this LSI can be made substantially the same as those of a normal LSI having no check terminal 4. Therefore, even when the LSI is mounted on the wiring board, it is not necessary to secure an extra mounting space for the check terminals 4. Furthermore, since the probe contact portion 4d corresponding to the tip of the check terminal 4 is formed in a hook shape, the inspection probe can be easily hooked on the check terminal 4. Thereby, the inspection probe can be brought into contact with the check terminal 4 easily and surely. In addition, the inspection probe is less likely to come off. Therefore, the electrical characteristic value of this LSI can be easily and surely obtained.

Next, the manufacturing process of the LSI will be described. FIG. 4 is a plan view of a lead frame used for manufacturing an LSI. This lead frame is created by pressing the frame substrate 7 extending to the left and right sides in FIG. In the vicinity of the center of the lead frame formed on one frame frame 8, the chip mount portion 7
1 is provided. The chip mount portion 71 has a substantially square shape, and support portions 72a, 72b, 72c, 72d extending from the frame substrate 7 are connected to the four corners thereof.

Each side 71a, 71 of the chip mount portion 71
The tips of a plurality of lead terminal portions 73 extending inward from the frame substrate 7 face b, 71c, and 71d, respectively. The lead terminal portion 73 extends inward in parallel to the edges 8 a to 8 d of the frame frame 8 in parallel with each other, and each edge 71 of the chip mount portion 71 extends from the middle portion thereof.
The shape is such that it converges toward a to 71d. That is, the shape is such that it is radially diffused with the chip mount portion 71 as the center. The lead terminal portion 73 finally becomes the lead terminal 2.

From the middle of the lead terminal portion 73, the check terminal portions 74 which finally become the check terminals 4 all branch to the same side. The check terminal portion 74 is branched from a portion (hereinafter referred to as “vertical portion”) 73a of the lead terminal portion 73, which extends in a direction perpendicular to the edges 8a to 8d of the frame 8. The branch positions of the check terminal portions 74 branched from the adjacent lead terminal portions 73 are displaced along the longitudinal direction of the vertical portion 73a of the lead terminal portion 73. For example, check terminal portion 741
The branch position of is closer to the edge 8a of the frame 8 than the branch positions of the adjacent check terminal portions 742.
Furthermore, the check terminal portion 741 of the check terminal portion 742
The distance from the edge portion 8a of the frame frame 8 at the branch position of the check terminal portion 743 adjacent to the opposite side is substantially equal to the distance from the edge portion 8A of the check terminal portion 741.

FIG. 5 is a diagram for explaining the structure of the check terminal portion 74 in more detail. Check terminal part 74
Has a connecting portion 74a and a standing portion 74b. The connection portion 74a is formed by vertically branching from the vertical portion 73a of the lead terminal portion 73. The upright portion 74b is formed so as to be perpendicular to the connecting portion 74a, that is, parallel to the vertical portion 73a of the lead terminal portion 73. The tip 74d of the check terminal portion 74 has a hook shape. The hook is oriented in a direction away from the lead terminal portion 73 to which the check terminal portion 74 is connected.

First, as shown in FIG. 6A, the pressing die 9 is placed and fixed on the upper surface of the lead frame as described above. More specifically, each edge portion 9a of the pressing die 9 is
9b, 9c and 9d are the base point portions 74c of the check terminal portion 74.
Place it along the line. The pressing die 9 has a substantially square shape. Edges 9a, 9b, 9c of the pressing die 9,
Each of 9d has a concave portion 91 and a convex portion 92. The concave portions 91 and the convex portions 92 are alternately formed so as to correspond to the displacement of the base point portion 74c of the check terminal portion 74. More specifically, for example, as shown in FIG. 7, each of the base point portions 74c of the check terminal portions 741, 742, 743.
A concave portion 91a, a convex portion 92a, and a concave portion 91b of the edge portion 9a are formed so as to follow.

Next, as shown in FIG. 6 (b), the lifting die 100 is placed below the lead frame. As shown in FIG. 8 (a), the lifting die 100 includes a frame body 101 having a substantially square planar shape. Frame body 101
Each of the inner edge portions 102, 103, 104 and 105 has a concave portion 110 and a convex portion 111. The concave portion 110 and the convex portion 111 are the base points 74 c of the check terminal portion 74.
They are alternately formed so as to correspond to the deviation of. More specifically, for example, as shown in FIG.
The concave portion 91a, the convex portion 92a and the concave portion 91b of
The convex portion 111a, the concave portion 110a, and the convex portion 111b are provided on the edge portion 102.

Lifting members 106 are attached to the concave portions 110 and the convex portions 111 of the respective edge portions 102 to 105, as shown in FIG. 8 (a). Lifting member 106
As shown in FIG. 8B, the upper surface portion 106a and the front surface portion 1
It is a rectangular parallelepiped including 06b, the side surface portion 106c, and the back surface portion 106d, and projects upward. Each edge 1 of the frame 101
The length r of the lifting member 106 in the direction orthogonal to 02 to 105 is substantially the same as the length of the rising portion 74b of the check terminal portion 74.

When the lifting die 100 is placed below the lead frame, as shown in FIG. 7, the lifting member 106 is used.
Boundary portion 106e between the upper surface portion 106a and the front surface portion 106b of the
Are arranged along the base point portion 74c of the check terminal portion 74. In this state, the lifting die 100 is moved upward. As a result, the upright portion 74b is replaced by the upright portion 74b.
The lifting member 106 having a length r substantially equal to the length b is pushed upward. At this time, the edge portions 9a to 9a of the pressing die 9 are
Since d is along the base point portion 74c, the standing portion 74b is
Using the base point portion 74c as a base point, it stands up to a position perpendicular to the horizontal plane. That is, the state is as shown in FIG.

After that, the pressing die 9 and the lifting die 1
When 00 is removed, as shown in FIG. 9, the lead frame in which the upright portions 74b of the check terminal portions 74 are raised is completed. After the lead frame is completed, as shown in FIG. 10, the chip mount portion 7 of the completed lead frame is formed.
The LSI chip 5 is mounted on the substrate 1, and the LSI chip 5 and the lead terminal portion 73 are connected by the bonding wire 6. Next, the upper package portion 11 and the lower package portion 12 are sandwiched from above and below the lead frame and pressure-bonded, and then heat treatment is performed. As a result, the package 1 is made and the sealing of the LSI chip 5 is completed.

After that, the extra frame substrate 7 of the lead frame is cut. As a result, L shown in FIG.
SI is completed. Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above-described embodiment, the probe contact portion 4d, which is the tip of the check terminal, has a hook shape. However, for example, it may have a ring shape as shown in FIG. Any shape can be adopted as long as it is a shape that can easily catch the probe for use.

In the above embodiment, the lead-out holes 3 are formed in a zigzag shape on the upper surface 1e of the package 1. For example, n (n ≧ 2) lead-out holes 3 adjacent to each other are formed in the longitudinal direction of the lead terminal 2. You may form so that the form shifted about may be repeated. Furthermore, in the above-described embodiment, the check terminal 4 is vertically drawn upward, but the present invention is not limited to such a form, and the check terminal 4 may be drawn to the outside through the package 1. For example, of the adjacent check terminals 4, one of the check terminals 4 is pulled out so as to be inclined toward the side faces 1a to 1d of the package 1, and the other check terminal 4 is placed on the side opposite to the side faces 1a to 1d of the package 1. You may make it draw out so that it may become an inclined shape. It goes without saying that this configuration also has the same effect as that of the above embodiment.

Further, in the above embodiment, the check terminal 4
Is drawn to the same height as the upper surface 1e of the package 1, but the check terminals 4 may be drawn to a position lower than the upper surface 1e, for example. It goes without saying that this configuration also has the same effect as that of the above embodiment. Furthermore, in the above embodiment, the case where the present invention is applied to a flat package type LSI has been described. However, according to the present invention, for example, SIP (Singl)
e In-Line Package) type, DIP (Dual In-Line Package)
It can be applied to various LSIs such as molds.

Furthermore, the present invention provides a TO (Transistor Outl)
Of course, it can be applied to an (ine) type IC and other semiconductor devices. Besides, it is possible to make various design changes within the scope of the technical matters described in the claims.

[0035]

As described above, according to the present invention, even when the inspection probe is brought into contact with the check terminals, the check terminals are not deformed, so that the contact between the check terminals can be prevented. As a result, it is possible to prevent a short circuit between the lead terminals. Therefore, the electrical characteristic value can be accurately obtained. As a result, the reliability of the semiconductor device can be ensured. Moreover, the tester does not need to concentrate his / her nerves on the prevention of short circuits between the lead terminals, so that the load on the tester can be reduced.

According to the second aspect of the invention, a spatial margin can be provided between the adjacent check terminals.
It is possible to prevent accidental contact of the inspection probe. Therefore, the electrical characteristic value can be accurately obtained. As a result, the reliability of the semiconductor device can be ensured. In addition, the burden on the tester can be reduced. According to the invention of claim 3, the inspection probe can be brought into contact with the check terminal easily and surely. In addition, the inspection probe is less likely to come off the check terminal. Therefore, the electrical characteristic test can be performed easily and accurately.

According to the invention described in claim 4, it is possible to obtain a semiconductor device having the same external dimensions as a normal semiconductor device not including a check terminal. Therefore, even when this semiconductor device is mounted on the substrate, an extra mounting space for the check terminals is unnecessary. Therefore, it is possible to meet the demand for higher packaging density.

[Brief description of drawings]

FIG. 1 is an LSI according to an embodiment to which the present invention is applied.
FIG.

FIG. 2 is a sectional view taken along line II-II of FIG.

FIG. 3 is a perspective view of a check terminal for explaining the check terminal in more detail.

FIG. 4 is a plan view of a lead frame used for manufacturing an LSI.

FIG. 5 is a diagram for explaining a configuration of a check terminal portion included in a lead frame.

FIG. 6 is a diagram for explaining the manufacturing process of the LSI.

FIG. 7 is an enlarged view showing the vicinity of a check terminal portion in the process of manufacturing an LSI.

FIG. 8 is a diagram showing a configuration of a lifting die. this house,
(a) is a plan view and (b) is a perspective view of a part thereof.

FIG. 9 is a diagram for explaining the manufacturing process of the LSI.

FIG. 10 is also a diagram for explaining the manufacturing process of the LSI.

FIG. 11 is a diagram for explaining a conventional check terminal.

[Explanation of symbols]

 1 Package 2 Lead terminal 3 Lead-out hole 4 Check terminal 5 LSI chip

Claims (4)

[Claims] 1. A semiconductor component, a lead terminal connected to the semiconductor component, an insulating container in which the semiconductor component is sealed so that a part of the lead terminal is exposed to the outside, and the lead terminal It has a connected lead connection part and a probe contact part to be brought into contact with the inspection probe, and passes through the composition of the container so that the probe contact part by the inspection probe can be accessed from outside the container. A semiconductor device including a check terminal for an electrical characteristic test that is drawn out. 2. The semiconductor device according to claim 1, wherein the check terminals of adjacent lead terminals are drawn out at positions displaced from each other in the longitudinal direction of the lead terminals. 3. The semiconductor according to claim 1, wherein the probe contact portion of the check terminal is a hook portion which is provided at a tip portion of the check terminal and on which an inspection probe can be hooked. apparatus. 4. The container is formed with a drawing hole through which a check terminal can be inserted, and the check terminal is drawn through the drawing hole to a position where it does not project from the surface of the container. The semiconductor device according to claim 1, claim 2, or claim 3.