JPS6149447A - Package for integrated circuit device - Google Patents
Package for integrated circuit deviceInfo
- Publication number
- JPS6149447A JPS6149447A JP17107784A JP17107784A JPS6149447A JP S6149447 A JPS6149447 A JP S6149447A JP 17107784 A JP17107784 A JP 17107784A JP 17107784 A JP17107784 A JP 17107784A JP S6149447 A JPS6149447 A JP S6149447A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- rows
- package
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
- H05K3/308—Adaptations of leads
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
本発明はパッケージ本体の両側面から多数の外部リード
を横に引出し、それからほぼ垂直に下方に曲げたデュア
ルインライン(DIP)型と同様のリード配列、但し、
リード列が3列以上の集1貢回路装置のパッケージに関
する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a dual-in-line (DIP) type lead structure in which a large number of external leads are pulled out from both sides of the package body and then bent downward almost vertically. Array, however,
The present invention relates to a package for an integrated circuit device having three or more lead rows.
口、従来の技術
現在、電子部品は大きく発展し、多くの分野で利用され
、利用分野によっては、その電子装置をよりコンパクト
にする必要を生じている。例えばポータプル用途の電子
装置、あるいは腕時計、カメラなどの電子部品の実装に
許されるスペースは非常に小さいものである。そこで電
子回路部品として半導体集積回路装置が太いに剛いられ
ている。BACKGROUND OF THE INVENTION Currently, electronic components have greatly developed and are used in many fields, and depending on the field of use, it is necessary to make the electronic devices more compact. For example, the space allowed for mounting electronic devices for portable use, or electronic components such as wristwatches and cameras, is extremely small. Therefore, semiconductor integrated circuit devices are becoming thicker and more rigid as electronic circuit components.
その半導体集積回路装置自体も高集積化が計られ、内容
も年々複雑になってきており、当然、半導体集積回路装
置のパッケージに付随するリードフレームのリード数も
多くなっている。集積回路のパッケージには、そのリー
ド配列の列の数によりシングルインライン(SIP)型
やプーアルインライン(1)IP)型があるが、リード
フレームのリード数が多くなるにつれ、現在では、リー
ド配列が2列以上のものも出現しはじめ、今後雫も多く
なる事は、明らかである。Semiconductor integrated circuit devices themselves are becoming more highly integrated and their contents are becoming more complex year by year, and naturally the number of leads on lead frames attached to semiconductor integrated circuit device packages is also increasing. Integrated circuit packages come in single-in-line (SIP) and pool-in-line (1) IP) types depending on the number of rows in the lead array, but as the number of leads on lead frames increases, the lead array Things with two or more rows have begun to appear, and it is clear that there will be more drops in the future.
ここで問題となるのはリード配列が、3列、4列と多く
なるにつれ、そのメーカーやユーザーに於ける評価試験
、測定、実装時でのソケットやプリント基板への挿入が
困難となりリード折れ、曲がり等が発生し易くなること
である。The problem here is that as the number of lead arrangements increases to 3 or 4 rows, it becomes difficult for manufacturers and users to insert the leads into sockets or printed circuit boards during evaluation tests, measurements, and mounting, leading to broken leads. This means that bending and the like are more likely to occur.
第2図は、既に出現しているリード配列が4列のパッケ
ージの従来例の正面図である。図において、パッケージ
本体1の両側面から両側に引出され、それぞれ、内側の
リード列12と外側のリード列13の全体で4列に配置
されたリードの高さ方向の長さは全べて同じである。FIG. 2 is a front view of a conventional example of a package with four rows of leads that has already appeared. In the figure, the lengths in the height direction of the leads that are pulled out from both sides of the package body 1 and arranged in four rows including the inner lead row 12 and the outer lead row 13 are all the same. It is.
ハ0発明が解決しようとする問題点
上述のような、4列に配置されたリードを正確にソケッ
トやプリント板に挿入するには、1列内のリードのずれ
(凹凸)を修正しながら4列同時に挿入しなければなら
ず、特に内側にあるリード列12のリードの修正が困難
であるだめ、非常に挿入し雑いことが問題である。Problems to be Solved by the Invention In order to accurately insert the leads arranged in four rows into a socket or printed board as described above, it is necessary to correct the misalignment (unevenness) of the leads within one row. The problem is that the lead rows must be inserted at the same time, and it is particularly difficult to correct the leads in the inner lead row 12, making the insertion process very cumbersome.
二0問題点をTW決するための技術手段上記問題点に対
し、本発明では、従来のパッケージのリードの長さが内
側と外側で同一であったのに対し、内(!11のリード
の長さを外側のリードよりも長くしている。Technical Means for Solving 20 Problems with TW To solve the above problems, in the present invention, while the lead length of the conventional package was the same on the inside and outside, the lead length of the inside (!11) The lead is longer than the outer lead.
ホ0作用
このようにすることにより、ソケットやプリント板に挿
入する際、先ず内側のリードを修正しながら正しい位置
に押入し、そのあと外側のリードを修正しながら正しい
位置に押入出来る様になる。By doing this, when inserting into a socket or printed board, you can first correct the inner lead and push it into the correct position, then correct the outer lead and push it into the correct position. .
へ、実施例 つぎに本発明を実施例により説明する。To, Example Next, the present invention will be explained by examples.
第1図は本発明の一実施例の斜視図である。図において
、パッケージ本体1の両側面から引出された多数のリー
ドは、一本置きにパッケージ本体1から近い位置と離れ
た位置で垂直に下方に曲げられて、それぞれ内1q11
のリード列2と外側のリード列3を形成している。そし
て、内側のリード列2の各リードの垂直部の長さは、外
側のリード列3の各リードの垂直部の長さより長くなっ
ている。FIG. 1 is a perspective view of an embodiment of the present invention. In the figure, a large number of leads pulled out from both sides of the package body 1 are bent vertically downward at positions close to and away from the package body 1 every other lead.
A lead row 2 and an outer lead row 3 are formed. The length of the vertical portion of each lead in the inner lead row 2 is longer than the length of the vertical portion of each lead in the outer lead row 3.
なお、本例は4列のリード列について述べているが、3
列以上のリード列に対しても本発明は同様に適用される
。Note that this example describes four lead rows, but three
The present invention is similarly applied to lead rows having more than one lead row.
ト0発明の効果
上述のとおり、内側のリードが外側のリードより長いの
で、ソケットやプリント板に実装する際、まず内・副の
リードの先端をソケットやプリント板のリード挿入穴に
挿入して正しい挿入位置を確保し、それから外側のリー
ドを挿入穴に誘導しながら押入することにより、多数の
リードが、リードの祈れ、曲りなどなく荏易に挿入笑装
できる効果がある。Effects of the Invention As mentioned above, the inner leads are longer than the outer leads, so when mounting on a socket or printed board, first insert the tips of the inner and sub leads into the lead insertion holes of the socket or printed board. By securing the correct insertion position and then inserting the outer lead while guiding it into the insertion hole, it is possible to easily insert a large number of leads without bending or bending the leads.
第1図は本発明の一実!順例の斜視図、第2図は従来の
集項回路装置のパッケージの正面図である。
]・・・・・・パッケージ本体、2.12・・・・・・
内側のリード列、3,1.3・・・・・・外側のリード
列。
第 l 図
$2Tf!JFigure 1 is the fruit of this invention! FIG. 2 is a front view of a conventional integrated circuit device package. ]...Package body, 2.12...
Inner lead row, 3,1.3...Outer lead row. Figure l $2Tf! J
Claims (1)
同様な並びの、3列以上のリード配列を有する集積回路
装置のパッケージに於いて、前記リード配列のうち内側
にあるリード配列のリードの長さを外側にあるリード配
列のリードより長くした事を特徴とする集積回路装置の
パッケージ。In an integrated circuit device package having three or more rows of lead arrays in the same arrangement as the two lead arrays of a dual-in-line package, the length of the leads of the inner lead array among the lead arrays is set to the outer side. A package for an integrated circuit device characterized by having longer leads than a certain lead arrangement.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17107784A JPS6149447A (en) | 1984-08-17 | 1984-08-17 | Package for integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17107784A JPS6149447A (en) | 1984-08-17 | 1984-08-17 | Package for integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6149447A true JPS6149447A (en) | 1986-03-11 |
Family
ID=15916585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17107784A Pending JPS6149447A (en) | 1984-08-17 | 1984-08-17 | Package for integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6149447A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4985747A (en) * | 1988-06-09 | 1991-01-15 | Oki Electric Industry Co., Ltd. | Terminal structure and process of fabricating the same |
-
1984
- 1984-08-17 JP JP17107784A patent/JPS6149447A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4985747A (en) * | 1988-06-09 | 1991-01-15 | Oki Electric Industry Co., Ltd. | Terminal structure and process of fabricating the same |
US4989318A (en) * | 1988-06-09 | 1991-02-05 | Oki Electric Industry Co., Ltd. | Process of assembling terminal structure |
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