JPH0266975A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0266975A JPH0266975A JP63218766A JP21876688A JPH0266975A JP H0266975 A JPH0266975 A JP H0266975A JP 63218766 A JP63218766 A JP 63218766A JP 21876688 A JP21876688 A JP 21876688A JP H0266975 A JPH0266975 A JP H0266975A
- Authority
- JP
- Japan
- Prior art keywords
- main
- mosfet
- terminal
- voltage
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000001514 detection method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電力用ＭＯＳ Ｆ ＥＴ絶縁ゲート型バイポ
ーラトランジスタ （以下Ｉ ＧＢＴと記す）パワート
ランジスタあるいは電力用静電誘導トランジスタなどの
電力用半導体素子を一つの半導体基板に複数個作成して
並列接続し、かつ負荷短絡状態において保護される半導
体装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to power semiconductor devices such as power MOSFET insulated gate bipolar transistor (hereinafter referred to as IGBT) power transistors or power static induction transistors. The present invention relates to a semiconductor device in which a plurality of semiconductor devices are fabricated on one semiconductor substrate and connected in parallel, and are protected in a load short-circuit condition.
並列接続された複数の電力用半導体素子を負荷短絡状態
において保護するためには、従来は第２図に示すように
、主端子１１．１２の間の並列接続素子（この場合はＩ
ＧＥＴ）の一つを主素子１３と別に電流検出用副素子１
４として用い、これには比較的抵抗値の小さい検出抵抗
１５を主婦子１２との間に直列に挿入し、その出力電圧
ｖ１を演算増幅器１６を介して素子１３．１４の駆動回
路１７に入力し、素子１３．１４の駆動電圧を制御する
。これにより、主素子１３に加わっている電圧によらな
いで副素子１４を流れる一定の電流で電流制限が行われ
る。In order to protect a plurality of parallel-connected power semiconductor devices in a load short-circuit condition, conventionally, as shown in FIG.
GET) is connected to the current detection sub-element 1 separately from the main element 13.
4, a detection resistor 15 with a relatively small resistance value is inserted in series with the main element 12, and its output voltage v1 is input to the drive circuit 17 of the elements 13 and 14 via the operational amplifier 16. and controls the driving voltage of elements 13 and 14. As a result, current is limited by a constant current flowing through the sub-element 14 regardless of the voltage applied to the main element 13.
第２図の半導体装置には以下の問題がある。 The semiconductor device shown in FIG. 2 has the following problems.
（１）演算増幅器１６を構成するために、例えばＣＭＯ
８の回路を形成する必要があり、製造プロセスが複雑と
なり、余計なチップ面積を必要とし、コストが大幅に上
昇する。(1) In order to configure the operational amplifier 16, for example, a CMO
8 circuits need to be formed, complicating the manufacturing process, requiring extra chip area, and significantly increasing costs.
（２）例えばモータ負荷の起動時やロック時あるいはラ
ンプ負荷の点灯特等過大な電流が必要で、かつ半導体装
置に加わる電圧が小さい場合にも電流制限動作が行われ
てしまう。(2) For example, when an excessive current is required when starting or locking a motor load, or when lighting a lamp load, and the voltage applied to the semiconductor device is small, the current limiting operation is also performed.
本発明の課題は、上記の問題を解決し、負荷の短絡時に
だけ電流制限動作が行われ、しかも容易に低コストで製
造可能な半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to provide a semiconductor device in which a current limiting operation is performed only when a load is short-circuited, and which can be easily manufactured at low cost.
上記の課題の解決のために、本発明は、第一の主端子と
第二の主端子との間を流れる主電流を制御する制御端子
を有する半導体素子の複数個を一つの半導体基板に作成
し、各主端子および制御端子のいずれも並列に接続した
半導体装置において、並列接続された半導体素子の少な
くとも一つと第二の主端子の間にその半導体素子の動作
抵抗以上の大きさの抵抗値の検出抵抗が接続され、その
検出抵抗の両端の電圧が制ｆｆｌ端子と第二の主端子と
を短絡可能の補助スイッチング素子の制御端子に入力さ
れるものとする。In order to solve the above-mentioned problems, the present invention creates a plurality of semiconductor elements having a control terminal for controlling the main current flowing between a first main terminal and a second main terminal on one semiconductor substrate. However, in a semiconductor device in which both main terminals and control terminals are connected in parallel, there is a resistance value greater than the operating resistance of the semiconductor element between at least one of the parallel-connected semiconductor elements and the second main terminal. A detection resistor is connected, and the voltage across the detection resistor is input to the control terminal of the auxiliary switching element that can short-circuit the control ffl terminal and the second main terminal.
検出抵抗の両端の電圧が補助スイッチング素子のしきい
値電圧を越えたとき、スイッチング素子が並列接続主半
導体素子の制？！ｉ＠子と第二の主端子を短絡し、始め
て電流制限動作が行われるので、補助スイッチング素子
のしきい値電圧を適宜設定することにより、負荷短絡時
にのみ電流制限動作を行わせることができる。なお、検
出抵抗の値が副素子の動作抵抗値よりも低いと、主素子
に加わる電圧がかなり低いときにも動作してしまうので
、検出抵抗の値は副素子の動作抵抗値より大きくする。When the voltage across the detection resistor exceeds the threshold voltage of the auxiliary switching element, does the switching element control the parallel-connected main semiconductor element? ! Since the current limiting operation is performed only when the i@ child and the second main terminal are short-circuited, by appropriately setting the threshold voltage of the auxiliary switching element, the current limiting operation can be performed only when the load is short-circuited. . Note that if the value of the detection resistor is lower than the operating resistance value of the sub-element, it will operate even when the voltage applied to the main element is quite low, so the value of the detection resistor is made larger than the operating resistance value of the sub-element.
第１図は本発明の一実施例の回路を示し、第２図と共通
の部分には同一の符号が付されている。FIG. 1 shows a circuit according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals.
主素子１３と副素子１４（いずれもＩＧＢＴ）ガ主端子
１１．１２間に並列接続されていることは第２図と同様
であるが、検出抵抗１３の出力電圧■１がゲートに印加
されるＭＯ３ＦＥＴ１Ｂが備えられている。The main element 13 and the sub-element 14 (both IGBT) are connected in parallel between the main terminals 11 and 12, as shown in Fig. 2, but the output voltage 1 of the detection resistor 13 is applied to the gate. MO3FET1B is provided.
ＭＯＳＦＥＴのドレインは素子１３．１４の制御端子１
９に、ソースは主端子１２に接続されている。この回路
の動作の要点を第３図を引用して説明する。The drain of the MOSFET is the control terminal 1 of elements 13 and 14.
9, the source is connected to the main terminal 12. The main points of the operation of this circuit will be explained with reference to FIG.
第３図のたて軸は素子１３と１４との電流密度、横軸は
素子１３と素子１４および検出抵抗１５の両端とに加わ
る電圧である０曲＆１３１ 、３２は素子１３．１４の
保護回路が働かない場合の一定ゲート電圧下の動作曲線
、曲線３３ 、３４は素子１３．素子１４の保護回路が
働いてＩ ＧＢＴのゲート電圧が下げられた場合の動作
曲線である。スイッチング素子１８の動作点はｂｍに設
定されているものとする。すなわち副素子１４に流れる
電流１１が８゜からｂｌを経てｂ！に達するまで、主素
子にもａ、からａｔを経て飽和領域に達しａ、に至るま
での大きな電流を流すことができる０次に事故により′
９Ｌ荷が短絡した場合、素子１３に加わる電圧が上昇し
、電圧・電流曲ｍ３ｉ、３２上を右上の方へ動く、この
とき、検出抵抗１５の出力電圧ｖ１がＭＯ３ＦＥＴ１８
のしきい値電圧に達するため、ＭＯＳＦＥＴがオンして
素子１３．１４のゲ・−ト電圧を下げる。これにより副
素子Ｘ４および検出抵抗２５の両ｙｉｔ圧はｂ８から水
平に右方向へ移動し、外から加わる電圧で決まる動作点
Ｃに達する。主素子１３はａ工から右下方に移動し、や
はり０点に達する。このようにして、負荷短絡時にだけ
素子１３．１４の電流を制限することが可能である。な
お動作点Ｃを高電圧側に移動させたいときには、検出抵
抗１５の値をさらに大きくすればよい。In FIG. 3, the vertical axis is the current density of elements 13 and 14, and the horizontal axis is the voltage applied across elements 13 and 14 and the detection resistor 15. Curves 33 and 34 are operating curves under a constant gate voltage when the device 13. This is an operating curve when the protection circuit of the element 14 is activated and the gate voltage of the IGBT is lowered. It is assumed that the operating point of the switching element 18 is set to bm. In other words, the current 11 flowing through the sub-element 14 moves from 8° through bl to b! Due to the zero-order accident, a large current can be passed through the main element from a, through at, until reaching the saturation region, a.
When the 9L load is short-circuited, the voltage applied to the element 13 increases and moves toward the upper right on the voltage/current curve m3i, 32. At this time, the output voltage v1 of the detection resistor 15 increases to the MO3FET18.
reaches the threshold voltage of , the MOSFET turns on and lowers the gate voltage of elements 13 and 14. As a result, both the yit pressures of the sub-element X4 and the detection resistor 25 move horizontally to the right from b8, and reach the operating point C determined by the voltage applied from the outside. The main element 13 moves from point a to the lower right and also reaches the 0 point. In this way, it is possible to limit the current in element 13.14 only in the event of a load short-circuit. Note that when it is desired to move the operating point C to the high voltage side, the value of the detection resistor 15 may be further increased.
第４図は第１図に示した本発明の一実施例の半導体装置
を形成した１枚のシリコン基板の平面図であり、第５図
はそのＡ−Ａ線、第６図はＢ−Ｂ線に沿っての断面図で
ある。シリコン基板の大部分には主Ｉ ＧＢＴ素子１３
が形成され、そのうちの一つは副Ｉ ＧＢＴ素子１４と
して働き、基板上に各素子のゲート電極と同様成膜され
る多結晶シリコンよりなる検出抵抗１５に接続されてい
る。ＩＧＢＴ素子の設けられない部分にはＭＯ３ＦＥＴ
１８が作成され、ドレインは、一部が各Ｉ ＧＢＴ素子
のゲート電極となる多結晶シリコン膜に、ソースは、検
出抵抗１５の他端と共に各Ｉ ＧＢＴ素子のソース電極
と共通のアルミニウム配線電極にそれぞれ接触する。こ
れらの接続の詳細については後述する。FIG. 4 is a plan view of one silicon substrate on which a semiconductor device according to an embodiment of the present invention shown in FIG. 1 is formed, FIG. FIG. 3 is a cross-sectional view along the line. Most of the silicon substrate contains the main IGBT element 13.
are formed, one of which serves as a sub-IGBT element 14 and is connected to a detection resistor 15 made of polycrystalline silicon, which is formed on the substrate in the same manner as the gate electrode of each element. MO3FET is installed in the part where IGBT element is not provided.
18 is created, and the drain is connected to a polycrystalline silicon film, a part of which becomes the gate electrode of each IGBT element, and the source is connected to an aluminum wiring electrode that is common to the source electrode of each IGBT element together with the other end of the detection resistor 15. contact each. Details of these connections will be described later.
各主Ｉ ＧＢＴ素子１３の構造は第５図に示されている
、ｐ＋シリコン基板１の上にｎ４バッファ層２を介して
積層されたｎ−エピタキシャル層３に多数のｐベース層
４が形成される。ｐベース層４の中には中央に環状にソ
ース層５が形成され、このソース層５とｎ−Ｗｉ３の間
のｐベース層４にチャネルが形成されるよう、多結晶シ
リコン膜からなるゲー）を極７がゲート酸化膜６を介し
て設けられている。ゲート電極７はさらに絶縁膜８で覆
われ、その絶縁膜の開口部８】でベース層４およびソー
ス層５に接触するアルミニウム配線がソース電８ｉ９を
形成している。別にｐ°基板１の下面にはドレイン電極
１０が接触している。The structure of each main IGBT element 13 is shown in FIG. 5, in which a large number of p base layers 4 are formed on an n- epitaxial layer 3 laminated on a p+ silicon substrate 1 via an n4 buffer layer 2. Ru. An annular source layer 5 is formed in the center of the p base layer 4, and a gate made of a polycrystalline silicon film is formed so that a channel is formed in the p base layer 4 between the source layer 5 and n-Wi3. A pole 7 is provided with a gate oxide film 6 interposed therebetween. The gate electrode 7 is further covered with an insulating film 8, and an aluminum wiring that contacts the base layer 4 and the source layer 5 at an opening 8 in the insulating film forms a source electrode 8i9. In addition, a drain electrode 10 is in contact with the lower surface of the p° substrate 1.
ＭＯ３ＦＥ７１８の構造は第６図に示されている。The structure of MO3FE718 is shown in FIG.
ＭＯ３ＦＥＴ１８は、ｐベース層４にソース層５１とド
レインＦＪ５２を設けその中間上にゲート酸化膜６を介
してゲート電極７１を設けることにより形成されててい
る。ソース層５１．ドレイン層５２とｎ°層３の間にチ
ャネルが形成されないようその上には厚い酸化膜６１が
形成されている。多結晶シリコン膜を覆う絶縁膜８の開
口部８２ではソース層５１およびベース層４がＭ配線９
１に、開口部８３ではドレイン層５２がＭ配線９２に接
触し、このＭ配線９２の他端は絶縁膜８の開口部８４で
ゲート電極７に接続されている。Ａ７配線９１の他端は
Ｉ ＧＢＴ素子１３のソース電極９に連結されている。The MO3FET 18 is formed by providing a source layer 51 and a drain FJ 52 on the p base layer 4, and providing a gate electrode 71 therebetween with a gate oxide film 6 interposed therebetween. Source layer 51. A thick oxide film 61 is formed thereon to prevent a channel from being formed between the drain layer 52 and the n° layer 3. In the opening 82 of the insulating film 8 covering the polycrystalline silicon film, the source layer 51 and the base layer 4 are connected to the M wiring 9.
1, the drain layer 52 contacts the M wiring 92 in the opening 83, and the other end of the M wiring 92 is connected to the gate electrode 7 in the opening 84 of the insulating film 8. The other end of the A7 wiring 91 is connected to the source electrode 9 of the IGBT element 13.
このようなＭＯ３ＦＥＴ１８のベース層４は主素子１３
のベース層４と、ソース層５１およびドレイン層５２は
ソース層５と同一工程で形成できることは明らかである
。なお、図示しないが副ＩＧＢＴ素子１４は主ＩＧＢＴ
素子１３と全く同一構造である。The base layer 4 of such MO3FET 18 is the main element 13
It is clear that the base layer 4, the source layer 51, and the drain layer 52 can be formed in the same process as the source layer 5. Although not shown, the sub-IGBT element 14 is a main IGBT
It has exactly the same structure as element 13.
第４図において実線７０は多結晶シリコン膜の領界を示
し、ゲート電８ｉ７．７１および検出抵抗１５を構成し
ているが、各ゲート電極７は連続して形成されている。In FIG. 4, a solid line 70 indicates the area of the polycrystalline silicon film, which constitutes the gate electrodes 8i7, 71 and the detection resistor 15, and each gate electrode 7 is formed continuously.
破線９０はＭ膜の領界を示し、−点鎖線８０は絶縁膜の
領界を示す、ＡＩ膜は絶縁膜の開口部８でシリコン板面
に接触して主素子１３のソース電極９を、開口部８１で
シリコン板面に接触して副素子１４のソース電極９を、
開口部８２でシリコン板面に接触してスイッチング素子
１８のソース電極９１を、開口部８３でシリコン板面に
接触してスイッチング素子１８めドレイン電極９２を形
成する。抵抗１５およびゲート７１を形成する多結晶シ
リコン膜の一端は、絶縁膜９の開口部８５で各主素子１
３のソース電極９、ＭＯ３ＦＥＴ１８のソース電極９１
とつながるＭ膜に接触し、他端は絶縁膜９の開口部８６
で副素子１４のソース電極とつながるＭ膜に接触してい
る。なお二点鎖線８８は厚い酸化膜の領界を示す。The broken line 90 indicates the area of the M film, and the dashed line 80 indicates the area of the insulating film. The source electrode 9 of the sub-element 14 is brought into contact with the silicon plate surface through the opening 81.
A source electrode 91 of the switching element 18 is formed in contact with the silicon plate surface through the opening 82, and a drain electrode 92 of the switching element 18 is formed in contact with the silicon plate surface through the opening 83. One end of the polycrystalline silicon film forming the resistor 15 and the gate 71 is connected to each main element 1 at the opening 85 of the insulating film 9.
3 source electrode 9, MO3FET 18 source electrode 91
The other end is in contact with the M film connected to the opening 86 of the insulating film 9.
and is in contact with the M film connected to the source electrode of the sub-element 14. Note that a two-dot chain line 88 indicates a region of a thick oxide film.
なお上記の実施例ではスイッチング素子１８としてユニ
ポーラ型のＭＯＳＦＥＴを用いたのは、バイポーラトラ
ンジスタやＩ ＧＢＴを用いるよりも寄生素子の動作を
抑制できるからであるが、これに限定されるものではな
い。In the above embodiment, a unipolar MOSFET is used as the switching element 18 because the operation of parasitic elements can be suppressed more than using a bipolar transistor or an IGBT, but the present invention is not limited to this.
本発明によれば、同一半導体基板に作成され、並列接続
される複数の同一半導体素子の一つの副素子に接続され
た検出抵抗の出力電圧を直接補助スイッチング素子の制
御電極に入力し、負荷短絡時の主端子間の電圧上昇によ
り前記スイッチング素子をオンさせて並列接続の各素子
への制御入力を低下させ、電流の上昇を抑制することが
できる。According to the present invention, the output voltage of the detection resistor connected to one sub-element of a plurality of identical semiconductor elements fabricated on the same semiconductor substrate and connected in parallel is inputted directly to the control electrode of the auxiliary switching element, thereby shorting the load. When the voltage between the main terminals increases, the switching element is turned on to reduce the control input to each element connected in parallel, thereby suppressing the increase in current.
検出抵抗の値を副素子の動作抵抗値以上とすることによ
り、電流制限動作が負荷短絡時でない低い主端子間電圧
で始まることが防止される。そして、このような保護回
路は主素子および副素子と同一半導体基板に、工程を増
すことなく、低コストで集積することができる。By setting the value of the detection resistor to be equal to or greater than the operating resistance value of the sub-element, it is possible to prevent the current limiting operation from starting at a low voltage between the main terminals when the load is not short-circuited. Such a protection circuit can be integrated on the same semiconductor substrate as the main element and the sub-element at low cost without increasing the number of steps.
第１図は本発明の一実施例の半導体装置の回路図、第２
図は従来の保ｆｉ１回路付き半導体装置の回路図、第３
図は本発明の一実施例の電流制限動作を示す電流・電圧
線図、第４図は第１図に示した半導体装置のシリコン基
板の平面図、第５図、第６図はそれぞれ第４図のＡ−Ａ
線、Ｂ−Ｂ線に沿っての断面図である。
１１、１２：主端子、１３：主ＩＧＢＴ素子、１４：副
ＩＧＢＴ素子、１５：検出抵抗、１８二補助ＭＯ３Ｆ第
４図
第１図
］○
第５図
一一一−３FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, and FIG.
The figure is a circuit diagram of a conventional semiconductor device with a FI1 circuit.
4 is a plan view of the silicon substrate of the semiconductor device shown in FIG. 1, and FIGS. A-A in the diagram
FIG. 3 is a cross-sectional view taken along line B-B. 11, 12: Main terminal, 13: Main IGBT element, 14: Sub IGBT element, 15: Detection resistor, 182 auxiliary MO3F Fig. 4 Fig. 1] ○ Fig. 5 111-3
Claims (1)
制御する制御端子を有する半導体素子の複数個を一つの
半導体基板に作成し、各主端子および制御端子のいずれ
も並列に接続したものにおいて、並列接続された半導体
素子の少なくとも一つと第二の主端子の間にその半導体
素子の動作抵抗以上の大きさの抵抗値の検出抵抗が接続
され、その検出抵抗の両端の電圧が制御端子と第二主端
子とを短絡可能の補助スイッチング素子の制御端子に入
力されることを特徴とする半導体装置。1) A plurality of semiconductor elements having control terminals that control the main current flowing between a first main terminal and a second main terminal are created on one semiconductor substrate, and each main terminal and control terminal are connected in parallel. A detection resistor with a resistance value greater than the operating resistance of the semiconductor element is connected between at least one of the semiconductor elements connected in parallel and the second main terminal, and A semiconductor device characterized in that a voltage is input to a control terminal of an auxiliary switching element capable of short-circuiting a control terminal and a second main terminal.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63218766A JPH0266975A (en) | 1988-09-01 | 1988-09-01 | Semiconductor device |
| KR1019890011734A KR920010818B1 (en) | 1988-09-01 | 1989-08-18 | Semiconductor devices |
| DE3927307A DE3927307A1 (en) | 1988-09-01 | 1989-08-18 | Short circuit protected transistor circuit - includes MOSFET and parallel resistance between control connection for auxiliary IGBT and one main connection |
| FR8911516A FR2635929A1 (en) | 1988-09-01 | 1989-09-01 | SEMICONDUCTOR DEVICE HAVING SHORT-CIRCUIT PROTECTION CIRCUIT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63218766A JPH0266975A (en) | 1988-09-01 | 1988-09-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0266975A true JPH0266975A (en) | 1990-03-07 |
Family
ID=16725064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63218766A Pending JPH0266975A (en) | 1988-09-01 | 1988-09-01 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH0266975A (en) |
| KR (1) | KR920010818B1 (en) |
| DE (1) | DE3927307A1 (en) |
| FR (1) | FR2635929A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010103571A (en) * | 2010-02-08 | 2010-05-06 | Renesas Technology Corp | Semiconductor device |
| US7932553B2 (en) | 2007-12-24 | 2011-04-26 | Denso Corporation | Semiconductor device including a plurality of cells |
| CN102570809A (en) * | 2010-12-31 | 2012-07-11 | 意法半导体研发(深圳)有限公司 | Short-circuit protection circuit and method |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0479758A (en) * | 1990-07-19 | 1992-03-13 | Fuji Electric Co Ltd | Driving circuit of current sensing igbt |
| JP3180831B2 (en) * | 1991-03-22 | 2001-06-25 | 富士電機株式会社 | Insulated gate control semiconductor device |
| JPH04323863A (en) * | 1991-04-23 | 1992-11-13 | Toyota Autom Loom Works Ltd | Semiconductor device |
| DE4122653C2 (en) * | 1991-07-09 | 1996-04-11 | Daimler Benz Ag | Controllable semiconductor switching device with integrated current limitation and overtemperature shutdown |
| JPH05315852A (en) * | 1992-05-12 | 1993-11-26 | Fuji Electric Co Ltd | Current limit circuit and constant voltage source for the same |
| JP3084982B2 (en) * | 1992-11-25 | 2000-09-04 | 富士電機株式会社 | Semiconductor device |
| CN111371080B (en) * | 2018-12-25 | 2022-08-30 | 上海睿驱微电子科技有限公司 | Equipment with overcurrent limiting function and construction method thereof |
| CN111370478B (en) * | 2018-12-25 | 2022-04-01 | 上海睿驱微电子科技有限公司 | Polycrystalline silicon with overcurrent limiting function and construction method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62143450A (en) * | 1985-12-18 | 1987-06-26 | Hitachi Ltd | Composite semiconductor device |
| JPS63318781A (en) * | 1987-06-22 | 1988-12-27 | Nissan Motor Co Ltd | Mosfet with overcurrent protective function |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4667121A (en) * | 1986-05-27 | 1987-05-19 | Motorola, Inc. | Integrated circuit speed controller |
-
1988
- 1988-09-01 JP JP63218766A patent/JPH0266975A/en active Pending
-
1989
- 1989-08-18 DE DE3927307A patent/DE3927307A1/en not_active Ceased
- 1989-08-18 KR KR1019890011734A patent/KR920010818B1/en not_active IP Right Cessation
- 1989-09-01 FR FR8911516A patent/FR2635929A1/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62143450A (en) * | 1985-12-18 | 1987-06-26 | Hitachi Ltd | Composite semiconductor device |
| JPS63318781A (en) * | 1987-06-22 | 1988-12-27 | Nissan Motor Co Ltd | Mosfet with overcurrent protective function |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7932553B2 (en) | 2007-12-24 | 2011-04-26 | Denso Corporation | Semiconductor device including a plurality of cells |
| JP2010103571A (en) * | 2010-02-08 | 2010-05-06 | Renesas Technology Corp | Semiconductor device |
| CN102570809A (en) * | 2010-12-31 | 2012-07-11 | 意法半导体研发(深圳)有限公司 | Short-circuit protection circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR900005446A (en) | 1990-04-14 |
| KR920010818B1 (en) | 1992-12-17 |
| FR2635929A1 (en) | 1990-03-02 |
| DE3927307A1 (en) | 1990-04-05 |
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