JP2005064472A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high withstand voltage semiconductor device at a low cost in which a device for power, a circuit for driving the device for power, and a logic device for controlling the device for power are integrated on a single chip. <P>SOLUTION: A high withstand voltage junction terminal structure 34 comprising a RESURF (reduced surface field) structure in loop form is formed on a SOI substrate, and a horizontal IGBT13, a horizontal FWD14, an output stage device 15, and a driving circuit 16 are formed inside the region. The horizontal IGBT13 and horizontal FWD14 are encircled by a trench separation region 19, which is an insulation region. Drain electrodes 17a, 17b of high withstand voltage NMOSFETs 12a, 12b, which are level shift devices, are provided inside the high withstand voltage junction terminal structure 34, and a gate electrode and a source electrode of the NMOSFETs are provided outside the high withstand voltage junction terminal structure 34. The high withstand voltage junction terminal structure 34 is encircled by the trench separation region 19, which is a second insulation region. A control circuit 11 is provided outside the second insulation region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device such as a high breakdown voltage IC (integrated circuit) in which a high breakdown voltage lateral semiconductor element and a low breakdown voltage control semiconductor element are integrated on the same substrate by applying a dielectric isolation technique. The present invention relates to a semiconductor device that constitutes a one-chip inverter in which an IGBT (insulated gate bipolar transistor) and a lateral FWD (freewheeling diode) are mounted on a same substrate together with a drive circuit, a control circuit, and a level shift circuit.

  2. Description of the Related Art In recent years, in a semiconductor device such as a high voltage IC, a high voltage power IC has been developed in which a power switching element such as an IGBT and a circuit for driving, controlling and protecting the same are integrated on a single semiconductor substrate. . In such a high withstand voltage power IC, element isolation techniques such as junction isolation and dielectric isolation are used.

  In the dielectric isolation structure, the capacitance per unit area of the isolation region is significantly smaller than that of the junction isolation structure, so that it is possible to form a structure that is less likely to cause breakdown or malfunction of the semiconductor device due to the latch-up phenomenon of the parasitic element. There is an advantage. In addition, a leakage current due to light occurs in an element having a junction isolation structure in a strong radiation environment, but the dielectric isolation structure has an advantage that it can be eliminated.

  Because of the advantages as described above, a one-chip inverter has been developed in which a lateral IGBT and a lateral FWD are mounted on the same substrate as a control element for controlling them using a dielectric isolation technique. The advantage of the 1-chip inverter is that the size of the inverter device can be reduced by reducing the mounting area of the chip and the chip using bonding wires compared to the conventional configuration in which the power element chip and the control element chip are separately provided. This means that high reliability can be realized by reducing the electrical connection between them.

  FIG. 9 shows a configuration of a general inverter circuit. As shown in FIG. 9, the power devices used for driving a three-phase motor or the like (not shown) include six IGBTs Q1, Q2, Q3, Q4, Q5, Q6 and one connected to each of them in parallel. It is composed of FWDD1, D2, D3, D4, D5, and D6, and constitutes a bridge circuit. The anodes of FWDD1, D2, D3, D4, D5, and D6 are connected to the emitters of IGBTs Q1, Q2, Q3, Q4, Q5, and Q6, respectively, and the cathodes are connected to the collector.

  Collectors of IGBTs Q1, Q2 and Q3 which are upper arm switching elements of U phase, V phase and W phase, and emitters of IGBTs Q4, Q5 and Q6 which are lower arm switching elements of U phase, V phase and W phase, respectively A DC voltage is applied between the two. This DC voltage is obtained by the AC power source 1, the converter 2 and the capacitor C.

  The gates of the IGBTs Q1, Q2 and Q3 on the upper arm side are connected to the corresponding output stage elements 3a, 3b and 3c, respectively. The gates of the IGBTs Q4, Q5, Q6 on the lower arm side are respectively connected to corresponding output stage elements (not shown) provided in the control circuit 4. That is, IGBTs Q1, Q2, Q3, Q4, Q5, and Q6 are turned on / off based on the output signals of the corresponding output stage elements. In FIG. 9, the connection between each gate and the output stage element is omitted in order to avoid the drawing from being complicated.

  A control signal that determines which one of IGBTs Q1, Q2, Q3, Q4, Q5, and Q6 is turned on and which is turned off is issued from the control circuit 4 based on a signal supplied from a microcomputer (not shown). The control signals for the IGBTs Q1, Q2 and Q3 on the upper arm side are adjusted in voltage by the level shift circuit 5 and then supplied to the output stage elements 3a, 3b and 3c via the corresponding drive circuits 6a, 6b and 6c. The Control signals for the IGBTs Q4, Q5, Q6 on the lower arm side are supplied to output stage elements (not shown) via corresponding drive circuits (not shown) provided in the control circuit 4.

  FIG. 10 is a plan view of a principal part schematically showing the configuration of the U-phase upper arm of a conventional one-chip inverter. As shown in FIG. 10, a conventional one-chip inverter (for U-phase upper arm) 10 drives each of U-phase, V-phase and W-phase on an SOI (silicon on insulator) substrate based on an input signal. A control circuit 11 for outputting a control signal to the circuit; a high breakdown voltage NMOSFET (N-channel insulated gate field effect transistor using an oxide film as a gate insulating film) 12a, 12b, U, constituting a level shift element of the level shift circuit; A lateral IGBT 13 which is a switching element of the upper arm, a lateral FWD 14 connected in parallel to the lateral IGBT 13, an output stage element 15 which supplies a switching signal to the lateral IGBT 13, and drain electrodes 17a and 17b of high breakdown voltage NMOSFETs 12a and 12b (level shift elements) Based on signals supplied from the wirings 18a and 18b Driving circuit 16 for generating an output signal to the Chikaradan element 15 is fabricated.

  The formation region of each circuit and element is separated by a trench isolation region 19 serving as an insulating region. In FIG. 10, only the circuits related to the basic functions of the inverter are explicitly shown, and the protection circuits included in the drive circuit and the control circuit and the circuits having other functions are not clearly shown ( The same applies to other figures). Further, as a level shift element, a high breakdown voltage PMOSFET (P channel MOSFET) for a level down circuit may be mounted instead of the high breakdown voltage NMOSFET for the level up circuit.

  FIG. 11 is a longitudinal sectional view taken along the line G-G ′ of FIG. 10 and shows a sectional configuration of the high breakdown voltage NMOSFET 12a (level shift element). As shown in FIG. 11, the SOI substrate 20 includes a first semiconductor substrate 21 as a support substrate and a second semiconductor substrate 23 as a semiconductor layer on which an element structure is formed, and an oxide film 22 as an insulating layer. It is the structure which bonded together via. The drain electrode 17a of the high voltage NMOSFET 12a is provided at the center of the high voltage NMOSFET 12a. Around the drain electrode 17a, a high breakdown voltage junction termination structure 24 having a RESURF structure such as a double RESURF (reduced surface field) or a single RESURF is formed.

  The gate electrode 25 and the source electrodes 26 a and 26 b of the high voltage NMOSFET 12 a are formed on a part of the outer periphery of the high voltage junction termination structure 24. P diffusion layers 27 a and 27 b are provided on the surface of the high breakdown voltage junction termination structure 24 in order to increase the breakdown voltage due to the RESURF effect. A trench isolation region 19 is provided around the high breakdown voltage NMOSFET 12a. An oxide film 28 is formed on the sidewall of the trench isolation region 19. The inner portion of the oxide film 28 is filled with polycrystalline silicon 29.

  As shown in FIG. 11, in the conventional one-chip inverter, since the wiring 18a connected to the drain electrode 17a of the high breakdown voltage NMOSFET 12a crosses over the high breakdown voltage junction termination structure 24, this wiring 18a and the second semiconductor A portion where a high voltage of about 600 V, for example, is applied to the substrate 23 is generated. For this reason, the interlayer insulating film 30 such as an oxide film between the high voltage wiring 18a and the second semiconductor substrate 23 must be thick. If the interlayer insulating film 30 is thin, the potential of the high voltage wiring 18a affects the potential distribution of the substrate, which causes the breakdown voltage degradation of the high breakdown voltage NMOSFET 12a. Further, the interlayer insulating film 30 may be destroyed when the potential of the drain electrode 17a jumps.

  The same applies to the interlayer insulating film between the second semiconductor substrate and the wiring 18b connected to the drain electrode 17b of the other high breakdown voltage NMOSFET 12b shown in FIG. The same applies to the V-phase upper arm and the W-phase upper arm having the same configuration as the above-described U-phase upper arm.

  By the way, the present inventors have eliminated the structure in which the high potential wiring crosses the ground (GND) level substrate through the insulating film by using the self-shielding technique, thereby realizing a high voltage IC of 1000 V or more. It has been previously reported that this is possible (see, for example, Non-Patent Document 1). Various self-shielding techniques have been proposed (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

  FIG. 12 is a plan view of a principal part schematically showing the configuration of the U-phase upper arm of the inverter device in which the self-shielding technology is applied to the conventional multi-chip configuration. As shown in FIG. 12, the control circuit 11, the output stage element 15, and the drive circuit 16 are fabricated on a high voltage IC chip 31. The IGBT 32 and the FWD 33 are manufactured on a chip different from the high voltage IC chip 31.

  The output stage element 15 and the drive circuit 16 are formed in a region surrounded by a high voltage junction termination structure 34 having a loop-shaped resurf structure on the high voltage IC chip 31. The output stage element 15 is electrically connected to the gate electrode 35 and the emitter electrode 36 of the IGBT 32 via bonding wires 37 and 38, respectively.

  FIG. 13 is a vertical cross-sectional view taken along the line H-H ′ of FIG. 12 and shows a cross-sectional configuration of the high breakdown voltage NMOSFET 12 a that is a level shift element. As shown in FIG. 13, the drain electrode 17a of the high breakdown voltage NMOSFET 12a is formed at one end of the high breakdown voltage junction termination structure 34, and the gate electrode 25 and the source electrode 26a of the high breakdown voltage NMOSFET 12a are formed at the other end. 26b is formed. The cross-sectional configuration of the other high breakdown voltage NMOSFET 12b is the same as that in FIG. The configuration for the V-phase upper arm and the configuration for the W-phase upper arm are the same as the configuration for the U-phase upper arm.

Japanese Patent No. 3214818 JP-A-9-55498 US Pat. No. 6,124,628 Tatsuhiko Fujihira, 4 others, “Self-shielding: New High-Voltage Inter-Connection Techniques for HVICs”, i-Triple E. (USA), 1996, p. 231-234

  As described above, the conventional one-chip inverter requires the thick interlayer insulating film 30 between the high-voltage wiring 18a and the second semiconductor substrate 23. However, an oxide film or the like that can be formed on the substrate is used. The thickness of the insulating film is limited in terms of manufacturing cost. The thickness of the interlayer insulating film that is currently in practical use is about 6 μm for a 600V withstand voltage 1-chip inverter. On the other hand, when a one-chip inverter of the 1200V withstand voltage class is realized with the same structure as that of the 600V withstand voltage, in order to ensure high reliability, the interlayer insulating film under the high voltage wiring is formed with a thickness exceeding 10 μm. Therefore, there is a problem that it is difficult to manufacture at low cost.

  The present invention has been made in view of the above problems, and is a low-cost, high-breakdown-voltage semiconductor device in which a power element and a drive circuit for driving the power element are integrated on the same chip. An object is to provide a semiconductor device in which logic elements for controlling elements are also integrated.

  In order to achieve the above object, a semiconductor device according to the present invention includes a support substrate, an insulating layer stacked on the support substrate, a semiconductor layer stacked on the insulating layer, and a surface region of the semiconductor layer. A high withstand voltage junction termination structure made of a RESURF structure formed in a loop shape, a power element formed in a region surrounded by the high withstand voltage junction termination structure, and formed in a region surrounded by the high withstand voltage junction termination structure The power element driving means, an insulating region that surrounds the power element in a region surrounded by the high-voltage junction termination structure, and penetrates the semiconductor layer to reach the insulating layer; A level shift element having an input electrode to which a voltage before level shift is applied on one side of the junction termination structure and an output electrode for outputting a voltage after level shift on the other side; Output electrode of the serial level shift element and the wiring that electrically connects the driving means, characterized by comprising, an interlayer insulating film provided between the wire and the semiconductor layer.

  According to the present invention, since the level shift element is formed across the inner side and the outer side of the high voltage junction termination structure by applying the self-shielding technique, the high potential wiring connected to the level shift element is connected to the ground. It is connected to the driving means without crossing over the (GND) level semiconductor layer. Therefore, it is not necessary to provide a particularly thick interlayer insulating film on the semiconductor layer. In addition, since the power element is dielectrically separated by an insulating region in the inner region of the high-voltage junction termination structure, the grounding (GND) level outside the power element and the high-voltage junction termination structure is used as a reference potential. It is possible to prevent a parasitic element from operating with the element.

  In this invention, the drive means may be provided between the high voltage junction termination structure and the insulating region. Moreover, the structure which comprises the 2nd insulation area | region which surrounds the said high voltage | pressure-resistant junction termination structure and penetrates the said semiconductor layer and reaches the said insulating layer may be sufficient. Alternatively, the drive unit may be surrounded by the insulating region. By doing so, the operation of the parasitic element can be further suppressed, so that the reliability can be improved.

  In the above invention, the level shift element has a drain electrode serving as the output electrode on one side of the high voltage junction termination structure and a source serving as the gate electrode and the input electrode on the other side. You may be comprised by high voltage | pressure-resistant MOSFET (insulated gate field effect transistor) which has an electrode. One or both of IGBT and FWD may be formed as the power element. One or both of NMOSFET and PMOSFET may be formed in the driving means. In this way, it is possible to obtain a one-chip inverter that integrates a power element and its driving means, which is low in cost, hardly breaks down or malfunctions due to the operation of a parasitic element, and has a withstand voltage exceeding 1000V.

  Further, in the above invention, a logic element may be provided in an outer region of the high breakdown voltage junction termination structure of the semiconductor layer. As the logic element, an N channel insulated gate field effect transistor and a P channel insulation are provided. One or both of the gate type field effect transistors may be formed. In this way, a one-chip inverter that integrates power elements (IGBT and FWD), driving means and control circuit thereof, which is low in cost, hardly breaks down or malfunctions due to the operation of parasitic elements, and has a withstand voltage exceeding 1000V. Is obtained.

  Furthermore, in the above invention, a second interlayer insulating film is formed on the semiconductor layer between the input electrode and the output electrode, and the input electrode and the output electrode are formed on the second interlayer insulating film. It is good also as a structure which extended to (2) and used also as the field plate of a level shift element. In this way, the presence of the field plate can alleviate the concentration of the electric field in the level shift element.

  According to the semiconductor device of the present invention, since it is not necessary to provide a particularly thick interlayer insulating film under the high potential wiring that connects the level shift element and the driving means, a high breakdown voltage semiconductor device can be obtained at low cost. There is an effect. In addition, since the operation of the parasitic element can be prevented, there is an effect that a semiconductor device that is unlikely to break down or malfunction can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each of the following embodiments, an example in which the present invention is applied to a three-phase inverter having a one-chip configuration will be described, and the configuration of the U-phase upper arm of the one-chip inverter will be described. The configuration of the upper arm of the V phase and the W phase is the same as the configuration of the upper arm of the U phase. The configuration of the lower arm for each phase is the same as the configuration of the U-phase upper arm except that there is no level shift element. Therefore, the description thereof is omitted.

Embodiment 1 FIG.
FIG. 1 is a main part plan view schematically showing the configuration of the U-phase upper arm of the one-chip inverter according to the first embodiment of the present invention. Note that in the first embodiment, the same components as those illustrated in FIGS. 10 to 13 are denoted by the same reference numerals and redundant description is omitted.

  As shown in FIG. 1, in the one-chip inverter (for U-phase upper arm) 40 according to the first embodiment, a control circuit 11 including a logic element, high breakdown voltage NMOSFETs 12a and 12b as level shift elements, and a horizontal type as a power element. The IGBT 13 and the lateral FWD 14, and the output stage element 15 and the drive circuit 16 constituting the drive means are fabricated on the same substrate. As this substrate, an SOI substrate 20 (see FIGS. 2 to 4) made up of a first semiconductor substrate 21, an oxide film 22, and a second semiconductor substrate 23 is used.

  The lateral IGBT 13, the lateral FWD 14, the output stage element 15, and the drive circuit 16 are fabricated in a region surrounded by a high voltage junction termination structure 34 having a loop-shaped resurf structure. Further, the lateral IGBT 13 and the lateral FWD 14 are fabricated in an element formation region surrounded by a trench isolation region 19 that is an insulating region. The output stage element 15 and the drive circuit 16 are fabricated in a region between the high voltage junction termination structure 34 and the trench isolation region 19.

  The high breakdown voltage NMOSFETs 12a and 12b are formed across the inside and outside of the high breakdown voltage junction termination structure. The drain electrodes 17a and 17b and the drive circuit 16 are electrically connected via wirings 18a and 18b. The high breakdown voltage junction termination structure 34 is surrounded by a trench isolation region 19 which is a second insulating region formed in a loop shape. The control circuit 11 is provided outside the trench isolation region 19 that is the second insulating region.

  FIG. 2 is a vertical cross-sectional view taken along the line A-A ′ of FIG. 1, and shows cross-sectional configurations of the horizontal IGBT 13 and the horizontal FWD 14. As shown in FIG. 2, the trench isolation region 19 passes through the second semiconductor substrate (N-type) 23 of the SOI substrate 20 and reaches the oxide film 22 of the SOI substrate 20. The lateral IGBT 13 and the lateral FWD 14 are formed in different element formation regions surrounded by the trench isolation region 19 and the oxide film 22 of the SOI substrate 20, respectively. Hereinafter, for convenience, an element formation region in which the lateral IGBT 13 is formed is referred to as an IGBT formation region, and an element formation region in which the lateral FWD 14 is formed is referred to as an FWD formation region.

In the IGBT formation region, P well regions 41 a and 41 b are selectively formed on the surface layer of the second semiconductor substrate 23. P ⁺ contact regions 45a and 45c and N ⁺ emitter regions 46a and 46b are formed on the surfaces of P well regions 41a and 41b. Emitter electrodes 47a and 47c are electrically connected to P ⁺ contact regions 45a and 45c and N ⁺ emitter regions 46a and 46b.

Further, the N buffer region 42 is selectively formed on the surface layer of the second semiconductor substrate 23 in the IGBT formation region. P ⁺ collector region 45 b is formed on the surface of N buffer region 42. The collector electrode 47b is electrically connected to the P ⁺ collector region 45b. Gate electrodes 44a and 44b are provided on the surfaces of P well regions 41a and 41b via a gate insulating film.

In the FWD formation region, P diffusion regions 41 c and 41 d are selectively formed on the surface layer of the second semiconductor substrate 23. The P ⁺ anode regions 45d and 45e are formed on the surfaces of the P diffusion regions 41c and 41d. The anode electrodes 47d and 47f are electrically connected to the P ⁺ anode regions 45d and 45e. The N ⁺ cathode region 46 c is selectively formed on the surface layer of the second semiconductor substrate 23. The cathode electrode 47e is electrically connected to the N ⁺ cathode region 46c.

On the trench isolation region 19, thermal oxide films 43a, 43d, and 43g for element isolation are provided. Thermal oxide films 43 b and 43 c are also formed between the P well regions 41 a and 41 b and the N buffer region 42. Thermal oxide films 43e and 43f are also formed between the P diffusion regions 41c and 41d and the N ⁺ cathode region 46c. An interlayer insulating film 30 such as BPSG is provided on the thermal oxide films 43a, 43b, 43c, 43d, 43e, 43f, 43g and the gate electrodes 44a, 44b.

  Further, as shown in FIG. 2, the emitter electrodes 47a and 47c, the collector electrode 47b, the anode electrodes 47d and 47f, and the cathode electrode 47e are projected on the interlayer insulating film 30, thereby having a function as a field plate. . Similarly, the gate electrodes 44a and 44b project over the thermal oxide films 43b and 43c, thereby functioning as field plates. The ends of the emitter electrodes 47a and 47c extend closer to the collector electrode 47b than the ends of the gate electrodes 44a and 44b positioned below, respectively, and the electric field concentrates near the ends of the gate electrodes 44a and 44b. To alleviate.

  A method for forming the lateral IGBT 13 and the lateral FWD 14 having the configuration shown in FIG. 2 will be described. First, an SOI substrate 20 is manufactured by attaching an N-type second semiconductor substrate 23 to an N-type or P-type first semiconductor substrate 21 with an oxide film 22 interposed therebetween. Then, a groove (trench) reaching the oxide film 22 from the surface of the second semiconductor substrate 23 is formed, and the second semiconductor substrate 23 is divided into a plurality of element formation regions. Next, an oxide film 28 is formed on the surface of the trench, and the inner side thereof is filled with polycrystalline silicon 29 to form a trench isolation region 19.

  Next, P well regions 41a and 41b and P diffusion regions 41c and 41d are formed on the surface of the IGBT forming region and the FWD forming region of the second semiconductor substrate 23, respectively. Further, an N buffer region 42 is formed on the surface of the IGBT forming region. Next, thermal oxide films 43a, 43b, 43c, 43d, 43e, 43f, and 43g are formed on the surface of the second semiconductor substrate 23. Next, a gate insulating film is formed on the P well regions 41a and 41b, and gate electrodes 44a and 44b made of polycrystalline silicon are formed thereon.

Next, the P ⁺ contact regions 45a and 45c and the P ⁺ collector region 45b of the lateral IGBT 13 and the P ⁺ anode regions 45d and 45e of the lateral FWD 14 are formed. Thereafter, N ⁺ emitter regions 46a and 46b of the lateral IGBT 13 and an N ⁺ cathode region 46c of the lateral FWD 14 are formed. Then, after forming an interlayer insulating film 30 such as BPSG on the surface, openings for contact with the semiconductor substrate are opened, and emitter electrodes 47a and 47c and collector electrodes 47b of the lateral IGBT 13 and anode electrodes 47d and 47d of the lateral FWD 14 are formed. 47f and the cathode electrode 47e are formed, and the lateral IGBT 13 and the lateral FWD 14 are completed.

FIG. 3 is a vertical cross-sectional view taken along the line BB ′ of FIG. 1 and shows a cross-sectional configuration of the high voltage NMOSFET 12a. As shown in FIG. 3, the N ⁺ drain region 54 c is formed inside the high breakdown voltage junction termination structure 34. The drain electrode 17a, which is the output electrode for outputting the voltage after the level shift, of the high breakdown voltage NMOSFET 12a is electrically connected to the N ⁺ drain region 54c. The P well regions 52 a and 52 b are formed outside the high breakdown voltage junction termination structure 34. Gate electrode 25 is provided on the substrate surface between P well regions 52a and 52b via a gate insulating film.

P ⁺ contact regions 53a and 53b and N ⁺ source regions 54a and 54b are formed on the surfaces of P well regions 52a and 52b. The source electrodes 26a and 26b, which are input electrodes to which the voltage before the level shift is applied, of the high breakdown voltage NMOSFET 12a are electrically connected to the N ⁺ source regions 54a and 54b and the P ⁺ contact regions 53a and 53b. In order to increase the breakdown voltage due to the RESURF effect, the P diffusion layer 27 a is provided under the thermal oxide film 43 j provided on the substrate surface of the high breakdown voltage junction termination structure 34.

  Further, a P diffusion layer 27b is also provided under the thermal oxide film 43k provided on the substrate surface under the wiring 18a extending from the drain electrode 17a to the drive circuit 16 (not shown). An interlayer insulating film 30 is provided between the wiring 18a and the thermal oxide film 43k. The N well layer 51 for forming the drive circuit 16 of the U-phase upper arm, the output stage element 15 and the like is provided on the opposite side of the high breakdown voltage NMOSFET 12a with the P diffusion layer 27b interposed therebetween. A thermal oxide film 43 h is provided on the trench isolation region 19.

  Further, as shown in FIG. 3, the source electrode 26b and the drain electrode 17a immediately outside the high breakdown voltage junction termination structure 34 are connected to the interlayer insulating film 30 (on the thermal oxide film 43j provided on the high breakdown voltage junction termination structure 34). (Corresponding to the second interlayer insulating film) and has a function as a field plate. Two source electrodes 26 a and 26 b sandwiching the gate electrode 25 may be connected on the interlayer insulating film 30 on the gate electrode 25.

  A method of forming the high breakdown voltage NMOSFET 12a having the configuration shown in FIG. 3 will be described. First, the N well layer 51 is formed in the surface layer of the element formation region of the second semiconductor substrate 23. Next, P diffusion layers 27a and 27b are formed, and P well regions 52a and 52b are formed. Next, thermal oxide films 43h, 43j, and 43k are formed on the surface of the second semiconductor substrate 23. Then, a gate insulating film is formed on the P well regions 52a and 52b, and a gate electrode 25 made of polycrystalline silicon is formed thereon.

Next, P ⁺ contact regions 53a and 53b are formed, followed by N ⁺ source regions 54a and 54b and an N ⁺ drain region 54c. Next, after an interlayer insulating film 30 such as BPSG is formed on the surface, an opening for contact with the semiconductor substrate is opened. Then, the source electrodes 26a and 26b and the drain electrode 17a are formed, and the wiring 18a is formed to complete the high breakdown voltage NMOSFET 12a.

FIG. 4 is a longitudinal sectional view taken along the line CC ′ of FIG. 1 and shows a sectional configuration of the high voltage junction termination structure 34. As shown in FIG. 4, a P diffusion layer 61 is provided under the thermal oxide film 43 n provided on the substrate surface of the high breakdown voltage junction termination structure 34 in order to increase the breakdown voltage by the RESURF effect. The P well region 62 is formed between the high breakdown voltage junction termination structure 34 and the trench isolation region 19 which is the second insulating region. P ⁺ contact region 63 is formed on the surface of P well region 62. The metal electrode 65 a is electrically connected to the P ⁺ contact region 63.

The N well layer 51 is provided in the inner region of the high breakdown voltage junction termination structure 34. N ⁺ contact region 64 is provided on the substrate surface between high voltage junction termination structure 34 and N well layer 51. The metal electrode 65 b is electrically connected to the N ⁺ contact region 64. A thermal oxide film 43 p is provided on the surface of the N well layer 51. A thermal oxide film 43m is also provided on the trench isolation region 19. The metal electrodes 65a and 65b project on the interlayer insulating film 30 on the thermal oxide film 43n provided in the high breakdown voltage junction termination structure 34, thereby functioning as a field plate.

A method of forming the high voltage junction termination structure 34 having the configuration shown in FIG. 4 will be described. First, the N well layer 51 is formed in the surface layer of the element formation region of the second semiconductor substrate 23. Next, a P diffusion layer 61 is formed, and a P well region 62 is formed. Next, thermal oxide films 43m, 43n, and 43p are formed on the surface of the second semiconductor substrate 23. Then, a P ⁺ contact region 63 is formed, and then an N ⁺ contact region 64 is formed. Next, after an interlayer insulating film 30 such as BPSG is formed on the surface, openings for contact with the semiconductor substrate are opened, and metal electrodes 65a and 65b are formed to complete the high voltage junction termination structure 34.

  According to the first embodiment described above, by adopting the self-shielding structure, the wirings 18a and 18b connected to the drain electrodes 17a and 17b only cross over the substrate having the same potential level as the reference potential of the upper arm. Therefore, it is not necessary to make the interlayer insulating film 30 between the wirings 18a and 18b and the substrate specially thick, and it is sufficient if the thickness of the interlayer insulating film 30 is about 1 to 5 μm. Therefore, a one-chip inverter having a high withstand voltage exceeding 1000V can be realized at low cost. Further, the inverter system can be reduced in size.

  Further, according to the first embodiment, since the lateral IGBT 13 and the lateral FWD 14 are shielded by the oxide film 22 of the SOI substrate 20 and the oxide film 28 of the trench isolation region 19, the operation of the parasitic element can be prevented. The operation of the parasitic element is also prevented by the high breakdown voltage junction termination structure 34 being surrounded by the trench isolation region 19. Therefore, the one-chip inverter can be prevented from being broken or malfunctioning, so that a highly reliable one-chip inverter can be obtained.

Embodiment 2. FIG.
FIG. 5 is a main part plan view schematically showing a configuration of the U-phase upper arm of the one-chip inverter according to the second embodiment of the present invention. 6, 7 and 8 are longitudinal sectional views taken along lines DD ′, EE ′ and FF ′ of FIG. 5, respectively. Note that in the second embodiment, the same configurations as those illustrated in FIGS. 1 to 4 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 5, in the one-chip inverter (for U-phase upper arm) 70 of the second embodiment, the high voltage junction termination structure 34 is not surrounded by the trench isolation region 19. On the other hand, the output stage element 15 and the drive circuit 16 are also surrounded by the trench isolation region 19 in the inner region of the high breakdown voltage junction termination structure 34.

Further, as shown in FIGS. 6 to 8, an SOI substrate in which an oxide film 22 is stacked on a first semiconductor substrate 21 and a P-type second semiconductor substrate 123 is bonded thereon as an SOI substrate. A substrate 120 is used. Therefore, the N ⁻ layer 71 is formed on the surface layer of the second semiconductor substrate 123. The high breakdown voltage NMOSFETs 12 a and 12 b, the lateral IGBT 13, the lateral FWD 14, and the high breakdown voltage junction termination structure 34 are formed on the surface side of the N ⁻ layer 71. Other configurations are the same as those of the first embodiment.

  FIG. 6 shows a cross-sectional configuration of the lateral IGBT 13 and the lateral FWD 14 in the second embodiment. As shown in FIG. 6, the trench isolation region 19 penetrates the second semiconductor substrate 123 of the SOI substrate 120 and reaches the oxide film 22 of the SOI substrate 120. The lateral IGBT 13 and the lateral FWD 14 are formed in the IGBT formation region and the FWD formation region surrounded by the trench isolation region 19 and the oxide film 22 of the SOI substrate 120, respectively.

In IGBT forming region, P-well regions 41a, 41b is, N ^- through the layer 71, N of the second semiconductor substrate 123 ^- has reached the lower part of layer 71 (hereinafter referred to as P layer 72) . Further, the P diffusion regions 41 c and 41 d in the FWD formation region also penetrate the N ⁻ layer 71 and reach the P layer 72.

Other configurations of the lateral IGBT 13 and the lateral FWD 14 are the same as those in FIG. In addition, the method for forming the lateral IGBT 13 and the lateral FWD 14 having the configuration shown in FIG. 6 is only to add the step of forming the N ⁻ layer 71 to the method described in the first embodiment.

FIG. 7 shows a cross-sectional configuration of the high breakdown voltage NMOSFET 12a. FIG. 8 shows a cross-sectional configuration of the high voltage junction termination structure 34. As shown in FIGS. 7 and 8, no trench isolation region is provided outside the high voltage junction termination structure 34. The termination portion is formed by a PN junction between the N ⁻ layer 71 and the P layer 72. A P ⁺ contact region 73 for contact with the P layer 72 is provided on the outer surface of the terminal portion. A metal electrode 74 is electrically connected to the P ⁺ contact region 73.

Other configurations of the high voltage NMOSFET 12 and the high voltage junction termination structure 34 are the same as those in FIGS. 3 and 4. Further, the high breakdown voltage NMOSFET 12a having the configuration shown in FIG. 7 and the high breakdown voltage junction termination structure 34 shown in FIG. 8 are formed by adding a process of forming the N ⁻ layer 71 to the method described in the first embodiment, and P ⁺ The P ⁺ contact region 73 may be formed simultaneously with the contact regions 53a, 53b and 63, and the metal electrode 74 may be formed simultaneously with the source electrodes 26a and 26b, the drain electrode 17a and the metal electrodes 65a and 65b.

  According to the second embodiment described above, the following effects are obtained in addition to the same effects as the first embodiment. Since the distance of the high voltage junction termination structure 34 is long, if a trench isolation region (second insulating region) is provided along the outer periphery thereof, a large area is required. In addition, since a crystal defect may occur around the trench isolation region, a device cannot be formed near the trench isolation region.

  For this reason, when a trench isolation region is provided around the high-voltage junction termination structure 34, the effective area of the device is small although the chip area is large. In other words, the chip becomes large. On the other hand, if the trench isolation region is not provided outside the high voltage junction termination structure 34 as in the second embodiment, the chip can be downsized.

  Further, according to the second embodiment, since the output stage element 15 and the drive circuit 16 are surrounded by the trench isolation region 19, the elements constituting the output stage element 15 and the drive circuit 16 and the high voltage junction termination structure It is possible to prevent the operation (such as latch-up) of a parasitic element with an element having a ground (GND) level that constitutes the outer control circuit 11 or the like as a reference potential.

According to the second embodiment, when a high voltage is applied between the collector electrode 47b and the emitter electrodes 47a and 47c of the lateral IGBT 13, only between the P well regions 41a and 41b and the N ⁻ layer 71. In addition, since the depletion layer spreads between the N ⁻ layer 71 and the P layer 72, electric field concentration hardly occurs. Further, when a high voltage is applied between the anode electrodes 47d and 47f and the cathode electrode 47e of the horizontal FWD 14, not only between the P diffusion regions 41c and 41d and the N ⁻ layer 71 but also between the N ⁻ layer 71 and Since the depletion layer spreads between the P layer 72, electric field concentration hardly occurs. Therefore, the high breakdown voltage can be easily increased even if the distance of the high breakdown voltage junction termination structure 34 is short.

Further, according to the second embodiment, the high breakdown voltage junction termination structure 34 is similarly applied with the addition of the PN junction between the N ⁻ layer 71 and the P layer 72, so that the distance of the high breakdown voltage junction termination structure 34 is short. High breakdown voltage can be easily achieved.

  In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. For example, in addition to a high breakdown voltage NMOSFET for a level up circuit for driving the upper arm IGBT as a level shift element, a high breakdown voltage PMOSFET is used for a level down circuit for outputting a sense signal or the like. 34 may be provided across the inside and outside of 34. Alternatively, the conductivity types of the semiconductor layer and the semiconductor region may be reversed.

  The power elements are not limited to IGBTs and FWDs, and IGBTs and FWDs are not limited to the configurations of the above embodiments. Moreover, the arrangement | positioning location of the trench isolation | separation area | region 19 can be suitably changed if the operation | movement of a parasitic element can be prevented. In addition to the three-phase one-chip inverter, the present invention can be applied to a semiconductor device in which a power element, its drive circuit, control circuit, and the like are integrated on one chip.

  As described above, the semiconductor device according to the present invention is useful for a semiconductor device such as a high voltage IC in which a power element and its drive circuit and control circuit are integrated on one chip, and particularly constitutes a one-chip inverter. Suitable for semiconductor devices.

It is a principal part top view which shows typically the structure for the U-phase upper arm of the 1-chip inverter concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in A-A 'of FIG. It is a longitudinal cross-sectional view which shows the cross-sectional structure in B-B 'of FIG. It is a longitudinal cross-sectional view which shows the cross-sectional structure in C-C 'of FIG. It is a principal part top view which shows typically the structure for the U-phase upper arm of the 1-chip inverter concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in D-D 'of FIG. It is a longitudinal cross-sectional view which shows the cross-sectional structure in E-E 'of FIG. It is a longitudinal cross-sectional view which shows the cross-sectional structure in F-F 'of FIG. It is a circuit diagram which shows the structure of a general inverter circuit. It is a principal part top view which shows typically the structure for the U-phase upper arm of the conventional 1-chip inverter. It is a longitudinal cross-sectional view which shows the cross-sectional structure in G-G 'of FIG. It is a principal part top view which shows typically the structure for the U-phase upper arm of the inverter apparatus of the conventional multichip structure. It is a longitudinal cross-sectional view which shows the cross-sectional structure in H-H 'of FIG.

Explanation of symbols

11 logic elements (control circuit)
12a, 12b level shift element (high voltage NMOSFET)
13, 14 Power element (horizontal IGBT, horizontal FWD)
15, 16 Driving means (output stage element, driving circuit)
17a, 17b Output electrode (drain electrode)
18a, 18b wiring 19 insulating region, second insulating region (trench isolation region)
21 Support substrate (first semiconductor substrate)
22 Insulating layer (oxide film)
23 Semiconductor layer (second semiconductor substrate)
26a, 26b Input electrode (source electrode)
30 Interlayer insulating film 34 High voltage junction termination structure 40, 70 Semiconductor device (1-chip inverter)

Claims (10)

A support substrate;
An insulating layer laminated on the support substrate;
A semiconductor layer stacked on the insulating layer;
A high voltage junction termination structure comprising a RESURF structure formed in a loop shape in the surface region of the semiconductor layer;
A power element formed in a region surrounded by the high withstand voltage junction termination structure;
Driving means for the power element formed in a region surrounded by the high voltage junction termination structure;
An insulating region that surrounds the power element in a region surrounded by the high-breakdown-voltage junction termination structure and reaches the insulating layer through the semiconductor layer;
A level shift element having an input electrode to which a voltage before level shift is applied on one side of the high withstand voltage junction termination structure and an output electrode for outputting the voltage after level shift on the other side; ,
Wiring for electrically connecting the output electrode of the level shift element and the driving means;
An interlayer insulating film provided between the semiconductor layer and the wiring;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the driving unit is provided between the high voltage junction termination structure and the insulating region.   The semiconductor device according to claim 1, further comprising a second insulating region that surrounds the high-breakdown-voltage junction termination structure and penetrates the semiconductor layer to reach the insulating layer.   The semiconductor device according to claim 1, wherein the driving unit is surrounded by the insulating region.   The level shift element has a high withstand voltage junction having a drain electrode serving as the output electrode on one side of the high withstand voltage junction termination structure and a gate electrode and a source electrode serving as the input electrode on the other side. The semiconductor device according to claim 1, wherein the semiconductor device is formed of an insulated gate field effect transistor.   The semiconductor device according to claim 1, wherein one or both of an insulated gate bipolar transistor and a diode are formed as the power element.   7. One or both of an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor are formed in the driving means. The semiconductor device described.   The semiconductor device according to claim 1, wherein a logic element is provided in an outer region of the high-voltage junction termination structure of the semiconductor layer.   9. The semiconductor device according to claim 8, wherein one or both of an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor is formed as the logic element. A second interlayer insulating film is formed on the semiconductor layer between the input electrode and the output electrode, and the input electrode and the output electrode protrude to the second interlayer insulating film. The semiconductor device according to claim 1, which also serves as a field plate of the level shift element.

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