WO2011030597A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2011030597A1
WO2011030597A1 PCT/JP2010/060104 JP2010060104W WO2011030597A1 WO 2011030597 A1 WO2011030597 A1 WO 2011030597A1 JP 2010060104 W JP2010060104 W JP 2010060104W WO 2011030597 A1 WO2011030597 A1 WO 2011030597A1
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Prior art keywords
trench isolation
semiconductor
region
electrode
main electrode
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PCT/JP2010/060104
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French (fr)
Japanese (ja)
Inventor
雅人 滝
博臣 江口
峰司 大川
清春 早川
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トヨタ自動車株式会社
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Publication of WO2011030597A1 publication Critical patent/WO2011030597A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0664—Vertical bipolar transistor in combination with diodes

Definitions

  • the present invention relates to a semiconductor device in which different types of semiconductor elements are mounted on one semiconductor layer.
  • Japanese Patent Application Laid-Open No. 2005-64472 and Japanese Patent Application Laid-Open No. 10-200102 disclose an example of a semiconductor device used for an inverter circuit.
  • a lateral IGBT Lateral Insulated Gate Bipolar Transistor
  • LIGBT Lateral Insulated Gate Bipolar Transistor
  • FWD Free Wheeling Diode
  • connection wiring that connects the collector electrode of the LIGBT and the cathode electrode of the FWD is laterally above the n ⁇ type breakdown voltage holding region (also referred to as a drift region) of the LIGBT and FWD. It is extended and arranged.
  • a high voltage is applied to the connection wiring connecting the collector electrode and the cathode electrode.
  • this connection wiring is disposed above the breakdown voltage holding region, the electron concentration on the surface of the breakdown voltage holding region increases due to the potential of the connection wiring, and the charge balance of the breakdown voltage holding region is lost. End up.
  • the breakdown voltage holding region the potential distribution becomes non-uniform, and the expansion of the depletion layer at the time of reverse bias is suppressed, and the breakdown voltage decreases.
  • the interlayer insulating film provided between the semiconductor layer and the connection wiring is formed thicker, it is possible to secure a large distance between the semiconductor layer and the connection wiring, thereby suppressing the influence of the connection wiring. it can.
  • the interlayer insulating film is formed thicker, there is a problem in terms of a decrease in heat dissipation and an increase in manufacturing cost.
  • connection wiring is formed using a bonding wire, a large distance can be ensured between the semiconductor layer and the connection wiring, so that the influence of the connection wiring can be suppressed.
  • the bonding wire becomes a problem in terms of a decrease in reliability due to breakage or the like and an increase in manufacturing cost.
  • the technology disclosed in this specification is intended to provide a semiconductor device in which a decrease in breakdown voltage is suppressed by adopting a new and novel layout.
  • the semiconductor device disclosed in this specification includes a semiconductor layer having a first element region and a second element region, a first type of first semiconductor element, and a second type of second semiconductor element.
  • the first semiconductor element and the second semiconductor element are different types of semiconductor elements.
  • the first semiconductor element is disposed in the first element region of the semiconductor layer and includes a first main electrode and a second main electrode.
  • the first semiconductor element is configured such that a current flows between the first main electrode and the second main electrode.
  • the second semiconductor element is disposed in the second element region of the semiconductor layer and includes a third main electrode and a fourth main electrode.
  • the second semiconductor element is configured such that a current flows between the third main electrode and the fourth main electrode.
  • connection wiring for connecting the first main electrode of the first semiconductor element and the third main electrode of the second semiconductor element becomes unnecessary.
  • the connection wiring for connecting the second main electrode of the first semiconductor element and the fourth main electrode of the second semiconductor element is also unnecessary.
  • a situation in which the potential distribution in the semiconductor layer becomes non-uniform due to the connection wiring as in the conventional semiconductor device is suppressed.
  • a reduction in breakdown voltage is suppressed by adopting a novel layout.
  • one main electrode of the first semiconductor element can be formed without using connection wiring.
  • One main electrode of the second semiconductor element can be brought into contact.
  • FIG. 1 shows an outline of a circuit configuration of an inverter circuit 100.
  • 2 shows a planar layout of the semiconductor device of the first embodiment. The plane layout of each electrode of LIGBT and FWD is shown.
  • FIG. 4 shows a cross-sectional view corresponding to line IV-IV in FIG.
  • FIG. 3 shows a cross-sectional view corresponding to the line VV in FIG. 2.
  • the enlarged plan view of an adjacent part is shown.
  • separation part is shown.
  • separation part was provided is shown.
  • the plane layout of the semiconductor device of 2nd Example is shown. 2 shows a planar layout of a conventional semiconductor device.
  • FIG. 11 is a cross-sectional view corresponding to the line XI-XI in FIG. 10.
  • the semiconductor device disclosed in this specification includes different types of semiconductor elements.
  • Each semiconductor element may include a pair of main electrodes, one main electrode may be disposed on the first trench isolation side, and the other main electrode may be disposed on the second trench isolation side.
  • the direction of the current flowing between the pair of main electrodes may be either. Note that, in adjacent portions where different semiconductor elements are adjacent, the direction of the current flowing between the pair of electrodes of one semiconductor element is substantially parallel to the direction of the current flowing between the pair of electrodes of the other semiconductor element. It is desirable that
  • the different types of semiconductor elements may be a combination of switching elements and switching elements, or a combination of switching elements and free-wheeling diodes.
  • the switching element is preferably a transistor, for example, an IGBT, a MISFET, a MOSFET, or a HEMT.
  • the first trench isolation portion may make a round when the semiconductor layer is viewed in plan.
  • the second trench insulation isolation part may make a round around the first trench insulation isolation part when the semiconductor layer is viewed in plan.
  • the element region sandwiched between the first trench isolation portion and the second trench isolation portion also makes a round when the semiconductor layer is viewed in plan.
  • different types of first semiconductor elements and second semiconductor elements can be mounted with a small mounting area.
  • the element region sandwiched between the first trench isolation portion and the second trench isolation portion reciprocates twice along at least one direction when the semiconductor layer is viewed in plan view. It may be. According to the semiconductor device of this embodiment, the area of the element region occupying the semiconductor layer can be increased, and the mounting area can be reduced.
  • the semiconductor device disclosed in this specification may further include a third trench isolation portion.
  • the third trench isolation portion has a first end and a second end, and may penetrate the semiconductor layer.
  • the first end of the third trench isolation may be in contact with the first trench isolation and the second end of the third trench isolation may be in contact with the second trench isolation.
  • the third trench isolation portion may separate the first element region and the second element region.
  • the first semiconductor element and the second semiconductor element can be electrically separated by the third trench isolation part.
  • a parasitic element structure may be formed between the first semiconductor element and the second semiconductor element. Even in such a case, the provision of the third trench isolation portion prevents the parasitic current from flowing through the parasitic element structure.
  • One main electrode of the semiconductor element may be disposed at least above the first trench isolation portion, and the other main electrode of the semiconductor element may be disposed at least above the second trench isolation portion.
  • the first semiconductor region that is in direct contact with one main electrode of the semiconductor element may be in contact with the side surface of the first trench isolation portion.
  • the second semiconductor region that is in direct contact with the other main electrode of the semiconductor element may be in contact with the side surface of the second trench isolation portion.
  • the first semiconductor region that is in direct contact with one main electrode of the semiconductor element may be provided along the first trench isolation portion when viewed in plan. Furthermore, the second semiconductor region that is in direct contact with the other main electrode of the semiconductor element may also be provided along the second trench isolation portion when viewed in plan.
  • the semiconductor device disclosed in this specification may be mounted on an SOI substrate. Different semiconductor elements may be formed in the semiconductor layer of the SOI substrate.
  • FIG. 1 shows an outline of the circuit configuration of the inverter circuit 100 incorporated in the inverter module.
  • Inverter circuit 100 is provided between high-voltage DC power supply 300 and motor 400, converts DC power supplied from high-voltage DC power supply 300 into AC power, and supplies the AC power to motor 400.
  • the DC power supplied from the high-voltage DC power supply 300 is generally boosted by a converter, and the converter is often incorporated in an inverter module.
  • a capacitor 200 is provided between the high-voltage DC power supply 300 and the inverter circuit 100 to smooth DC power.
  • the inverter circuit 100 includes six semiconductor devices 111-116. As will be described later, the six semiconductor devices 111 to 116 are mounted on one SOI substrate and are configured by one chip. Note that each of the six semiconductor devices 111 to 116 may be mounted on a separate SOI substrate. Each of the semiconductor devices 111 to 116 includes transistors Tr1 to Tr6 and freewheeling diodes D1 to D6 connected in parallel to the transistors Tr1 to Tr6. For the transistors Tr1 to Tr6, a lateral IGBT (Lateral Insulated Gate Bipolar Transistor: hereinafter referred to as LIGBT) is employed.
  • LIGBT Lateral Insulated Gate Bipolar Transistor
  • free-wheeling diodes D1 to D6 free-wheeling diodes (hereinafter referred to as “FWD”) are employed.
  • a gate control signal is applied to the gates of the transistors Tr1 to Tr6 from an inverter drive circuit (not shown).
  • the inverter circuit 100 includes a U-phase arm, a V-phase arm, and a W-phase arm connected in parallel between the high-voltage wiring 100H and the low-voltage wiring 100L of the high-voltage DC power supply 300.
  • the U-phase arm includes semiconductor devices 111 and 112 connected in series via an intermediate node Nm1.
  • the V-phase arm includes semiconductor devices 113 and 114 connected in series via an intermediate node Nm2.
  • the W-phase arm includes semiconductor devices 115 and 116 connected in series via an intermediate node Nm3.
  • the intermediate nodes Nm1 to Nm3 are connected to the phase output lines Uout, Vout, Wout.
  • Each phase output line Uout, Vout, Wout is connected to one end of each phase coil of the three-phase motor 400.
  • the other end of each phase coil is commonly connected to the neutral point.
  • the motor 400 in this example has three phases, but the technology disclosed in this specification can be applied to various AC motors without limiting the number of phases.
  • FIG. 2 is a plan view showing the layout of the semiconductor device.
  • FIG. 3 is a plan view in which the layout of each electrode disposed in the semiconductor device is superimposed on FIG.
  • FIG. 4 is a cross-sectional view corresponding to the line IV-IV in FIG. 2, and shows a cross-sectional view of the LIGBT in the adjacent portion.
  • FIG. 5 is a cross-sectional view corresponding to the line VV in FIG. 2, and shows a cross-sectional view of the FWD in the adjacent portion.
  • the semiconductor layer 26 of the SOI substrate 20 is formed with a first trench isolation portion 12 and a second trench isolation portion 14 that penetrate the semiconductor layer 26.
  • the first trench isolation / separation portion 12 makes a round when the SOI substrate 20 is viewed in plan.
  • the second trench isolation part 14 is provided away from the first trench isolation part 12 and makes a round around the first trench isolation part 12 when the SOI substrate 20 is viewed in plan.
  • the first trench isolation part 12 and the second trench isolation part 14 extend in parallel except for the corners, and the distance between them is constant.
  • the element regions 16 and 18 sandwiched between the first trench isolation portion 12 and the second trench isolation portion 14 are isolated from the peripheral semiconductor layer 26.
  • the first element region 16 and the second element region 18 are adjacent to each other in the adjacent portion 11 when the SOI substrate 20 is viewed in plan.
  • the first element region 16 and the second element region 18 in the adjacent portion 11 are orthogonal to the direction (x-axis direction) connecting the first trench insulation isolation portion 12 and the second trench insulation isolation portion 14. They are arranged so as to oppose each other along (y-axis direction).
  • a LIGBT is provided in the first element region 16, and an FWD is provided in the second element region 18. This example is merely an example, and the layout of the first element region 16 and the second element region 18 can take various forms as necessary.
  • first element region 16 and the second element region 18 may be arranged so as to face each other along the x-axis direction, or may be arranged so as to face each other along other directions.
  • a plurality of first element regions 16 and a plurality of second element regions 18 may be provided.
  • FIG. 4 shows a cross-sectional view of the LIGBT in the vicinity of the adjacent portion 11.
  • the SOI substrate 20 includes a semiconductor support layer 22, a buried insulating layer 24, and a semiconductor layer 26.
  • the semiconductor support layer 22 is formed of single crystal silicon into which an n-type or p-type impurity is introduced at a high concentration.
  • the buried insulating layer 24 is made of silicon oxide.
  • the semiconductor layer 26 is formed of single crystal silicon into which n-type impurities are introduced at a low concentration.
  • the LIGBT is formed in the first element region 16 sandwiched between the first trench isolation part 12 and the second trench isolation part 14.
  • the first trench isolation portion 12 extends through the semiconductor layer 26 to the buried insulating layer 24, and includes a silicon oxide film 12a and a polysilicon core 12b covered with the oxide film 12a.
  • the second trench isolation portion 14 penetrates the semiconductor layer 26 and reaches the buried insulating layer 24, and includes a silicon oxide film 14a and a polysilicon core portion 14b covered with the oxide film 14a. I have.
  • the LIGBT includes a p + type body contact region 31, an n + type emitter region 32, a p type body region 33, an n ⁇ type drift region 34, and an n + type. Embedded region 35, n-type buffer region 36, and p + -type collector region 37.
  • the body contact region 31, the emitter region 32, and the body region 33 are provided on the second trench isolation portion 14 side in the surface layer portion of the semiconductor layer 26.
  • the body contact region 31 and the body region 33 are in contact with the side surface of the second trench isolation portion 14.
  • Emitter region 32 is separated from drift region 34 by body region 33.
  • the drift region 34 is provided between the body region 33 and the buffer region 36 and is a region that holds a potential difference when the LIGBT is turned off.
  • the buried region 35 is provided in the back layer portion of the semiconductor layer 26, and is provided between the first trench insulation isolation portion 12 and the second trench insulation isolation portion 14.
  • the buffer region 36 and the collector region 37 are provided on the first trench isolation portion 12 side in the surface layer portion of the semiconductor layer 26.
  • the buffer region 36 and the collector region 37 are in contact with the side surface of the first trench isolation portion 12.
  • the collector region 37 is separated from the drift region 34 by the buffer region 36.
  • these cross-sectional structures are common throughout the first element region 16. Accordingly, the body contact region 31, the emitter region 32, and the body region 33 are provided over the entire first element region 16 along the side surface of the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. ing. Similarly, the buffer region 36 and the collector region 37 are provided over the entire first element region 16 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
  • the LIGBT further includes an interlayer insulating film 41, a collector electrode 42, a LOCOS (Local Oxidation of Silicon) oxide film 43, a gate electrode 44, a planar gate portion 47, and an emitter electrode 48.
  • an interlayer insulating film 41 As shown in FIG. 4, the LIGBT further includes an interlayer insulating film 41, a collector electrode 42, a LOCOS (Local Oxidation of Silicon) oxide film 43, a gate electrode 44, a planar gate portion 47, and an emitter electrode 48. I have.
  • LOCOS Local Oxidation of Silicon
  • the interlayer insulating film 41 covers the surface of the SOI substrate 20 and is made of silicon oxide.
  • the collector electrode 42 is disposed on the surface of the interlayer insulating film 41 on the first trench isolation portion 12 side. In particular, the collector electrode 42 is also disposed above the first trench isolation portion 12.
  • the collector electrode 42 is disposed above the first trench isolation portion 12 along at least the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, the collector electrode 42 partially extends through the interlayer insulating film 41 and is in contact with the collector region 37 via the contact portion 42a.
  • the contact portion 42 a is provided over the entire first element region 16 along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
  • the collector electrode 42 extends beyond the buffer region 36 in the direction from the first trench isolation part 12 to the second trench isolation part 14 (leftward in the case of FIG. 4) when the SOI substrate 20 is viewed in plan. It is desirable that it is not arranged.
  • the LOCOS oxide film 43 is provided on the surface of the drift region 34 and is made of silicon oxide.
  • the gate electrode 44 is disposed on the surface of the interlayer insulating film 41 between the collector electrode 42 and the emitter electrode 48. A portion of the gate electrode 44 extends through the interlayer insulating film 41 and is in contact with the planar gate portion 47.
  • the planar gate portion 47 has a planar electrode 45 and a gate insulating film 46, and faces the surface of the body region 33 that separates the emitter region 32 and the drift region 34.
  • the planar electrode 45 covers the surface of the gate insulating film 46 and a part of the surface of the LOCOS oxide film 43, and is formed of polysilicon into which impurities are introduced at a high concentration.
  • the gate insulating film 46 is made of silicon oxide.
  • the emitter electrode 48 is disposed on the surface of the interlayer insulating film 41 on the second trench isolation portion 14 side. In particular, the emitter electrode 48 is also disposed above the second trench isolation portion 14. The emitter electrode 48 is disposed above the second trench isolation part 14 along at least the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Further, the emitter electrode 48 partially extends through the interlayer insulating film 41 and is in contact with the body contact region 31 and the emitter region 32 via the contact portion 48a. The contact portion 48 a is provided over the entire first element region 16 along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. As described above, in the adjacent portion 11, the collector electrode 42 and the emitter electrode 48 are arranged with an interval in the x-axis direction, and the gate electrode 44 is arranged within the interval.
  • the FWD includes a p + type anode contact region 131, a p type anode region 133, an n type cathode region 136, an n + type cathode contact region 137, a cathode electrode 142, and an anode electrode 148. It is different from LIGBT in that it is.
  • the anode contact region 131 and the anode region 133 are provided on the second trench isolation portion 14 side in the surface layer portion of the semiconductor layer 26. In particular, the anode contact region 131 and the anode region 133 are in contact with the side surface of the second trench isolation portion 14.
  • the anode region 133 is manufactured by the same manufacturing process as the body region 33 of the LIGBT, and has the same dopant, concentration, and diffusion depth as the body region 33.
  • the cathode region 136 and the cathode contact region 137 are provided on the first trench isolation portion 12 side in the surface layer portion of the semiconductor layer 26. In particular, the cathode region 136 and the cathode contact region 137 are in contact with the side surfaces of the first trench isolation portion 12.
  • the cathode region 136 is manufactured in the same manufacturing process as the buffer region 36 of the LIGBT, and has the same dopant, concentration, and diffusion depth as the buffer region 36. These cross-sectional structures are common throughout the second element region 18. Therefore, the anode contact region 131 and the anode region 133 are provided over the entire second element region 18 along the side surface of the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Similarly, the cathode region 136 and the cathode contact region 137 are provided over the entire second element region 18 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
  • the body region 33 of the LIGBT and the anode region 133 of the FWD are in contact with each other at the adjacent portion 11 shown in FIG. For this reason, these p-type regions 33 and 133 circulate in the element regions 16 and 18 along the side surfaces of the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan.
  • the buffer region 36 of the LIGBT and the cathode region 136 of the FWD are also in contact with each other at the adjacent portion 11 shown in FIG. For this reason, these n-type regions 36 and 136 also circulate in the element regions 16 and 18 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
  • the cathode electrode 142 is disposed on the surface of the interlayer insulating film 41 on the first trench isolation portion 12 side. In particular, the cathode electrode 142 is also disposed above the first trench isolation portion 12. The cathode electrode 142 is disposed above the first trench isolation portion 12 along at least the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, a part of the cathode electrode 142 extends through the interlayer insulating film 41 and is in contact with the cathode contact region 137 through the contact portion 137a. The contact portion 137 a is provided over the entire second element region 18 along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, the cathode electrode 142 is disposed beyond the cathode region 136 in the direction from the first trench insulation isolation portion 12 to the second trench insulation isolation portion 14 (leftward in the case of FIG. 5) when viewed in plan. Desirably not.
  • the anode electrode 148 is disposed on the surface of the interlayer insulating film 41 on the second trench isolation portion 14 side. In particular, the anode electrode 148 is also disposed above the second trench isolation portion 14. The anode electrode 148 is disposed above the second trench isolation part 14 along at least the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Further, a part of the anode electrode 148 extends through the interlayer insulating film 41 and is in contact with the anode contact region 131 through the contact portion 148a. The contact portion 148a is provided over the entire second element region 18 along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan.
  • the anode electrode 148 preferably extends partially through the interlayer insulating film 41 and is in contact with the planar electrode 45. Further, the anode electrode 148 is disposed beyond the planar electrode 45 in the direction from the second trench insulation isolation portion 14 to the first trench insulation isolation portion 12 (rightward in the case of FIG. 5) when viewed in plan. Desirably not. As described above, in the adjacent portion 11, the cathode electrode 142 and the anode electrode 148 are arranged at an interval in the x-axis direction.
  • the contact portion 48a of the emitter electrode 48 of the LIGBT and the contact portion 148a of the anode electrode 148 of the FWD are adjacent to each other in the adjacent portion 11 shown in FIG. For this reason, these contact portions 48 a and 148 a make a round along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan.
  • the contact portion 42a of the collector electrode 42 of the LIGBT and the contact portion 142a of the cathode electrode 142 of the FWD are also adjacent in the adjacent portion 11 shown in FIG. For this reason, these contact portions 42 a and 142 a make a round along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
  • the collector electrode 42, the gate electrode 44, and the emitter electrode 48 of the LIGBT, and the cathode electrode 142 and the anode electrode 148 of the FWD are manufactured in the same manufacturing process using vapor deposition technology. Aluminum is used as the material for these electrodes.
  • the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are provided in a range inside the first trench isolation portion 12 when viewed in plan. That is, the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are one common electrode.
  • a collector / cathode bonding pad 19 is provided on the one common electrode.
  • the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are provided in a range outside the second trench isolation portion 14. That is, the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are also one common electrode. An emitter / anode bonding pad 15 is provided on the one common electrode.
  • the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are configured as one common electrode. For this reason, the connection wiring which connects the collector electrode 42 and the cathode electrode 142 is unnecessary. Further, the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are also configured as one common electrode. For this reason, the connection wiring which connects the emitter electrode 48 and the anode electrode 148 is also unnecessary. Thereby, these connection wirings do not extend above the drift region 34 of the LIGBT and FWD. Therefore, in the semiconductor device of the present embodiment, unlike the conventional structure shown in FIGS. 10 and 11, a situation where the potential distribution in the drift region becomes non-uniform does not occur.
  • the common electrode of the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD is disposed inside, the emitter electrode 48 of the LIGBT, and the anode electrode of the FWD.
  • 148 common electrodes are arranged around it so as to surround them.
  • the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are connected to the high voltage side of the high voltage DC power supply 300, and the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are connected to the high voltage DC power supply 300. Connected to the low pressure side.
  • the low-voltage common electrode is provided so as to surround the high-voltage common electrode.
  • the semiconductor devices 111 to 116 shown in FIG. 1 are mounted on one SOI substrate 20. Therefore, the voltage difference between the plurality of semiconductor devices can be reduced by arranging the common electrode on the low voltage side around.
  • FIG. 6 shows an enlarged plan view of the adjacent portion 11 where the first element region 16 and the second element region 18 are adjacent to each other.
  • the LIGBT and the FWD are provided adjacent to each other, there is a parasitic MOS composed of the emitter region 32 of the LIGBT, the body region 33, the drift region 34, and the cathode region 136 of the FWD.
  • the area of the adjacent portion 11 where the LIGBT and the FWD are in contact is smaller than the entire area of the LIGBT and the FWD. Therefore, when the LIGBT is turned on, the phenomenon that the parasitic MOS as shown by the broken line arrow in FIG. As a result, in the semiconductor device of this embodiment, when the LIGBT is turned on, the IGBT operation becomes dominant and a low on-voltage can be obtained.
  • the semiconductor device of this embodiment further includes a third trench isolation 13.
  • the first end 13 ⁇ / b> A is in contact with the first trench isolation 12 and the second end 13 ⁇ / b> B is in contact with the second trench isolation 14.
  • the first element region 16 and the second element region 18 are separated by the third trench isolation portion 13.
  • the third trench isolation part 13 also includes a silicon oxide film 13a and a polysilicon core part 13b covered with the oxide film 13a.
  • FIG. 9 is a plan view showing the layout of the semiconductor device of the second embodiment. Constituent elements common to the semiconductor device of the first embodiment are denoted by common reference numerals and description thereof is omitted.
  • the y axis It is characterized by reciprocating along the direction. In this example, part of the element regions 16 and 18 reciprocate four times along the y-axis direction.
  • a part 52 of the semiconductor layer 26 surrounded by the first trench isolation portion 12 has a comb-like shape when the SOI substrate 20 is viewed in plan view.
  • the FWD is arranged on the inner side and the LIGBT is arranged so as to surround it.
  • LIGBT has a large switching loss
  • the amount of heat generated during operation is larger than that of FWD. Therefore, when the FWD having a small heat generation amount is arranged in the central portion and the LIGBT having a large heat generation amount is arranged around, the entire temperature distribution of the semiconductor device is made uniform, and the situation where the central portion becomes locally high is suppressed. be able to. Thereby, malfunction and damage of the semiconductor device due to high temperature are suppressed.
  • silicon is used as the semiconductor material of the SOI substrate.
  • other semiconductor materials may be used.
  • a compound semiconductor such as gallium nitride, silicon carbide, or gallium arsenide may be used.

Abstract

Disclosed is a semiconductor device which comprises an LIGBT that is arranged in a first element region and an FWD that is arranged in a second element region. The first element region and the second element regions are arranged side by side along the y-axis direction in an adjacence portion when the SOI substrate is viewed in plan. The collector electrode and the emitter electrode of the LIGBT are arranged at a distance along the x-axis direction in the adjacence portion when the SOI substrate is viewed in plan. The cathode electrode and the anode electrode of the FWD are arranged at a distance along the x-axis direction in the adjacence portion when the SOI substrate is viewed in plan. The collector electrode of the LIGBT and the cathode electrode of the FWD are in contact with each other, while the emitter electrode of the LIGBT and the anode electrode of the FWD are in contact with each other.

Description

半導体装置Semiconductor device
　本出願は、２００９年９月１１日に出願された日本国特許出願第２００９－２０９９８７号に基づく優先権を主張する。その出願の全ての内容は、この明細書中に参照により援用されている。
　本発明は、１つの半導体層に異なる種類の半導体素子が搭載された半導体装置に関する。 This application claims priority based on Japanese Patent Application No. 2009-209987 filed on Sep. 11, 2009. The entire contents of that application are incorporated herein by reference.
The present invention relates to a semiconductor device in which different types of semiconductor elements are mounted on one semiconductor layer.
　近年、１つの半導体層に異なる種類の半導体素子が搭載された半導体装置の開発が進められている。例えば、スイッチング用の半導体素子と還流用の半導体素子が１つの半導体層に搭載された半導体装置が開発されている。この種の半導体装置は、用途に応じて様々な電気制御回路に組み込まれて用いられる。例えば、直流電力を交流電力に変換するインバータ回路は、この種の半導体装置の複数個が接続されることによって構成されている。 In recent years, development of semiconductor devices in which different types of semiconductor elements are mounted on one semiconductor layer has been underway. For example, a semiconductor device in which a switching semiconductor element and a refluxing semiconductor element are mounted on one semiconductor layer has been developed. This type of semiconductor device is used by being incorporated into various electric control circuits depending on the application. For example, an inverter circuit that converts DC power to AC power is configured by connecting a plurality of semiconductor devices of this type.
　特開２００５－６４４７２号公報及び特開平１０－２００１０２号公報には、インバータ回路に用いられる半導体装置の一例が開示されている。これらの半導体装置では、横型のＩＧＢＴ（Lateral Insulated Gate Bipolar Transistor：以下、ＬＩＧＢＴという）と還流用ダイオード（Free Wheeling Diode：以下、ＦＷＤという）が１つのＳＯＩ（Semiconductor on Insulator）基板に搭載されている。 Japanese Patent Application Laid-Open No. 2005-64472 and Japanese Patent Application Laid-Open No. 10-200102 disclose an example of a semiconductor device used for an inverter circuit. In these semiconductor devices, a lateral IGBT (Lateral Insulated Gate Bipolar Transistor) (hereinafter referred to as LIGBT) and a freewheeling diode (Free Wheeling Diode) (hereinafter referred to as FWD) are mounted on a single SOI (Semiconductor On On Insulator) substrate. .
　図１０及び図１１に、特開２００５－６４４７２号公報で開示される半導体装置の構成を概略して示す。図１０に、半導体装置の平面レイアウトを示す。図１１に、図１０のXI－XI線に対応した断面図を示す。図１０及び図１１に示されるように、ＳＯＩ基板の半導体層を貫通してトレンチ絶縁分離部が形成されており、そのトレンチ絶縁分離部によって半導体層の一部が２つの素子領域に区画されている。一方の素子領域にはＬＩＧＢＴが配置されており、他方の素子領域にはＦＷＤが配置されている。 10 and 11 schematically show the configuration of the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2005-64472. FIG. 10 shows a planar layout of the semiconductor device. FIG. 11 is a cross-sectional view corresponding to the line XI-XI in FIG. As shown in FIGS. 10 and 11, a trench insulation isolation portion is formed through the semiconductor layer of the SOI substrate, and a part of the semiconductor layer is partitioned into two element regions by the trench insulation isolation portion. Yes. The LIGBT is disposed in one element region, and the FWD is disposed in the other element region.
　図１０に示されるように、ＬＩＧＢＴは、実装面積を小さくするために、コレクタ電極の周囲をエミッタ電極が一巡する構成を備えている。ＦＷＤも同様に、実装面積を小さくするために、カソード電極の周囲をアノード電極が一巡する構成を備えている。コレクタ電極とカソード電極は、ＳＯＩ基板の上方を横方向に伸びて配設されている接続配線を介して電気的に接続されている。エミッタ電極とアノード電極も、ＳＯＩ基板の上方を横方向に伸びて配設されている接続配線を介して電気的に接続されている。 As shown in FIG. 10, the LIGBT has a configuration in which the emitter electrode makes a round around the collector electrode in order to reduce the mounting area. Similarly, the FWD has a configuration in which the anode electrode makes a round around the cathode electrode in order to reduce the mounting area. The collector electrode and the cathode electrode are electrically connected to each other via a connection wiring that extends in the lateral direction above the SOI substrate. The emitter electrode and the anode electrode are also electrically connected through a connection wiring arranged extending in the lateral direction above the SOI substrate.
　図１１に示されるように、ＬＩＧＢＴのコレクタ電極とＦＷＤのカソード電極を接続する接続配線の一部は、ＬＩＧＢＴ及びＦＷＤのｎ－型の耐圧保持領域（ドリフト領域ともいう）の上方を横方向に伸びて配設されている。通常、コレクタ電極とカソード電極を接続する接続配線には高電圧が印加されている。このため、この接続配線が耐圧保持領域の上方に配設されていると、この接続配線の電位に誘起されて耐圧保持領域の表面の電子濃度が増加し、耐圧保持領域のチャージバランスが崩れてしまう。この結果、耐圧保持領域は、電位分布が不均一となり、逆バイアス時の空乏層の伸びが抑制され、耐圧が低下してしまう。 As shown in FIG. 11, a part of the connection wiring that connects the collector electrode of the LIGBT and the cathode electrode of the FWD is laterally above the n − type breakdown voltage holding region (also referred to as a drift region) of the LIGBT and FWD. It is extended and arranged. Usually, a high voltage is applied to the connection wiring connecting the collector electrode and the cathode electrode. For this reason, if this connection wiring is disposed above the breakdown voltage holding region, the electron concentration on the surface of the breakdown voltage holding region increases due to the potential of the connection wiring, and the charge balance of the breakdown voltage holding region is lost. End up. As a result, in the breakdown voltage holding region, the potential distribution becomes non-uniform, and the expansion of the depletion layer at the time of reverse bias is suppressed, and the breakdown voltage decreases.
　例えば、半導体層と接続配線の間に設けられている層間絶縁膜をより厚く形成すれば、半導体層と接続配線の間の距離を大きく確保することができるので、接続配線の影響を抑えることができる。しかしながら、層間絶縁膜をより厚く形成すると、放熱性の低下及び製造コストの増加の点で問題となる。 For example, if the interlayer insulating film provided between the semiconductor layer and the connection wiring is formed thicker, it is possible to secure a large distance between the semiconductor layer and the connection wiring, thereby suppressing the influence of the connection wiring. it can. However, if the interlayer insulating film is formed thicker, there is a problem in terms of a decrease in heat dissipation and an increase in manufacturing cost.
　また、ボンディングワイヤを用いて接続配線を形成すれば、半導体層と接続配線の間の距離を大きく確保することができるので、接続配線の影響を抑えることができる。しかしながら、ボンディングワイヤは、破損等による信頼性の低下及び製造コストの増加の点で問題となる。 Further, if the connection wiring is formed using a bonding wire, a large distance can be ensured between the semiconductor layer and the connection wiring, so that the influence of the connection wiring can be suppressed. However, the bonding wire becomes a problem in terms of a decrease in reliability due to breakage or the like and an increase in manufacturing cost.
　上記の説明では、特開２００５－６４４７２号公報で開示される半導体装置を例にして、接続配線に起因した耐圧低下の課題を説明したが、同様の課題は特開平１０－２００１０２号公報で開示される半導体装置にも存在する。また、同様の課題は、ＬＩＧＢＴとＦＷＤを１つの半導体層に搭載した半導体装置に限らず、異なる種類の半導体素子を１つの半導体層に搭載する半導体装置において広く存在する。 In the above description, the problem of the breakdown voltage reduction caused by the connection wiring has been described by taking the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2005-64472 as an example, but the same problem is disclosed in Japanese Patent Application Laid-Open No. 10-200102. Also present in semiconductor devices. A similar problem is not limited to semiconductor devices in which LIGBT and FWD are mounted on one semiconductor layer, but also widely exist in semiconductor devices in which different types of semiconductor elements are mounted on one semiconductor layer.
　本明細書で開示される技術は、新規で斬新なレイアウトを採用することにより、耐圧の低下が抑制される半導体装置を提供することを目的としている。 The technology disclosed in this specification is intended to provide a semiconductor device in which a decrease in breakdown voltage is suppressed by adopting a new and novel layout.
　本明細書で開示される半導体装置は、第１素子領域と第２素子領域を有する半導体層と、第１種類の第１半導体素子と、第２種類の第２半導体素子を備えている。第１半導体素子と第２半導体素子は、異なる種類の半導体素子である。第１半導体素子は、半導体層の第１素子領域に配置されており、第１主電極と第２主電極を備えている。第１半導体素子は、第１主電極と第２主電極の間を電流が流れるように構成されている。第２半導体素子は、半導体層の第２素子領域に配置されており、第３主電極と第４主電極を備えている。第２半導体素子は、第３主電極と第４主電極の間を電流が流れるように構成されている。第１素子領域と第２素子領域は、半導体層を平面視したときに、隣接部において第１方向に沿って並んでいる。第１半導体素子の第１主電極と第２主電極は、半導体層を平面視したときに、隣接部において、第２方向に間隔を置いて配置されている。第２半導体素子の第３主電極と第４主電極も、半導体層を平面視したときに、隣接部において、第２方向に間隔を置いて配置されている。第２方向は、第１方向に対して直交する方向である。ここで、隣接部において、第１半導体素子の第１主電極と第２半導体素子の第３主電極が接している。さらに、隣接部において、第１半導体素子の第２主電極と第２半導体素子の第４主電極も接している。この構成によると、第１半導体素子の第１主電極と第２半導体素子の第３主電極を接続する接続配線が不要となる。同様に、第１半導体素子の第２主電極と第２半導体素子の第４主電極を接続する接続配線も不要となる。このため、本明細書で開示される半導体装置では、従来の半導体装置のように、接続配線に起因して半導体層内の電位分布が不均一となる事態が抑制される。本明細書で開示される半導体装置では、斬新なレイアウトを採用することにより、耐圧の低下が抑制される。 The semiconductor device disclosed in this specification includes a semiconductor layer having a first element region and a second element region, a first type of first semiconductor element, and a second type of second semiconductor element. The first semiconductor element and the second semiconductor element are different types of semiconductor elements. The first semiconductor element is disposed in the first element region of the semiconductor layer and includes a first main electrode and a second main electrode. The first semiconductor element is configured such that a current flows between the first main electrode and the second main electrode. The second semiconductor element is disposed in the second element region of the semiconductor layer and includes a third main electrode and a fourth main electrode. The second semiconductor element is configured such that a current flows between the third main electrode and the fourth main electrode. The first element region and the second element region are arranged along the first direction in the adjacent portion when the semiconductor layer is viewed in plan. The first main electrode and the second main electrode of the first semiconductor element are arranged at an interval in the second direction at an adjacent portion when the semiconductor layer is viewed in plan. The third main electrode and the fourth main electrode of the second semiconductor element are also arranged at an interval in the second direction in the adjacent portion when the semiconductor layer is viewed in plan. The second direction is a direction orthogonal to the first direction. Here, in the adjacent portion, the first main electrode of the first semiconductor element and the third main electrode of the second semiconductor element are in contact with each other. Further, in the adjacent portion, the second main electrode of the first semiconductor element and the fourth main electrode of the second semiconductor element are also in contact. According to this configuration, the connection wiring for connecting the first main electrode of the first semiconductor element and the third main electrode of the second semiconductor element becomes unnecessary. Similarly, the connection wiring for connecting the second main electrode of the first semiconductor element and the fourth main electrode of the second semiconductor element is also unnecessary. For this reason, in the semiconductor device disclosed in this specification, a situation in which the potential distribution in the semiconductor layer becomes non-uniform due to the connection wiring as in the conventional semiconductor device is suppressed. In the semiconductor device disclosed in this specification, a reduction in breakdown voltage is suppressed by adopting a novel layout.
　本明細書で開示される技術によると、第１半導体素子と第２半導体素子が１つの半導体層に搭載される半導体装置において、接続配線を用いることなく、第１半導体素子の１つの主電極と第２半導体素子の１つの主電極を接触させることができる。これにより、接続配線を利用した場合に生じる半導体層内の電位分布の不均一化を回避することができる。 According to the technique disclosed in this specification, in a semiconductor device in which a first semiconductor element and a second semiconductor element are mounted on one semiconductor layer, one main electrode of the first semiconductor element can be formed without using connection wiring. One main electrode of the second semiconductor element can be brought into contact. As a result, it is possible to avoid non-uniform potential distribution in the semiconductor layer that occurs when the connection wiring is used.
インバータ回路１００の回路構成の概略を示す。1 shows an outline of a circuit configuration of an inverter circuit 100. 第１実施例の半導体装置の平面レイアウトを示す。2 shows a planar layout of the semiconductor device of the first embodiment. ＬＩＧＢＴ及びＦＷＤの各電極の平面レイアウトを示す。The plane layout of each electrode of LIGBT and FWD is shown. 図２のIV－IV線に対応した断面図を示す。FIG. 4 shows a cross-sectional view corresponding to line IV-IV in FIG. 図２のV－V線に対応した断面図を示す。FIG. 3 shows a cross-sectional view corresponding to the line VV in FIG. 2. 隣接部の拡大平面図を示す。The enlarged plan view of an adjacent part is shown. 第３トレンチ絶縁分離部が設けられた半導体装置の平面レイアウトを示す。The planar layout of the semiconductor device provided with the 3rd trench insulation isolation | separation part is shown. 第３トレンチ絶縁分離部が設けられた隣接部の拡大平面図を示す。The enlarged plan view of the adjacent part in which the 3rd trench insulation isolation | separation part was provided is shown. 第２実施例の半導体装置の平面レイアウトを示す。The plane layout of the semiconductor device of 2nd Example is shown. 従来の半導体装置の平面レイアウトを示す。2 shows a planar layout of a conventional semiconductor device. 図１０のXI－XI線に対応した断面図を示す。FIG. 11 is a cross-sectional view corresponding to the line XI-XI in FIG. 10.
　本明細書で開示される半導体装置は、異なる種類の半導体素子を備えている。各半導体素子は、一対の主電極を備えており、一方の主電極が第１トレンチ絶縁分離側に配置されており、他方の主電極が第２トレンチ絶縁分離側に配置されていてもよい。一対の主電極間を流れる電流の向きはどちらでもよい。なお、異なる半導体素子が隣接する隣接部において、一方の半導体素子の一対の電極間を流れる電流の向きと他方の半導体素子の一対の電極間を流れる電流の向きは略平行であり、且つ同じ向きであるのが望ましい。異なる種類の半導体素子は、スイッチング素子とスイッチング素子の組合せでもよく、スイッチング素子と還流ダイオードの組合せでもよい。スイッチング素子は、トランジスタであるのが望ましく、例えば、ＩＧＢＴ、ＭＩＳＦＥＴ、ＭＯＳＦＥＴ、ＨＥＭＴであるのが望ましい。 The semiconductor device disclosed in this specification includes different types of semiconductor elements. Each semiconductor element may include a pair of main electrodes, one main electrode may be disposed on the first trench isolation side, and the other main electrode may be disposed on the second trench isolation side. The direction of the current flowing between the pair of main electrodes may be either. Note that, in adjacent portions where different semiconductor elements are adjacent, the direction of the current flowing between the pair of electrodes of one semiconductor element is substantially parallel to the direction of the current flowing between the pair of electrodes of the other semiconductor element. It is desirable that The different types of semiconductor elements may be a combination of switching elements and switching elements, or a combination of switching elements and free-wheeling diodes. The switching element is preferably a transistor, for example, an IGBT, a MISFET, a MOSFET, or a HEMT.
　本明細書で開示される半導体装置では、第１トレンチ絶縁分離部が、半導体層を平面視したときに一巡していてもよい。また、第２トレンチ絶縁分離部が、半導体層を平面視したときに第１トレンチ絶縁分離部の周囲を一巡していてもよい。これにより、第１トレンチ絶縁分離部と第２トレンチ絶縁分離部で挟まれた素子領域も、半導体層を平面視したときに一巡している。この形態の半導体装置によると、異なる種類の第１半導体素子と第２半導体素子を小さい実装面積で搭載することができる。 In the semiconductor device disclosed in this specification, the first trench isolation portion may make a round when the semiconductor layer is viewed in plan. Further, the second trench insulation isolation part may make a round around the first trench insulation isolation part when the semiconductor layer is viewed in plan. As a result, the element region sandwiched between the first trench isolation portion and the second trench isolation portion also makes a round when the semiconductor layer is viewed in plan. According to the semiconductor device of this embodiment, different types of first semiconductor elements and second semiconductor elements can be mounted with a small mounting area.
　本明細書で開示される半導体装置では、第１トレンチ絶縁分離部と第２トレンチ絶縁分離部で挟まれた素子領域が、半導体層を平面視したときに、少なくとも一方向に沿って２往復していてもよい。この形態の半導体装置によると、半導体層に占める素子領域の面積を大きくすることができ、実装面積を小さく抑えることができる。 In the semiconductor device disclosed in this specification, the element region sandwiched between the first trench isolation portion and the second trench isolation portion reciprocates twice along at least one direction when the semiconductor layer is viewed in plan view. It may be. According to the semiconductor device of this embodiment, the area of the element region occupying the semiconductor layer can be increased, and the mounting area can be reduced.
　本明細書で開示される半導体装置は、第３トレンチ絶縁分離部をさらに備えていてもよい。第３トレンチ絶縁分離部は、第１端部と第２端部を有しており、半導体層を貫通していてもよい。第３トレンチ絶縁分離部の第１端部が第１トレンチ絶縁分離部に接しており、第３トレンチ絶縁分離部の第２端部が第２トレンチ絶縁分離部に接していてもよい。さらに、第３トレンチ絶縁分離部は、第１素子領域と第２素子領域を隔てていてもよい。この形態の半導体装置によると、第３トレンチ絶縁分離部によって第１半導体素子と第２半導体素子を電気的に分離することができる。例えば、第１半導体素子と第２半導体素子に採用される構成によっては、第１半導体素子と第２半導体素子の間に寄生の素子構造が形成されることがある。そのような場合でも、第３トレンチ絶縁分離部が設けられていると、その寄生の素子構造を介して寄生電流が流れることが防止される。 The semiconductor device disclosed in this specification may further include a third trench isolation portion. The third trench isolation portion has a first end and a second end, and may penetrate the semiconductor layer. The first end of the third trench isolation may be in contact with the first trench isolation and the second end of the third trench isolation may be in contact with the second trench isolation. Furthermore, the third trench isolation portion may separate the first element region and the second element region. According to the semiconductor device of this aspect, the first semiconductor element and the second semiconductor element can be electrically separated by the third trench isolation part. For example, depending on the configuration employed for the first semiconductor element and the second semiconductor element, a parasitic element structure may be formed between the first semiconductor element and the second semiconductor element. Even in such a case, the provision of the third trench isolation portion prevents the parasitic current from flowing through the parasitic element structure.
　半導体素子の一方の主電極が少なくとも第１トレンチ絶縁分離部の上方に配設されており、半導体素子の他方の主電極が少なくとも第２トレンチ絶縁分離部の上方に配設されていてもよい。 One main electrode of the semiconductor element may be disposed at least above the first trench isolation portion, and the other main electrode of the semiconductor element may be disposed at least above the second trench isolation portion.
　半導体素子の一方の主電極が直接的に接する第１半導体領域は、第１トレンチ絶縁分離部の側面に接していてもよい。また、半導体素子の他方の主電極が直接的に接する第２半導体領域は、第２トレンチ絶縁分離部の側面に接していてもよい。 The first semiconductor region that is in direct contact with one main electrode of the semiconductor element may be in contact with the side surface of the first trench isolation portion. In addition, the second semiconductor region that is in direct contact with the other main electrode of the semiconductor element may be in contact with the side surface of the second trench isolation portion.
　半導体素子の一方の主電極が直接的に接する第１半導体領域は、平面視したときに、第１トレンチ絶縁分離部に沿って設けられていてもよい。さらに、半導体素子の他方の主電極が直接的に接する第２半導体領域も、平面視したときに、第２トレンチ絶縁分離部に沿って設けられていてもよい。 The first semiconductor region that is in direct contact with one main electrode of the semiconductor element may be provided along the first trench isolation portion when viewed in plan. Furthermore, the second semiconductor region that is in direct contact with the other main electrode of the semiconductor element may also be provided along the second trench isolation portion when viewed in plan.
　本明細書で開示される半導体装置は、ＳＯＩ基板に搭載されていてもよい。異なる半導体素子は、ＳＯＩ基板の半導体層に形成されていてもよい。 The semiconductor device disclosed in this specification may be mounted on an SOI substrate. Different semiconductor elements may be formed in the semiconductor layer of the SOI substrate.
　図１に、インバータモジュールに組み込まれているインバータ回路１００の回路構成の概略を示す。インバータ回路１００は、高圧直流電源３００とモータ４００の間に設けられており、高圧直流電源３００から供給される直流電力を交流電力に変換し、その交流電力をモータ４００に供給する。なお、高圧直流電源３００から供給される直流電力は、一般的にコンバータによって昇圧されることが多く、そのコンバータもインバータモジュール内に組み込まれていることが多い。高圧直流電源３００とインバータ回路１００の間には、コンデンサ２００が設けられており、直流電力を平滑化している。 FIG. 1 shows an outline of the circuit configuration of the inverter circuit 100 incorporated in the inverter module. Inverter circuit 100 is provided between high-voltage DC power supply 300 and motor 400, converts DC power supplied from high-voltage DC power supply 300 into AC power, and supplies the AC power to motor 400. Note that the DC power supplied from the high-voltage DC power supply 300 is generally boosted by a converter, and the converter is often incorporated in an inverter module. A capacitor 200 is provided between the high-voltage DC power supply 300 and the inverter circuit 100 to smooth DC power.
　図１に示されるように、インバータ回路１００は、６つの半導体装置１１１～１１６を備えている。後述するように、６つの半導体装置１１１～１１６は、１つのＳＯＩ基板に搭載されており、１チップで構成されている。なお、６つの半導体装置１１１～１１６は、それぞれが別個のＳＯＩ基板に搭載されてもよい。各半導体装置１１１～１１６は、トランジスタＴｒ１～Ｔｒ６と、そのトランジスタＴｒ１～Ｔｒ６に並列に接続されている還流用のダイオードＤ１～Ｄ６を備えている。トランジスタＴｒ１～Ｔｒ６には、横型のＩＧＢＴ（Lateral Insulated Gate Bipolar Transistor：以下、ＬＩＧＢＴという）が採用されている。還流用のダイオードＤ１～Ｄ６には、還流用のダイオード（Free Wheeling Diode：以下、ＦＷＤという）が採用されている。各トランジスタＴｒ１～Ｔｒ６のゲートには、図示しないインバータ駆動回路からゲート制御信号が印加されている。 As shown in FIG. 1, the inverter circuit 100 includes six semiconductor devices 111-116. As will be described later, the six semiconductor devices 111 to 116 are mounted on one SOI substrate and are configured by one chip. Note that each of the six semiconductor devices 111 to 116 may be mounted on a separate SOI substrate. Each of the semiconductor devices 111 to 116 includes transistors Tr1 to Tr6 and freewheeling diodes D1 to D6 connected in parallel to the transistors Tr1 to Tr6. For the transistors Tr1 to Tr6, a lateral IGBT (Lateral Insulated Gate Bipolar Transistor: hereinafter referred to as LIGBT) is employed. As the free-wheeling diodes D1 to D6, free-wheeling diodes (hereinafter referred to as “FWD”) are employed. A gate control signal is applied to the gates of the transistors Tr1 to Tr6 from an inverter drive circuit (not shown).
　図１に示されるように、インバータ回路１００は、高圧直流電源３００の高圧配線１００Ｈと低圧配線１００Ｌの間に並列に接続されているＵ相アーム、Ｖ相アーム及びＷ相アームを備えている。Ｕ相アームは、中間ノードＮｍ１を介して直列に接続された半導体装置１１１，１１２で構成されている。Ｖ相アームは、中間ノードＮｍ２を介して直列に接続された半導体装置１１３，１１４で構成されている。Ｗ相アームは、中間ノードＮｍ３を介して直列に接続された半導体装置１１５，１１６で構成されている。 As shown in FIG. 1, the inverter circuit 100 includes a U-phase arm, a V-phase arm, and a W-phase arm connected in parallel between the high-voltage wiring 100H and the low-voltage wiring 100L of the high-voltage DC power supply 300. The U-phase arm includes semiconductor devices 111 and 112 connected in series via an intermediate node Nm1. The V-phase arm includes semiconductor devices 113 and 114 connected in series via an intermediate node Nm2. The W-phase arm includes semiconductor devices 115 and 116 connected in series via an intermediate node Nm3.
　各中間ノードＮｍ１～Ｎｍ３は、各相出力線Ｕｏｕｔ、Ｖｏｕｔ、Ｗｏｕｔに接続されている。各相出力線Ｕｏｕｔ、Ｖｏｕｔ、Ｗｏｕｔは、３相のモータ４００の各相コイルの一端に接続されている。各相コイルの他端は、中性点に共通接続される。なお、この例のモータ４００は３相であるが、本明細書で開示される技術は、相数を限定することなく様々な交流電動機に適用可能である。 The intermediate nodes Nm1 to Nm3 are connected to the phase output lines Uout, Vout, Wout. Each phase output line Uout, Vout, Wout is connected to one end of each phase coil of the three-phase motor 400. The other end of each phase coil is commonly connected to the neutral point. Note that the motor 400 in this example has three phases, but the technology disclosed in this specification can be applied to various AC motors without limiting the number of phases.
　上記したように、６つの半導体装置１１１～１１６はいずれも、ＬＩＧＢＴとＦＷＤで構成されており、共通した形態を備えている。以下、図２～５を参照して、インバータ回路１００を構成する６つの半導体装置１１１～１１６のうちの１つを具体的に説明する。図２は、半導体装置のレイアウトを示す平面図である。図３は、半導体装置に配設される各電極のレイアウトを図２に重ねた平面図である。図４は、図２のIV－IV線に対応した断面図であり、隣接部におけるＬＩＧＢＴの断面図を示す。図５は、図２のV－V線に対応した断面図であり、隣接部におけるＦＷＤの断面図を示す。 As described above, all of the six semiconductor devices 111 to 116 are composed of LIGBT and FWD and have a common form. Hereinafter, one of the six semiconductor devices 111 to 116 constituting the inverter circuit 100 will be specifically described with reference to FIGS. FIG. 2 is a plan view showing the layout of the semiconductor device. FIG. 3 is a plan view in which the layout of each electrode disposed in the semiconductor device is superimposed on FIG. FIG. 4 is a cross-sectional view corresponding to the line IV-IV in FIG. 2, and shows a cross-sectional view of the LIGBT in the adjacent portion. FIG. 5 is a cross-sectional view corresponding to the line VV in FIG. 2, and shows a cross-sectional view of the FWD in the adjacent portion.
　図２に示されるように、ＳＯＩ基板２０の半導体層２６には、半導体層２６を貫通する第１トレンチ絶縁分離部１２と第２トレンチ絶縁分離部１４が形成されている。第１トレンチ絶縁分離部１２は、ＳＯＩ基板２０を平面視したときに一巡している。第２トレンチ絶縁分離部１４は、第１トレンチ絶縁分離部１２から離れて設けられており、ＳＯＩ基板２０を平面視したときに第１トレンチ絶縁分離部１２の周囲を一巡している。第１トレンチ絶縁分離部１２と第２トレンチ絶縁分離部１４は、角部を除いて平行に伸びており、その間隔は一定である。 As shown in FIG. 2, the semiconductor layer 26 of the SOI substrate 20 is formed with a first trench isolation portion 12 and a second trench isolation portion 14 that penetrate the semiconductor layer 26. The first trench isolation / separation portion 12 makes a round when the SOI substrate 20 is viewed in plan. The second trench isolation part 14 is provided away from the first trench isolation part 12 and makes a round around the first trench isolation part 12 when the SOI substrate 20 is viewed in plan. The first trench isolation part 12 and the second trench isolation part 14 extend in parallel except for the corners, and the distance between them is constant.
　第１トレンチ絶縁分離部１２と第２トレンチ絶縁分離部１４で挟まれた素子領域１６，１８は、周辺の半導体層２６から分離されている。第１素子領域１６と第２素子領域１８は、ＳＯＩ基板２０を平面視したときに、隣接部１１において隣接している。具体的には、第１素子領域１６と第２素子領域１８は、隣接部１１において、第１トレンチ絶縁分離部１２と第２トレンチ絶縁分離部１４を結ぶ方向（ｘ軸方向）に直交する方向（ｙ軸方向）に沿って対向するように並んでいる。第１素子領域１６にＬＩＧＢＴが設けられており、第２素子領域１８にＦＷＤが設けられている。なお、この例は一例であり、第１素子領域１６と第２素子領域１８のレイアウトは、必要に応じて様々で形態をとることができる。例えば、第１素子領域１６と第２素子領域１８は、ｘ軸方向に沿って対向するように並んでいてもよく、その他の方向に沿って対向するように並んでいてもよい。また、複数の第１素子領域１６と複数の第２素子領域１８が設けられていてもよい。 The element regions 16 and 18 sandwiched between the first trench isolation portion 12 and the second trench isolation portion 14 are isolated from the peripheral semiconductor layer 26. The first element region 16 and the second element region 18 are adjacent to each other in the adjacent portion 11 when the SOI substrate 20 is viewed in plan. Specifically, the first element region 16 and the second element region 18 in the adjacent portion 11 are orthogonal to the direction (x-axis direction) connecting the first trench insulation isolation portion 12 and the second trench insulation isolation portion 14. They are arranged so as to oppose each other along (y-axis direction). A LIGBT is provided in the first element region 16, and an FWD is provided in the second element region 18. This example is merely an example, and the layout of the first element region 16 and the second element region 18 can take various forms as necessary. For example, the first element region 16 and the second element region 18 may be arranged so as to face each other along the x-axis direction, or may be arranged so as to face each other along other directions. A plurality of first element regions 16 and a plurality of second element regions 18 may be provided.
　図４に、隣接部１１近傍におけるＬＩＧＢＴの断面図を示す。図４に示されるように、ＳＯＩ基板２０は、半導体支持層２２と埋込み絶縁層２４と半導体層２６を備えている。半導体支持層２２は、ｎ型又はｐ型の不純物が高濃度に導入された単結晶のシリコンで形成されている。埋込み絶縁層２４は、酸化シリコンで形成されている。半導体層２６は、ｎ型の不純物が低濃度に導入された単結晶のシリコンで形成されている。 FIG. 4 shows a cross-sectional view of the LIGBT in the vicinity of the adjacent portion 11. As shown in FIG. 4, the SOI substrate 20 includes a semiconductor support layer 22, a buried insulating layer 24, and a semiconductor layer 26. The semiconductor support layer 22 is formed of single crystal silicon into which an n-type or p-type impurity is introduced at a high concentration. The buried insulating layer 24 is made of silicon oxide. The semiconductor layer 26 is formed of single crystal silicon into which n-type impurities are introduced at a low concentration.
　図４に示されるように、ＬＩＧＢＴは、第１トレンチ絶縁分離部１２と第２トレンチ絶縁分離部１４で挟まれた第１素子領域１６に形成されている。第１トレンチ絶縁分離部１２は、半導体層２６を貫通して埋込み絶縁層２４まで達しており、酸化シリコンの酸化膜１２ａとその酸化膜１２ａで被覆されたポリシリコンの芯部１２ｂとを備えている。第２トレンチ絶縁分離部１４も同様に、半導体層２６を貫通して埋込み絶縁層２４まで達しており、酸化シリコンの酸化膜１４ａとその酸化膜１４ａで被覆されたポリシリコンの芯部１４ｂとを備えている。 As shown in FIG. 4, the LIGBT is formed in the first element region 16 sandwiched between the first trench isolation part 12 and the second trench isolation part 14. The first trench isolation portion 12 extends through the semiconductor layer 26 to the buried insulating layer 24, and includes a silicon oxide film 12a and a polysilicon core 12b covered with the oxide film 12a. Yes. Similarly, the second trench isolation portion 14 penetrates the semiconductor layer 26 and reaches the buried insulating layer 24, and includes a silicon oxide film 14a and a polysilicon core portion 14b covered with the oxide film 14a. I have.
　図４に示されるように、ＬＩＧＢＴは、ｐ＋型のボディコンタクト領域３１と、ｎ＋型のエミッタ領域３２と、ｐ型のボディ領域３３と、ｎ－型のドリフト領域３４と、ｎ＋型の埋込み領域３５と、ｎ型のバッファ領域３６と、ｐ＋型のコレクタ領域３７を備えている。 As shown in FIG. 4, the LIGBT includes a p + type body contact region 31, an n + type emitter region 32, a p type body region 33, an n − type drift region 34, and an n + type. Embedded region 35, n-type buffer region 36, and p + -type collector region 37.
　ボディコンタクト領域３１、エミッタ領域３２及びボディ領域３３は、半導体層２６の表層部のうちの第２トレンチ絶縁分離部１４側に設けられている。特に、ボディコンタクト領域３１及びボディ領域３３は、第２トレンチ絶縁分離部１４の側面に接している。エミッタ領域３２は、ボディ領域３３によってドリフト領域３４から隔てられている。ドリフト領域３４は、ボディ領域３３とバッファ領域３６の間に設けられており、ＬＩＧＢＴがオフしたときに電位差を保持する領域である。埋込み領域３５は、半導体層２６の裏層部に設けられており、第１トレンチ絶縁分離部１２と第２トレンチ絶縁分離部１４の間に亘って設けられている。バッファ領域３６及びコレクタ領域３７は、半導体層２６の表層部のうちの第１トレンチ絶縁分離部１２側に設けられている。特に、バッファ領域３６及びコレクタ領域３７は、第１トレンチ絶縁分離部１２の側面に接している。コレクタ領域３７は、バッファ領域３６によってドリフト領域３４から隔てられている。なお、これらの断面構造は、第１素子領域１６の全体に亘って共通している。したがって、ボディコンタクト領域３１、エミッタ領域３２及びボディ領域３３は、ＳＯＩ基板２０を平面視したときに、第２トレンチ絶縁分離部１４の側面に沿って第１素子領域１６の全体に亘って設けられている。同様に、バッファ領域３６とコレクタ領域３７は、ＳＯＩ基板２０を平面視したときに、第１トレンチ絶縁分離部１２の側面に沿って第１素子領域１６の全体に亘って設けられている。 The body contact region 31, the emitter region 32, and the body region 33 are provided on the second trench isolation portion 14 side in the surface layer portion of the semiconductor layer 26. In particular, the body contact region 31 and the body region 33 are in contact with the side surface of the second trench isolation portion 14. Emitter region 32 is separated from drift region 34 by body region 33. The drift region 34 is provided between the body region 33 and the buffer region 36 and is a region that holds a potential difference when the LIGBT is turned off. The buried region 35 is provided in the back layer portion of the semiconductor layer 26, and is provided between the first trench insulation isolation portion 12 and the second trench insulation isolation portion 14. The buffer region 36 and the collector region 37 are provided on the first trench isolation portion 12 side in the surface layer portion of the semiconductor layer 26. In particular, the buffer region 36 and the collector region 37 are in contact with the side surface of the first trench isolation portion 12. The collector region 37 is separated from the drift region 34 by the buffer region 36. Note that these cross-sectional structures are common throughout the first element region 16. Accordingly, the body contact region 31, the emitter region 32, and the body region 33 are provided over the entire first element region 16 along the side surface of the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. ing. Similarly, the buffer region 36 and the collector region 37 are provided over the entire first element region 16 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
　図４に示されるように、ＬＩＧＢＴはさらに、層間絶縁膜４１と、コレクタ電極４２と、ＬＯＣＯＳ（Local Oxidation of Silicon）酸化膜４３と、ゲート電極４４と、プレーナゲート部４７と、エミッタ電極４８を備えている。 As shown in FIG. 4, the LIGBT further includes an interlayer insulating film 41, a collector electrode 42, a LOCOS (Local Oxidation of Silicon) oxide film 43, a gate electrode 44, a planar gate portion 47, and an emitter electrode 48. I have.
　層間絶縁膜４１は、ＳＯＩ基板２０の表面を被覆しており、酸化シリコンで形成されている。コレクタ電極４２は、第１トレンチ絶縁分離部１２側の層間絶縁膜４１の表面に配設されている。特に、コレクタ電極４２は、第１トレンチ絶縁分離部１２の上方にも配設されている。コレクタ電極４２は、ＳＯＩ基板２０を平面視したときに、少なくとも第１トレンチ絶縁分離部１２に沿って第１トレンチ絶縁分離部１２の上方に配設されている。さらに、コレクタ電極４２は、一部が層間絶縁膜４１を貫通して伸びているとともにコレクタ領域３７に接触部４２ａを介して接している。接触部４２ａは、ＳＯＩ基板２０を平面視したときに、第１トレンチ絶縁分離部１２に沿って第１素子領域１６の全体に亘って設けられている。また、コレクタ電極４２は、ＳＯＩ基板２０を平面視したときに、第１トレンチ絶縁分離部１２から第２トレンチ絶縁分離部１４の向き（図４の場合、左向き）において、バッファ領域３６を超えて配設されていないのが望ましい。 The interlayer insulating film 41 covers the surface of the SOI substrate 20 and is made of silicon oxide. The collector electrode 42 is disposed on the surface of the interlayer insulating film 41 on the first trench isolation portion 12 side. In particular, the collector electrode 42 is also disposed above the first trench isolation portion 12. The collector electrode 42 is disposed above the first trench isolation portion 12 along at least the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, the collector electrode 42 partially extends through the interlayer insulating film 41 and is in contact with the collector region 37 via the contact portion 42a. The contact portion 42 a is provided over the entire first element region 16 along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. The collector electrode 42 extends beyond the buffer region 36 in the direction from the first trench isolation part 12 to the second trench isolation part 14 (leftward in the case of FIG. 4) when the SOI substrate 20 is viewed in plan. It is desirable that it is not arranged.
　ＬＯＣＯＳ酸化膜４３は、ドリフト領域３４の表面に設けられており、酸化シリコンで形成されている。ゲート電極４４は、コレクタ電極４２とエミッタ電極４８の間の層間絶縁膜４１の表面に配設されている。ゲート電極４４は、一部が層間絶縁膜４１を貫通して伸びているとともにプレーナゲート部４７に接している。プレーナゲート部４７は、プレーナ電極４５とゲート絶縁膜４６を有しており、エミッタ領域３２とドリフト領域３４を隔てているボディ領域３３の表面に対向している。プレーナ電極４５は、ゲート絶縁膜４６の表面とＬＯＣＯＳ酸化膜４３の表面の一部を被覆しており、不純物が高濃度に導入されたポリシリコンで形成されている。ゲート絶縁膜４６は、酸化シリコンで形成されている。 The LOCOS oxide film 43 is provided on the surface of the drift region 34 and is made of silicon oxide. The gate electrode 44 is disposed on the surface of the interlayer insulating film 41 between the collector electrode 42 and the emitter electrode 48. A portion of the gate electrode 44 extends through the interlayer insulating film 41 and is in contact with the planar gate portion 47. The planar gate portion 47 has a planar electrode 45 and a gate insulating film 46, and faces the surface of the body region 33 that separates the emitter region 32 and the drift region 34. The planar electrode 45 covers the surface of the gate insulating film 46 and a part of the surface of the LOCOS oxide film 43, and is formed of polysilicon into which impurities are introduced at a high concentration. The gate insulating film 46 is made of silicon oxide.
　エミッタ電極４８は、第２トレンチ絶縁分離部１４側の層間絶縁膜４１の表面に配設されている。特に、エミッタ電極４８は、第２トレンチ絶縁分離部１４の上方にも配設されている。エミッタ電極４８は、ＳＯＩ基板２０を平面視したときに、少なくとも第２トレンチ絶縁分離部１４に沿って第２トレンチ絶縁分離部１４の上方に配設されている。さらに、エミッタ電極４８は、一部が層間絶縁膜４１を貫通して伸びているとともにボディコンタクト領域３１及びエミッタ領域３２に接触部４８ａを介して接している。接触部４８ａは、ＳＯＩ基板２０を平面視したときに、第２トレンチ絶縁分離部１４に沿って第１素子領域１６の全体に亘って設けられている。上述したように、隣接部１１において、コレクタ電極４２とエミッタ電極４８はｘ軸方向に間隔を置いて配置されており、ゲート電極４４はその間隔内に配置されている。 The emitter electrode 48 is disposed on the surface of the interlayer insulating film 41 on the second trench isolation portion 14 side. In particular, the emitter electrode 48 is also disposed above the second trench isolation portion 14. The emitter electrode 48 is disposed above the second trench isolation part 14 along at least the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Further, the emitter electrode 48 partially extends through the interlayer insulating film 41 and is in contact with the body contact region 31 and the emitter region 32 via the contact portion 48a. The contact portion 48 a is provided over the entire first element region 16 along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. As described above, in the adjacent portion 11, the collector electrode 42 and the emitter electrode 48 are arranged with an interval in the x-axis direction, and the gate electrode 44 is arranged within the interval.
　図５に示されるように、ＦＷＤでは、いくつかの構成がＬＩＧＢＴの構成と共通している。以下では、ＬＩＧＢＴと相違する構成のみを説明し、共通する構成には共通の符号を付し、その説明を省略する。ＦＷＤは、ｐ＋型のアノードコンタクト領域１３１と、ｐ型のアノード領域１３３と、ｎ型のカソード領域１３６と、ｎ＋型のカソードコンタクト領域１３７と、カソード電極１４２と、アノード電極１４８を備えている点でＬＩＧＢＴから相違する。 As shown in FIG. 5, in the FWD, some configurations are common to the LIGBT configurations. In the following, only the configuration different from the LIGBT will be described, common configurations will be denoted by common reference numerals, and description thereof will be omitted. The FWD includes a p + type anode contact region 131, a p type anode region 133, an n type cathode region 136, an n + type cathode contact region 137, a cathode electrode 142, and an anode electrode 148. It is different from LIGBT in that it is.
　アノードコンタクト領域１３１及びアノード領域１３３は、半導体層２６の表層部のうちの第２トレンチ絶縁分離部１４側に設けられている。特に、アノードコンタクト領域１３１及びアノード領域１３３は、第２トレンチ絶縁分離部１４の側面に接している。また、アノード領域１３３は、ＬＩＧＢＴのボディ領域３３と同一の製造工程で作製されており、ボディ領域３３と同一のドーパント、濃度及び拡散深さを有している。カソード領域１３６及びカソードコンタクト領域１３７は、半導体層２６の表層部のうちの第１トレンチ絶縁分離部１２側に設けられている。特に、カソード領域１３６及びカソードコンタクト領域１３７は、第１トレンチ絶縁分離部１２の側面に接している。また、カソード領域１３６は、ＬＩＧＢＴのバッファ領域３６と同一の製造工程で作製されており、バッファ領域３６と同一のドーパント、濃度及び拡散深さを有している。なお、これらの断面構造は、第２素子領域１８の全体に亘って共通している。したがって、アノードコンタクト領域１３１及びアノード領域１３３は、ＳＯＩ基板２０を平面視したときに、第２トレンチ絶縁分離部１４の側面に沿って第２素子領域１８の全体に亘って設けられている。同様に、カソード領域１３６及びカソードコンタクト領域１３７は、ＳＯＩ基板２０を平面視したときに、第１トレンチ絶縁分離部１２の側面に沿って第２素子領域１８の全体に亘って設けられている。 The anode contact region 131 and the anode region 133 are provided on the second trench isolation portion 14 side in the surface layer portion of the semiconductor layer 26. In particular, the anode contact region 131 and the anode region 133 are in contact with the side surface of the second trench isolation portion 14. The anode region 133 is manufactured by the same manufacturing process as the body region 33 of the LIGBT, and has the same dopant, concentration, and diffusion depth as the body region 33. The cathode region 136 and the cathode contact region 137 are provided on the first trench isolation portion 12 side in the surface layer portion of the semiconductor layer 26. In particular, the cathode region 136 and the cathode contact region 137 are in contact with the side surfaces of the first trench isolation portion 12. The cathode region 136 is manufactured in the same manufacturing process as the buffer region 36 of the LIGBT, and has the same dopant, concentration, and diffusion depth as the buffer region 36. These cross-sectional structures are common throughout the second element region 18. Therefore, the anode contact region 131 and the anode region 133 are provided over the entire second element region 18 along the side surface of the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Similarly, the cathode region 136 and the cathode contact region 137 are provided over the entire second element region 18 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
　また、ＬＩＧＢＴのボディ領域３３とＦＷＤのアノード領域１３３は、図２に示される隣接部１１において接触している。このため、これらのｐ型領域３３，１３３は、ＳＯＩ基板２０を平面視したときに、第２トレンチ絶縁分離部１４の側面に沿って素子領域１６，１８内を一巡している。さらに、ＬＩＧＢＴのバッファ領域３６とＦＷＤのカソード領域１３６も、図２に示される隣接部１１において接触している。このため、これらのｎ型領域３６，１３６も、ＳＯＩ基板２０を平面視したときに、第１トレンチ絶縁分離部１２の側面に沿って素子領域１６，１８内を一巡している。 Further, the body region 33 of the LIGBT and the anode region 133 of the FWD are in contact with each other at the adjacent portion 11 shown in FIG. For this reason, these p- type regions 33 and 133 circulate in the element regions 16 and 18 along the side surfaces of the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. Further, the buffer region 36 of the LIGBT and the cathode region 136 of the FWD are also in contact with each other at the adjacent portion 11 shown in FIG. For this reason, these n- type regions 36 and 136 also circulate in the element regions 16 and 18 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
　カソード電極１４２は、第１トレンチ絶縁分離部１２側の層間絶縁膜４１の表面に配設されている。特に、カソード電極１４２は、第１トレンチ絶縁分離部１２の上方にも配設されている。カソード電極１４２は、ＳＯＩ基板２０を平面視したときに、少なくとも第１トレンチ絶縁分離部１２に沿って第１トレンチ絶縁分離部１２の上方に配設されている。さらに、カソード電極１４２は、一部が層間絶縁膜４１を貫通して伸びているとともにカソードコンタクト領域１３７に接触部１３７ａを介して接している。接触部１３７ａは、ＳＯＩ基板２０を平面視したときに、第１トレンチ絶縁分離部１２に沿って第２素子領域１８の全体に亘って設けられている。また、カソード電極１４２は、平面視したときに、第１トレンチ絶縁分離部１２から第２トレンチ絶縁分離部１４の向き（図５の場合、左向き）において、カソード領域１３６を超えて配設されていないのが望ましい。 The cathode electrode 142 is disposed on the surface of the interlayer insulating film 41 on the first trench isolation portion 12 side. In particular, the cathode electrode 142 is also disposed above the first trench isolation portion 12. The cathode electrode 142 is disposed above the first trench isolation portion 12 along at least the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, a part of the cathode electrode 142 extends through the interlayer insulating film 41 and is in contact with the cathode contact region 137 through the contact portion 137a. The contact portion 137 a is provided over the entire second element region 18 along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, the cathode electrode 142 is disposed beyond the cathode region 136 in the direction from the first trench insulation isolation portion 12 to the second trench insulation isolation portion 14 (leftward in the case of FIG. 5) when viewed in plan. Desirably not.
　アノード電極１４８は、第２トレンチ絶縁分離部１４側の層間絶縁膜４１の表面に配設されている。特に、アノード電極１４８は、第２トレンチ絶縁分離部１４の上方にも配設されている。アノード電極１４８は、ＳＯＩ基板２０を平面視したときに、少なくとも第２トレンチ絶縁分離部１４に沿って第２トレンチ絶縁分離部１４の上方に配設されている。さらに、アノード電極１４８は、一部が層間絶縁膜４１を貫通して伸びているとともにアノードコンタクト領域１３１に接触部１４８ａを介して接している。接触部１４８ａは、ＳＯＩ基板２０を平面視したときに、第２トレンチ絶縁分離部１４に沿って第２素子領域１８の全体に亘って設けられている。また、アノード電極１４８は、一部が層間絶縁膜４１を貫通して伸びているとともにプレーナ電極４５にも接しているのが望ましい。さらに、アノード電極１４８は、平面視したときに、第２トレンチ絶縁分離部１４から第１トレンチ絶縁分離部１２の向き（図５の場合、右向き）において、プレーナ電極４５を越えて配設されていないのが望ましい。上述したように、隣接部１１において、カソード電極１４２とアノード電極１４８はｘ軸方向に間隔を置いて配置されている。 The anode electrode 148 is disposed on the surface of the interlayer insulating film 41 on the second trench isolation portion 14 side. In particular, the anode electrode 148 is also disposed above the second trench isolation portion 14. The anode electrode 148 is disposed above the second trench isolation part 14 along at least the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Further, a part of the anode electrode 148 extends through the interlayer insulating film 41 and is in contact with the anode contact region 131 through the contact portion 148a. The contact portion 148a is provided over the entire second element region 18 along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. The anode electrode 148 preferably extends partially through the interlayer insulating film 41 and is in contact with the planar electrode 45. Further, the anode electrode 148 is disposed beyond the planar electrode 45 in the direction from the second trench insulation isolation portion 14 to the first trench insulation isolation portion 12 (rightward in the case of FIG. 5) when viewed in plan. Desirably not. As described above, in the adjacent portion 11, the cathode electrode 142 and the anode electrode 148 are arranged at an interval in the x-axis direction.
　また、ＬＩＧＢＴのエミッタ電極４８の接触部４８ａとＦＷＤのアノード電極１４８の接触部１４８ａは、図２に示される隣接部１１において隣接している。このため、これらの接触部４８ａ，１４８ａは、ＳＯＩ基板２０を平面視したときに、第２トレンチ絶縁分離部１４に沿って一巡している。さらに、ＬＩＧＢＴのコレクタ電極４２の接触部４２ａとＦＷＤのカソード電極１４２の接触部１４２ａも、図２に示される隣接部１１において隣接している。このため、これらの接触部４２ａ，１４２ａは、ＳＯＩ基板２０を平面視したときに、第１トレンチ絶縁分離部１２に沿って一巡している。 Further, the contact portion 48a of the emitter electrode 48 of the LIGBT and the contact portion 148a of the anode electrode 148 of the FWD are adjacent to each other in the adjacent portion 11 shown in FIG. For this reason, these contact portions 48 a and 148 a make a round along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. Further, the contact portion 42a of the collector electrode 42 of the LIGBT and the contact portion 142a of the cathode electrode 142 of the FWD are also adjacent in the adjacent portion 11 shown in FIG. For this reason, these contact portions 42 a and 142 a make a round along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.
　ＬＩＧＢＴのコレクタ電極４２、ゲート電極４４、エミッタ電極４８、及びＦＷＤのカソード電極１４２、アノード電極１４８は、蒸着技術を利用して、同一の製造工程で作製されている。これら電極の材料には、アルミニウムが用いられている。図３に示されるように、ＬＩＧＢＴのコレクタ電極４２とＦＷＤのカソード電極１４２は、平面視したときに、第１トレンチ絶縁分離部１２の内側の範囲に設けられている。すなわち、ＬＩＧＢＴのコレクタ電極４２とＦＷＤのカソード電極１４２は、１つの共通電極である。この１つの共通電極上にコレクタ・カソード用ボンディングパッド１９が設けられている。また、ＬＩＧＢＴのエミッタ電極４８とＦＷＤのアノード電極１４８は、第２トレンチ絶縁分離部１４の外側の範囲に設けられている。すなわち、ＬＩＧＢＴのエミッタ電極４８とＦＷＤのアノード電極１４８も、１つの共通電極である。この１つの共通電極上にエミッタ・アノード用ボンディングパッド１５が設けられている。 The collector electrode 42, the gate electrode 44, and the emitter electrode 48 of the LIGBT, and the cathode electrode 142 and the anode electrode 148 of the FWD are manufactured in the same manufacturing process using vapor deposition technology. Aluminum is used as the material for these electrodes. As shown in FIG. 3, the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are provided in a range inside the first trench isolation portion 12 when viewed in plan. That is, the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are one common electrode. A collector / cathode bonding pad 19 is provided on the one common electrode. Further, the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are provided in a range outside the second trench isolation portion 14. That is, the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are also one common electrode. An emitter / anode bonding pad 15 is provided on the one common electrode.
　本実施例の半導体装置では、ＬＩＧＢＴのコレクタ電極４２とＦＷＤのカソード電極１４２は１つの共通電極として構成されている。このため、コレクタ電極４２とカソード電極１４２を接続する接続配線が不要である。さらに、ＬＩＧＢＴのエミッタ電極４８とＦＷＤのアノード電極１４８も１つの共通電極として構成されている。このため、エミッタ電極４８とアノード電極１４８を接続する接続配線も不要である。これにより、これら接続配線がＬＩＧＢＴ及びＦＷＤのドリフト領域３４の上方を伸びることがない。したがって、本実施例の半導体装置では、図１０及び図１１で示される従来構造のように、ドリフト領域の電位分布が不均一化するという事態が発生しない。 In the semiconductor device of this embodiment, the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are configured as one common electrode. For this reason, the connection wiring which connects the collector electrode 42 and the cathode electrode 142 is unnecessary. Further, the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are also configured as one common electrode. For this reason, the connection wiring which connects the emitter electrode 48 and the anode electrode 148 is also unnecessary. Thereby, these connection wirings do not extend above the drift region 34 of the LIGBT and FWD. Therefore, in the semiconductor device of the present embodiment, unlike the conventional structure shown in FIGS. 10 and 11, a situation where the potential distribution in the drift region becomes non-uniform does not occur.
　また、図３に示されるように、本実施例の半導体装置では、ＬＩＧＢＴのコレクタ電極４２及びＦＷＤのカソード電極１４２の共通電極が内側に配置されており、ＬＩＧＢＴのエミッタ電極４８及びＦＷＤのアノード電極１４８の共通電極がそれを取囲むように周囲に配置されている。図１に示されるように、ＬＩＧＢＴのコレクタ電極４２及びＦＷＤのカソード電極１４２は高圧直流電源３００の高圧側に接続されており、ＬＩＧＢＴのエミッタ電極４８及びＦＷＤのアノード電極１４８が高圧直流電源３００の低圧側に接続されている。すなわち、本実施例の半導体装置では、高圧側の共通電極を取囲むように低圧側の共通電極が設けられている。上述したように、本実施例のインバータ回路は、１つのＳＯＩ基板２０に図１に示す半導体装置１１１～１１６が搭載されている。したがって、低圧側の共通電極を周囲に配置することで、複数の半導体装置間の電圧差を小さく抑えることができる。 Further, as shown in FIG. 3, in the semiconductor device of this embodiment, the common electrode of the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD is disposed inside, the emitter electrode 48 of the LIGBT, and the anode electrode of the FWD. 148 common electrodes are arranged around it so as to surround them. As shown in FIG. 1, the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are connected to the high voltage side of the high voltage DC power supply 300, and the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are connected to the high voltage DC power supply 300. Connected to the low pressure side. That is, in the semiconductor device of this embodiment, the low-voltage common electrode is provided so as to surround the high-voltage common electrode. As described above, in the inverter circuit of this embodiment, the semiconductor devices 111 to 116 shown in FIG. 1 are mounted on one SOI substrate 20. Therefore, the voltage difference between the plurality of semiconductor devices can be reduced by arranging the common electrode on the low voltage side around.
　さらに、図６に、第１素子領域１６と第２素子領域１８が隣接する隣接部１１の拡大平面図を示す。図６に示されるように、ＬＩＧＢＴとＦＷＤが隣接して設けられていると、ＬＩＧＢＴのエミッタ領域３２、ボディ領域３３、ドリフト領域３４、及びＦＷＤのカソード領域１３６で構成される寄生ＭＯＳが存在する。しかしながら、本実施例の半導体装置では、ＬＩＧＢＴとＦＷＤの全体の面積に比べて、ＬＩＧＢＴとＦＷＤの接する隣接部１１の面積が小さい。このため、ＬＩＧＢＴがオンしたときに、図６の破線矢印で示されるような寄生ＭＯＳが動作する現象が特に問題となることがない。この結果、本実施例の半導体装置では、ＬＩＧＢＴがオンしたときに、ＩＧＢＴ動作が支配的となり、低いオン電圧が得られる。 Further, FIG. 6 shows an enlarged plan view of the adjacent portion 11 where the first element region 16 and the second element region 18 are adjacent to each other. As shown in FIG. 6, when the LIGBT and the FWD are provided adjacent to each other, there is a parasitic MOS composed of the emitter region 32 of the LIGBT, the body region 33, the drift region 34, and the cathode region 136 of the FWD. . However, in the semiconductor device of this example, the area of the adjacent portion 11 where the LIGBT and the FWD are in contact is smaller than the entire area of the LIGBT and the FWD. Therefore, when the LIGBT is turned on, the phenomenon that the parasitic MOS as shown by the broken line arrow in FIG. As a result, in the semiconductor device of this embodiment, when the LIGBT is turned on, the IGBT operation becomes dominant and a low on-voltage can be obtained.
　なお、図７及び図８に示されるように、本実施例の半導体装置はさらに、第３トレンチ絶縁分離部１３を備えているのが望ましい。第３トレンチ絶縁分離部１３は、第１端部１３Ａが第１トレンチ絶縁分離部１２に接しており、第２端部１３Ｂが第２トレンチ絶縁分離部１４に接している。第１素子領域１６と第２素子領域１８は、第３トレンチ絶縁分離部１３によって分離されている。第３トレンチ絶縁分離部１３も、酸化シリコンの酸化膜１３ａとその酸化膜１３ａで被覆されたポリシリコンの芯部１３ｂとを備えている。第３トレンチ絶縁分離部１３が設けられていると、ＬＩＧＢＴからＦＷＤに電子が流入することが防止される。この結果、ＬＩＧＢＴがオンしたときに、寄生ＭＯＳが動作する現象を完全に防止することができる。 As shown in FIGS. 7 and 8, it is desirable that the semiconductor device of this embodiment further includes a third trench isolation 13. In the third trench isolation 13, the first end 13 </ b> A is in contact with the first trench isolation 12 and the second end 13 </ b> B is in contact with the second trench isolation 14. The first element region 16 and the second element region 18 are separated by the third trench isolation portion 13. The third trench isolation part 13 also includes a silicon oxide film 13a and a polysilicon core part 13b covered with the oxide film 13a. When the third trench isolation 13 is provided, electrons are prevented from flowing from the LIGBT to the FWD. As a result, it is possible to completely prevent the phenomenon in which the parasitic MOS operates when the LIGBT is turned on.
　図９は、第２実施例の半導体装置のレイアウトを示す平面図である。第１実施例の半導体装置と共通する構成要素には共通の符号を付し、その説明を省略する。第２実施例の半導体装置では、第１トレンチ絶縁分離部１２と第２トレンチ絶縁分離部１４で挟まれた素子領域１６，１８の一部が、ＳＯＩ基板２０を平面視したときに、ｙ軸方向に沿って往復していることを特徴としている。この例では、素子領域１６，１８の一部が、ｙ軸方向に沿って４往復している。換言すると、第１トレンチ絶縁分離部１２で囲まれた半導体層２６の一部５２が、ＳＯＩ基板２０を平面視したときに、櫛歯状の形態を有している、ということもできる。このような形態を採用することにより、半導体層２６に占める素子領域１６，１８の面積を大きくすることができ、実装面積を小さく抑えることができる。 FIG. 9 is a plan view showing the layout of the semiconductor device of the second embodiment. Constituent elements common to the semiconductor device of the first embodiment are denoted by common reference numerals and description thereof is omitted. In the semiconductor device of the second embodiment, when part of the element regions 16 and 18 sandwiched between the first trench isolation portion 12 and the second trench isolation portion 14 is viewed in plan view of the SOI substrate 20, the y axis It is characterized by reciprocating along the direction. In this example, part of the element regions 16 and 18 reciprocate four times along the y-axis direction. In other words, it can also be said that a part 52 of the semiconductor layer 26 surrounded by the first trench isolation portion 12 has a comb-like shape when the SOI substrate 20 is viewed in plan view. By adopting such a form, the area of the element regions 16 and 18 occupying the semiconductor layer 26 can be increased, and the mounting area can be reduced.
　また、図９に示されるように、本実施例の半導体装置では、ＦＷＤが内側に配置されており、ＬＩＧＢＴがそれを取囲むように配置されている。一般的に、ＬＩＧＢＴは、スイッチング損失が大きいことから、動作中の発熱量がＦＷＤよりも大きい。したがって、発熱量の小さいＦＷＤを中央部に配置し、発熱量の多いＬＩＧＢＴを周囲に配置すると、半導体装置の全体の温度分布が均一化され、中央部が局所的に高温になる事態を抑制することができる。これにより、高温による半導体装置の誤作動及び破損が抑制される。 Further, as shown in FIG. 9, in the semiconductor device of this embodiment, the FWD is arranged on the inner side and the LIGBT is arranged so as to surround it. Generally, since LIGBT has a large switching loss, the amount of heat generated during operation is larger than that of FWD. Therefore, when the FWD having a small heat generation amount is arranged in the central portion and the LIGBT having a large heat generation amount is arranged around, the entire temperature distribution of the semiconductor device is made uniform, and the situation where the central portion becomes locally high is suppressed. be able to. Thereby, malfunction and damage of the semiconductor device due to high temperature are suppressed.
　上記の実施例では、ＳＯＩ基板の半導体材料にシリコンが用いられている。この例に代えて、他の半導体材料を用いてもよい。例えば、窒化ガリウム、炭化珪素、ガリウム砒素等の化合物半導体を用いてもよい。 In the above embodiment, silicon is used as the semiconductor material of the SOI substrate. Instead of this example, other semiconductor materials may be used. For example, a compound semiconductor such as gallium nitride, silicon carbide, or gallium arsenide may be used.
　以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
　本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時の請求項に記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数の目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

Claims (6)

  1. 　第１素子領域と第２素子領域を有する半導体層と、
    　前記第１素子領域に配置されており、その間を電流が流れるように構成されている第１主電極と第２主電極を有する第１種類の第１半導体素子と、
    　前記第２素子領域に配置されており、その間を電流が流れるように構成されている第３主電極と第４主電極を有する第２種類の第２半導体素子と、を備えており、
    　前記第１素子領域と前記第２素子領域は、前記半導体層を平面視したときに、隣接部において第１方向に沿って並んでおり、
    　前記第１半導体素子の前記第１主電極と前記第２主電極は、前記半導体層を平面視したときに、前記隣接部において、前記第１方向に対して直交する第２方向に間隔を置いて配置されており、
    　前記第２半導体素子の前記第３主電極と前記第４主電極は、前記半導体層を平面視したときに、前記隣接部において前記第２方向に間隔を置いて配置されており、
    　前記第１半導体素子の前記第１主電極と前記第２半導体素子の前記第３主電極が接しており、
    　前記第１半導体素子の前記第２主電極と前記第２半導体素子の前記第４主電極が接している半導体装置。     A semiconductor layer having a first element region and a second element region;
    A first type of first semiconductor element having a first main electrode and a second main electrode arranged in the first element region and configured to allow current to flow there between;
    A second main semiconductor element having a third main electrode and a fourth main electrode arranged in the second element region and configured to allow current to flow there between,
    The first element region and the second element region are arranged along the first direction in adjacent portions when the semiconductor layer is viewed in plan view,
    The first main electrode and the second main electrode of the first semiconductor element are spaced from each other in a second direction orthogonal to the first direction at the adjacent portion when the semiconductor layer is viewed in plan. Arranged,
    The third main electrode and the fourth main electrode of the second semiconductor element are arranged at an interval in the second direction at the adjacent portion when the semiconductor layer is viewed in plan view,
    The first main electrode of the first semiconductor element is in contact with the third main electrode of the second semiconductor element;
    A semiconductor device in which the second main electrode of the first semiconductor element is in contact with the fourth main electrode of the second semiconductor element.
  2. 　前記半導体層を貫通する第１トレンチ絶縁分離部と、
    　その第１トレンチ絶縁分離部から離れているとともに、前記半導体層を貫通する第２トレンチ絶縁分離部と、をさらに備えており、
    　前記第１素子領域及び前記第２素子領域は、前記第１トレンチ絶縁分離部と前記第２トレンチ絶縁分離部で挟まれた素子領域に配置されており、
    　前記第１半導体素子の前記第１主電極が前記第１トレンチ絶縁分離部側に配置されており、前記第１半導体素子の前記第２主電極が前記第２トレンチ絶縁分離部側に配置されており、
    　前記第２半導体素子の前記第３主電極が前記第１トレンチ絶縁分離部側に配置されており、前記第２半導体素子の前記第４主電極が前記第２トレンチ絶縁分離部側に配置されている請求項１に記載の半導体装置。     A first trench isolation portion penetrating the semiconductor layer;
    A second trench isolation portion that is separated from the first trench isolation portion and penetrates the semiconductor layer, and
    The first element region and the second element region are disposed in an element region sandwiched between the first trench isolation portion and the second trench isolation portion,
    The first main electrode of the first semiconductor element is disposed on the first trench isolation portion, and the second main electrode of the first semiconductor element is disposed on the second trench isolation portion side. And
    The third main electrode of the second semiconductor element is disposed on the first trench insulation isolation part side, and the fourth main electrode of the second semiconductor element is disposed on the second trench insulation isolation part side. The semiconductor device according to claim 1.
  3. 　前記第１トレンチ絶縁分離部は、前記半導体層を平面視したときに一巡しており、
    　前記第２トレンチ絶縁分離部は、前記半導体層を平面視したときに前記第１トレンチ絶縁分離部の周囲を一巡している請求項２に記載の半導体装置。     The first trench insulation isolation part is circled when the semiconductor layer is viewed in plan,
    3. The semiconductor device according to claim 2, wherein the second trench isolation part makes a round around the first trench isolation part when the semiconductor layer is viewed in plan.
  4. 　前記第１トレンチ絶縁分離部と前記第２トレンチ絶縁分離部で挟まれた前記素子領域が、前記半導体層を平面視したときに、少なくとも一方向に沿って２往復する請求項２又は３に記載の半導体装置。 The element region sandwiched between the first trench isolation portion and the second trench isolation portion reciprocates twice along at least one direction when the semiconductor layer is viewed in plan. Semiconductor device.
  5. 　第１端部と第２端部を有するとともに、前記半導体層を貫通する第３トレンチ絶縁分離部をさらに備えており、
    　前記第３トレンチ絶縁分離部の前記第１端部が、前記第１トレンチ絶縁分離部に接しており、前記第３トレンチ絶縁分離部の前記第２端部が、前記第２トレンチ絶縁分離部に接しており、
    　前記第３トレンチ絶縁分離部は、前記第１素子領域と前記第２素子領域を隔てている請求項２～４のいずれか一項に記載の半導体装置。     A third trench insulation isolation portion having a first end portion and a second end portion and penetrating the semiconductor layer;
    The first end of the third trench isolation is in contact with the first trench isolation and the second end of the third trench isolation is at the second trench isolation. Touching,
    5. The semiconductor device according to claim 2, wherein the third trench isolation portion separates the first element region and the second element region.
  6. 　前記第１半導体素子が横型のＩＧＢＴであり、
    　前記第２半導体素子が横型の還流用ダイオードである請求項１～５のいずれか一項に記載の半導体装置。     The first semiconductor element is a lateral IGBT;
    The semiconductor device according to any one of claims 1 to 5, wherein the second semiconductor element is a horizontal reflux diode.
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