JP2010103571A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To assure extended condition where a protection capability of an insulated gate semiconductor device with built-in protection circuit works, improved heating shutoff, prevented malfunction, and improved usability. <P>SOLUTION: The insulated gate semiconductor device includes a power insulated gate semiconductor element (M9), protection circuit MOSFETs (M1-M7) to control the power insulated gate semiconductor element, a constant voltage circuit utilizing forward voltages of constant voltage circuit diodes (D2a-D2f), and voltage-limiting diodes (D1 and D0a-D0d) to control an upper limit of the supply voltage for the constant voltage circuit, wherein the power to the voltage-limiting diodes is supplied from an external gate terminal on the power insulated gate semiconductor element. The present invention has an effect of assuring improved reliability and usability for the insulated gate semiconductor device with built-in protection circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an insulated gate semiconductor device such as a power MOSFET or an IGBT (Insulated gate bipolar transistor), and more particularly, to an insulated gate for power with improved reliability of an insulated gate semiconductor device having a protection function on a chip. The present invention relates to a type semiconductor device.

  In an insulated gate field effect transistor called a power MOSFET that handles high power, an example in which an overheat cutoff circuit is built on the same chip is disclosed in Japanese Patent Application Laid-Open No. 63-229758 to improve the reliability. ing. In this conventional example, a resistor and a Zener diode are connected in series between an external gate terminal and an external source terminal, a constant voltage is generated at both ends of the Zener diode, and a resistor is connected to the external source terminal side at both ends. A diode is connected to the gate terminal side, and temperature detection is performed by voltage fluctuation of the resistor and the diode. When the element is overheated, a protection circuit MOSFET having a gate and a source connected to both ends of the resistor is turned on to shut off the power MOSFET of the main body. In this conventional overheat cutoff circuit, the gate-source voltage fluctuation of the protection circuit n-channel MOSFET with respect to the external gate voltage fluctuation is large, and therefore the gate voltage fluctuation is likely to be related to the overheat cutoff temperature fluctuation.

JP-A 63-229758

  In the above prior art, only the Zener diode is used in the constant voltage circuit in order to reduce the fluctuation of the cutoff temperature with respect to the fluctuation of the gate voltage. However, as a result of studies by the present inventors, the following has become clear.

  (Problem 1) In the case of a Zener diode, a soft breakdown occurs when the breakdown voltage is about 7 V or less. For this reason, when the external gate voltage is used at around 5 V, the cutoff temperature is likely to be subject to fluctuations in the external gate voltage. Therefore, the voltage range allowed for the external gate terminal is narrowed to about 4V to 7V or less in consideration of device variations.

  (Problem 2) When the gate voltage becomes negative, a leakage current due to the operation of the parasitic bipolar transistor flows from the external drain terminal to the external gate terminal, and therefore cannot be used in the source follower circuit.

  (Problem 3) When the drain voltage becomes negative, a current flows from the drain of the MOSFET for the protection circuit to the external source terminal by the operation of the parasitic bipolar transistor.

  (Problem 4) When a drain current flows suddenly as in the case of a load short-circuit accident, the temperature of the source pad portion becomes the highest, so the position of the temperature detection element needs to be determined by the positional relationship with the source pad. .

  The present invention has been made based on the above examination results, and an object of the present invention is to provide an insulated gate semiconductor device having a protection circuit function that is highly reliable and easy to use.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

In order to achieve the above object, an insulated gate semiconductor device according to an embodiment of the present invention includes:
(Means 1) Power insulated gate semiconductor element (M9);
MOSFET for protection circuit (M1 to M7) for controlling the gate current of the insulated gate semiconductor element for power,
A constant voltage circuit using a forward voltage of the first diodes (D2a to D2f);
Voltage limiting means (D1 and D0a to D0d) for limiting the upper limit of the power supply voltage of the constant voltage circuit;
The power of the constant voltage limiting means is supplied from an external gate terminal of the insulated gate semiconductor element for power (FIG. 1).

(Means 2) Power insulated gate semiconductor element (M9);
MOSFETs (M1 to M7) for protection circuits that control the insulated gate semiconductor elements for power,
A third diode (D5 to D7) connected in a reverse direction to the drain-body diode of the protection circuit MOSFET;
A fourth diode (D0a to D0d) connected between an external gate terminal and an external source terminal (external emitter terminal) of the power semiconductor element;
A current flows through the fourth diode so that the third diode does not breakdown even if the external gate terminal voltage changes, and the voltage of the external gate terminal and the external source terminal is clamped (see FIG. 1).

  (Means 3) A means for reducing the gate-source voltage of the first protection circuit MOSFET (M1) when the external drain voltage becomes negative is provided (FIG. 1). .

(Means 4) Insulated gate semiconductor element for power,
A temperature detection circuit;
In an insulated gate semiconductor device comprising a gate cut-off circuit that limits a current of the insulated gate semiconductor element for power when the temperature exceeds a specified temperature,
The temperature detection element used for the temperature detection circuit is formed in a region (a region included in P1 to P7) between the protection circuit region other than the temperature detection device and the external source terminal pad of the power insulated gate semiconductor device. This is a characteristic (FIG. 2). More specifically, the temperature detecting element is arranged within 300 μm from the external source terminal pad of the power insulated gate semiconductor element (FIG. 2).

In an exemplary embodiment of the invention,
(Operation 1) When a forward voltage of the first diodes (D2a to D2f) generates a constant voltage of about 3V and the external gate voltage becomes about 10V or more, a reverse connection diode or the like (D1 and D0a to D0d) can suppress the gate voltage dependence of the constant voltage circuit (FIG. 1).

(Operation 2) When the breakdown voltage and the forward voltage drop of D5 to D7 and D0a to D0 satisfy the following formula, it is possible to prevent the drain-body diode of the MOSFET for protection circuit (M1 to M7) from being forward-biased. The current can be prevented from flowing from the drain to the gate of the power MOSFET by the operation of the parasitic bipolar transistor.
BV (D5), BV (D6), BV (D7)
> Vf (D0a) + BV (D0b) + Vf (D0c) + Vf (D0d) (FIG. 1)
(Operation 3) When the drain voltage of the power MOSFET becomes negative with the cutoff circuit activated, the parasitic bipolar transistor operates, and in the worst case, the latch information is lost. After that, even if the drain voltage of the power MOSFET becomes positive, the cutoff circuit must be operated if the chip is not cooled. However, if the drain voltage of the power MOSFET becomes negative due to the addition of M5, Since the drain voltage goes to zero volts, M1 is easily turned off. For this reason, the interruption circuit is easy to work (FIG. 1).

  (Operation 4) In the case of a normal power MOSFET, there is only one metal electrode layer on the semiconductor surface. It is necessary to form a circuit wiring such as a source electrode layer of the power MOSFET and a temperature detecting element with this one metal electrode layer. By forming the temperature detection element in a region between the protection circuit area other than the temperature detection element and the external source terminal pad of the power insulated gate semiconductor element, the most in the semiconductor chip in the case of a load short-circuit accident The temperature detection element can be brought close to the source pad in the vicinity of the source pad where the temperature is likely to rise, and at the same time, the source electrode layer of the power MOSFET is hardly cut off, so that an increase in resistance of the source electrode layer can be prevented.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  It is possible to provide a power MOSFET or IGBT with a built-in protection circuit that is highly reliable and easy to use.

1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. 1 is a plan structural view of a semiconductor device according to a first embodiment of the present invention. It is a plane structure figure of the temperature detection element part of the semiconductor device of the 1st Embodiment of this invention. FIG. 4 is a cross-sectional structure diagram of a c-c ′ portion in FIG. 3. FIG. 3 is a cross-sectional structure diagram of the a-a ′ portion of FIG. 2. FIG. 3 is a cross-sectional structure diagram of a b-b ′ portion in FIG. 2. It is a manufacturing process figure of the semiconductor device of a 1st embodiment of the present invention. It is an impurity profile of the semiconductor device of the 1st Embodiment of this invention. It is an impurity profile of the semiconductor device of the 2nd Embodiment of this invention. It is sectional structure drawing of the semiconductor device of the 3rd Embodiment of this invention. It is a cutoff temperature characteristic figure of the semiconductor device of this invention. It is a plane structure figure of the semiconductor device of the 4th Embodiment of this invention. It is a plane structure figure of the semiconductor device of the 5th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 6th Embodiment of this invention. It is a plane structure figure of the semiconductor device of the 7th Embodiment of this invention. FIG. 16 is a cross-sectional structure diagram of a d-d ′ portion in FIG. 15. It is a circuit diagram of the semiconductor device of the 8th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 9th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 10th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 11th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 12th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 13th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 14th Embodiment of this invention. It is a circuit diagram of the semiconductor device of the 15th Embodiment of this invention. It is a cross-section figure of the semiconductor device of the 16th Embodiment of this invention. FIG. 25 is a three-phase inverter circuit diagram using the semiconductor device of the present invention of FIG. 24. It is a circuit diagram which drives the semiconductor device of this invention with a controller. FIG. 23 is an operation characteristic diagram of the circuit of FIG. 22.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

  FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. The semiconductor device of the present invention incorporates overheat protection and overcurrent protection circuits on the same chip as M9 in order to prevent element destruction due to overheating or overcurrent of the power MOSFET portion (M9).

  The semiconductor device of this embodiment includes a gate protection circuit, a constant voltage circuit, a temperature detection circuit, a latch circuit, a gate cutoff circuit, an overcurrent protection circuit, and a power MOSFET.

  The temperature detection circuit uses polycrystalline silicon diodes D3a to D3g as temperature detection elements. The forward voltage Vf of the polycrystalline silicon diode of the present embodiment has a temperature characteristic of about −1.5 mV / ° C. per one. Therefore, when the chip temperature rises, the voltage at the connection point between the polycrystalline silicon resistor R1 and the polycrystalline silicon diodes D3a to D3g decreases, and when this voltage falls below the threshold voltage of M1, M1 is turned off, and the cutoff circuit is turned off. Operate.

  The resistance R4 of the latch circuit is set higher by about one digit than the resistance R3. For this reason, when the semiconductor chip is not at a high temperature and the positive voltage is applied to the gate terminal, the output of the latch circuit becomes low potential and the gate cutoff circuit does not work.

  In the gate cutoff circuit, when a temperature rise is detected by the temperature detection circuit and the output of the latch circuit changes from a low potential to a high potential, M6 is turned on and the power MOSFET M9 is turned off. Once the overheat cutoff circuit operates, the output of the latch circuit becomes a high potential and the cutoff state is maintained, so that the gate voltage of M9 is held at a low potential even when the chip temperature is lowered. In order to turn on the power MOSFET M9 again, it is necessary to once reduce the voltage of the external gate terminal to near zero volts and reset the latch circuit.

  The overcurrent protection circuit monitors the drain current of M9 with the drain current of the sense MOSFET M8 having a gate width (for example, 900 μm) which is about 1/1000 or less than that of the main MOSFET M9. M7 is turned on, and the gate voltage of M9 is lowered to limit the drain current of M9.

  The first feature of the present embodiment is that the forward voltage of the polycrystalline silicon diodes D2a to D2f is used in addition to the polycrystalline silicon diodes D0a, D0c, and D0d for gate protection that limit the positive voltage of the gate terminal to 20V or less. The constant voltage circuit is provided, and the temperature detection circuit is operated using the voltage Vz1. In this embodiment, in order to further reduce the gate voltage dependency of the temperature detection circuit, Vz2 is limited to about 8 V or less by the polycrystalline silicon diode D1. In this embodiment, the diodes D2a to D2f for constant voltage circuits and the diodes D3a to D3g for temperature detection are arranged in the same direction, so that there is an effect of canceling out element variations of the diodes.

  The breakdown characteristics of the diode are soft breakdown when the withstand voltage is about 6 V or less, and a good constant voltage circuit cannot be obtained. In this embodiment, the change in Vz1 with respect to the change in the gate terminal voltage is suppressed by using the forward voltage of the polycrystalline silicon, and the voltage can be kept constant at about 3V or less. For this reason, there is an effect that the lower limit value of the gate terminal voltage at which the overheat cutoff circuit normally operates can be expanded from about 4V to about 3V. Furthermore, the constant voltage means using the breakdown voltage of the polycrystalline silicon diode D1 not only reduces the dependency of Vz1 on the gate terminal, but also suppresses the dependency of the output power supply voltage Vz2 on the temperature detection circuit on the gate terminal voltage. did it. Therefore, there is an effect that the upper limit value of the gate terminal voltage at which the overheat cutoff circuit normally operates can be expanded from about 7V to 18V or more.

  FIG. 11 shows the dependence of the cutoff temperature on the gate terminal voltage in the case where the constant voltage circuit of the present invention is provided and in the case of the conventional circuit without the constant voltage circuit. By incorporating the constant voltage circuit of the present invention, the fluctuation of the cutoff temperature when the external gate terminal voltage changes can be suppressed, so that the reliability can be improved and the usability can be improved by expanding the usable gate voltage range. There is. Specifically, the cutoff temperature has been changed by about 20 ° C. by changing the gate voltage by 3V, but according to the present invention, there is no change in the cutoff temperature at the same level until the gate voltage is changed by 10V or more. That is, according to the present invention, the change in the cutoff temperature when the gate voltage is changed by 10 V when the manufacturing margin is taken into consideration can be suppressed to 30 ° C. or less. Therefore, since the same element can be used for both the 5V power supply and the 12V power supply, the usability is improved and the reliability is improved.

  The second feature of the present embodiment is that a resistor R0c is provided to make the output power supply voltage Vz2 of the temperature detection circuit higher than the input power supply voltage Vz1 of the temperature detection circuit. Vz1 needs to be constant at a low value so that the overheat cutoff circuit can operate normally even when the external gate terminal voltage drops to about 3V. On the other hand, Vz2 must apply a voltage higher than Vz1 to the gate of M2 in order to operate the latch circuit at high speed.

  The third feature of the present embodiment is that the channel length of the temperature detection MOSFET M1 is made longer than the channel length of the gate cutoff circuit MOSFET M6. That is, the channel length of M1 is set to be long so that the variation in threshold voltage becomes sufficiently small, and the temperature detection accuracy is improved. On the other hand, the channel length of M6 in which the variation in threshold voltage has little influence on the variation in cutoff temperature is Shorten to increase current drive capability. Thereby, there is an effect that the area of the protection circuit portion can be reduced while preventing the deterioration of the shutoff temperature accuracy. The same effect can be achieved when the threshold voltage of M6 is made lower than the threshold voltage of M1.

  The fourth feature of the present embodiment is that the temperature detection diodes D3a to D3g are arranged not between the gate and the drain of the temperature detection circuit MOSFET M1, but between the gate and the source. When Vz1 fluctuates due to fluctuations in the gate terminal voltage, the fluctuations are not voltage changes across the diodes D3a to D3g, but voltage changes across the resistor R1. For this reason, in the case of this embodiment, the gate voltage dependency of the cut-off temperature can be reduced as compared with the conventional circuit (described in JP-A-63-229758).

  A fifth feature of the present embodiment is that a resistor R0b is provided in order to make the gate voltage power supply Vz3 of the MOSFET M6 for gate cutoff circuit used for blocking M9 higher than the output power supply voltage Vz2 of the temperature detection circuit. (R0a = 0 may also be used). Thereby, there is an effect that the response speed of the cutoff circuit can be increased.

  The sixth feature of the present embodiment is that, even if the gate terminal voltage becomes negative, polycrystalline silicon is used to prevent a parasitic diode between the drain and body of the protection circuit MOSFETs M1 to M7 from being forward biased. Diodes D5, D6, and D7 are provided, and further, current paths D0a to D0d are provided to prevent the breakdown of D5 to D6.

When the drain-body diode of the protection circuit MOSFET (pn junction diode formed by the n-type region 13a and the p-type region 4 in FIG. 5) is forward-biased, the drain of the power MOSFET (the n-type region 2 in FIG. 5). ) Operates as a collector, causing a problem that current flows from the drain terminal to the gate terminal. In order to prevent a current from flowing between the gate and the source, when a polycrystalline silicon diode D5 to D7 is only added, a negative voltage is applied to the external gate terminal exceeding the withstand voltage of these diodes (for example, Vgs = −10V). However, there is a problem that the above-mentioned parasitic npn transistor eventually operates. The point of this embodiment is not to prevent the current from flowing from the external source terminal to the external gate terminal, but to prevent the parasitic diode of the protection circuit MOSFET from being forward-biased. The current path is provided between the external source terminal and the external gate terminal (in this embodiment, the gate protection circuit is the current path). In order to realize this, the withstand voltage and forward voltage of the diodes D5 to D7 and D0a to D0d are set so as to satisfy the following conditions.
BV (D5), BV (D6), BV (D7)
> Vf (D0a) + BV (D0b) + Vf (D0c) + Vf (D0d)
here,
BV (D0b) = 4V,
BV (D5) = BV (D6) = BV (D7) = 7V,
Vf (D0a) = Vf (D0c) = Vf (D0d) = 0.3V.

  In order to make the breakdown voltage of D0b lower than D5, D6, and D7, it can be realized by shortening the length of the low-concentration p-type polysilicon layer 7b in FIG.

  The seventh feature of the present embodiment is that a protection circuit MOSFET M5 is provided in order to stabilize the latch circuit. Although the circuit operates originally without M5, there is a problem that the latch state is likely to become unstable because the load of the latch circuit is a resistor. In this embodiment, by adding M5, when the cutoff circuit operates and the output voltage of the latch circuit starts to become high potential, M5 is turned on and positive feedback is applied to the cutoff operation. That is, there is an effect that the gate voltage of the temperature detection circuit MOSFET M1 is further lowered, whereby the input voltage of the latch circuit is further increased, and the latch circuit state is easily stabilized. In addition, the addition of M5 has the following effects. In the case of a load having an inductance component, the external drain voltage may become lower than the external source voltage for a moment after the overheat cutoff circuit operates. At this time, the drain of the protection circuit MOSFETs M1 to M7 (n-type region 13a in FIG. 5) is the collector, the body (p-type region 4 in FIG. 5) is the base, and the drain of the power MOSFET (n-type region 2 in FIG. 5). The parasitic npn transistor as the emitter operates, the drain voltages of M1 and M4 drop, and in the worst case, the information in the latch circuit is lost. After that, when the external drain voltage becomes high, if the chip temperature is equal to or higher than the cutoff temperature, the cutoff circuit must operate again. In this circuit, when the external drain terminal of the power MOSFET becomes negative due to the addition of M5, the drain voltage of M5 also decreases due to the influence of the parasitic npn transistor, so that M1 can be turned off sufficiently deeply. Therefore, the interruption circuit is likely to work at high speed. Although the case where the drain of M5 is connected between D3e and D3f is shown in the present embodiment, it may be connected to another place as long as positive feedback works when the cutoff circuit starts to operate. For example, there are a gate of M1 and a connection point of polycrystalline silicon diodes D2a to D2f of a constant voltage circuit.

  The eighth feature of the present invention is that a capacitor C for preventing malfunction is incorporated. As a result, when the gate voltage rises rapidly, M2 is turned on to prevent the cutoff circuit from operating erroneously. This capacitor C is more effective in preventing noise from the gate if it is directly connected to the drain of M1, but there is a problem that the response speed of the cutoff circuit is lowered when the chip becomes hot, so that R2a and R2b It is connected to an intermediate point for optimization.

  FIG. 2 is a plan structural view of the semiconductor device according to the first embodiment of the present invention.

  The ninth feature of the present embodiment is that the temperature detecting element is arranged in the vicinity of the source pad (within 300 μm). Here, the temperature detecting element is an element used for temperature detection because voltage fluctuation, resistance value fluctuation, or current fluctuation is remarkable due to temperature rise. In the present embodiment, polycrystalline silicon diodes D3a to D3g are used. Conventionally, the maximum temperature of the power MOSFET was considered to be the center of the active region. However, this is the case where the temperature rise rate of the chip is made sufficiently slower than the temperature transmission speed in the chip. In the case of heat generation due to a sudden increase in drain current, such as a load short circuit accident, it has been found that the temperature rises most near the source pad. For this reason, the temperature detection diode is arranged closer to the source pad side than the temperature detection circuit unit such as M1 (see FIG. 1).

  The tenth feature of the present embodiment is that the source pad is arranged at a distance of 300 μm or more from the periphery of the chip. This is to reduce the current density flowing through the source electrode to avoid a local temperature rise and to prevent an increase in on-resistance of the source electrode.

  The eleventh feature of the present embodiment is that the temperature detection diode is disposed between the protection circuit unit other than the temperature detection diode and the source pad (in the region surrounded by P1, P2, P3, P4, P5, P6, and P7). ). Since the normal power MOSFET process has only one electrode on the chip surface, it is necessary to form the source electrode of the power MOSFET and wiring such as a temperature detection diode by this one metal electrode layer. By forming the temperature detection diode in the area between the protection circuit area other than the temperature detection diode and the external source terminal pad, the temperature near the source pad where the temperature rises most easily in the semiconductor chip in the event of a load short circuit accident At the same time as the detection diode is brought closer, the source electrode of the power MOSFET is not easily cut off, so that an increase in source resistance can be prevented. In order to prevent an increase in the source electrode, the gate finger (metal electrode layer for reducing the gate resistance) is wired so as to cover the active region of the power MOSFET and further arranged toward the source pad.

  A twelfth feature of the present embodiment is that a gate protection diode is formed around the gate pad so as to surround the gate pad, and is arranged at a corner of the protection circuit portion. As a result, it is possible to prevent the wiring of the protection circuit other than the temperature detection diode and the gate protection circuit from being obstructed by the gate pad, so that an increase in the chip area can be suppressed.

  FIG. 3 is a plan structural view of the temperature detecting element portion of the semiconductor device according to the first embodiment of the present invention, and FIG. 4 is a cross-sectional structural view of the c-c ′ portion of FIG. 1 is a high concentration n-type semiconductor substrate, 2 is an n-type epitaxial layer, and these are the drains of the power MOSFET. 7a is the gate of the power MOSFET, 12 is the source of the power MOSFET in the high concentration n-type region, 10 is the body in which the channel of the power MOSFET is formed in the p type region, and 5 is the source body of the power MOSFET in the high concentration p type region. -It is formed in order to reduce the parasitic npn transistor existing between the drains. The high-concentration p-type region 5 is also formed immediately below the temperature detection diode, and the p-type region 5 immediately below the temperature detection diode is inverted by n to prevent the parasitic element from working. Reference numeral 13 denotes a high-concentration p region formed to connect the body 10 of the power MOSFET to the source with low resistance.

  The thirteenth feature of the present embodiment is that the anode (p-type polycrystalline silicon layer 7d) and the cathode (n-type polycrystalline silicon layer 7c) of the temperature detection diode are formed in a ring shape. For this reason, there is an effect that an increase in leakage current at the end of the pn junction and an increase factor in variation in temperature characteristics can be eliminated. Although FIG. 3 shows a case where the junction is a quadrangle, an increase in the junction current at the corner can be further reduced by making these four corners arcs or obtuse angles.

  The fourteenth feature of the present embodiment is that the insulating layer 6 immediately below the temperature detection diode is formed on a thin oxide film of about 100 nm or less, which is the same level as the gate oxide film of the power MOSFET, and further a p-region polycrystalline silicon diode 7 d and the pattern of the n-type polycrystalline silicon diode 7 c are formed only in the inner part away from both sides of the polycrystalline silicon layer 7. In the present embodiment, the boron ion implantation step for forming the p-region polycrystalline silicon diode 7d is performed simultaneously with the 13 boron ion implantation step, and the step of forming the n-type polycrystalline silicon diode 7c is performed with 12 arsenic (or Phosphorus) Ion implantation is performed at the same time. For this reason, if the pattern of the n-type polycrystalline silicon diode 7c is extended to the outside of the polycrystalline silicon layer 7, the arsenic (or phosphorus) ion implantation process forms the p-type region 5 around the polycrystalline silicon diode. This is not preferable because a floating n-type region is formed. The reason why a thin insulating layer is used immediately below the temperature detection diode is to increase the heat transfer rate from the drain region 2 of the power MOSFET.

  5 is a cross-sectional structure diagram of the a-a ′ portion of FIG. 2, and FIG. 6 is a cross-sectional structure diagram of the b-b ′ portion of FIG. 2. The polycrystalline silicon diode shown in FIG. 5 has a structure of an element used for a constant voltage circuit like D2a to D2f in FIG.

  A fifteenth feature of the present embodiment is that a polycrystalline silicon diode for a constant voltage circuit using a forward voltage drop is a high-concentration n-type polycrystalline silicon layer, similar to the polycrystalline silicon diode for temperature detection shown in FIG. 7c and the high-concentration p-type polycrystalline silicon layer 7c are directly connected and further formed into a ring shape. By directly connecting the high-concentration region, the parasitic resistance component is reduced, and by forming it in the ring shape, there is an effect of eliminating an increase in leakage current at the end of the pn junction and an increase factor in variation in temperature characteristics. As described in the description of the temperature detection diode, when the four corners are formed into arcs or obtuse angles, an increase in junction current at the corners can be further reduced.

  The sixteenth feature of the present embodiment is that the capacitor of FIG. 1 is a MOS capacitor as shown in FIG. 10, and a p-type region 5 having a surface concentration higher than that of the p-type region 4 of the protection circuit MOSFET is provided immediately below the gate oxide film. It is in use. This prevents the surface of the p-type region 5 from being n-type inverted or increasing in resistance even when the voltage of the polycrystalline silicon layer 7a of the MOS capacitor is increased (see FIG. 8). Furthermore, by forming the p-type region 13 by being surrounded by the capacitor polycrystalline silicon layer 7a, the parasitic resistance in the p-type region 5 is reduced.

  FIGS. 7A to 7B are manufacturing process diagrams of the semiconductor device according to the first embodiment of the present invention, and are cross-sectional structure diagrams of main processes until the structure of FIG. 5 is obtained. FIG. 8 shows the impurity profile of the p-type well 4 of the protection circuit MOSFET, the p-type well region of the power MOSFET, and the impurity profile of the p-type region 5 used immediately below the capacitor. The p-type region 5 has a higher concentration than the p-type region 4 by increasing the amount of boron ion implantation by about one digit.

  An outline of a method for manufacturing a semiconductor device will be described below.

  (1) After forming the n-type epitaxial layer 2 on the high-concentration n-type substrate 1, the insulating layer 3 is formed, and boron ions are implanted and diffused to form the p-type regions 4 and 5 using this as a mask. Perform {FIG. 7 (a)}.

  (2) After removing the insulating layer 3, the insulating layer 6 is formed by selective oxidation using a nitride film and a gate oxidation step, and then the polycrystalline silicon layer 7 is formed. Thereafter, an insulating layer 8 is formed in a region where a polycrystalline silicon diode and a high-resistance polycrystalline silicon resistor are to be formed {FIG. 7B}.

  (3) An n-type impurity such as phosphorus is doped in a region not protected by the insulating layer 8 of the polycrystalline silicon layer 7 to form a 7a region. Next, the insulating layer 8 is removed and a p-type polycrystalline silicon layer 7b is formed by boron implantation. Next, the polycrystalline silicon layers 7a and 7b are patterned and formed and diffused in a self-aligned manner with the polycrystalline silicon layer 7a to form the p-type region 10 whose main purpose is to form the channel region of the power MOSFET. Then, after the low concentration n-type region 11 is formed by phosphorus (or arsenic) ion implantation process for increasing the breakdown voltage of the protection circuit MOSFET, the insulating layer 9 is formed.

  (4) Thereafter, the step of forming the n-type polycrystalline silicon diode 7c is performed simultaneously with the arsenic (or phosphorus) ion implantation of the n-type region 12, and the boron ion implantation for forming the p-region polycrystalline silicon diode 7d is performed. Simultaneously with the boron ion implantation process in the p region 13. Thereafter, an insulating layer 14 (including the insulating layer 9 and the same in other drawings) is formed, contact formation, metal electrode layer 15 formation, insulation layer 16 formation, back surface etching, back surface electrode 17 formation are performed, FIG. 5 is reached.

  FIG. 9 is an impurity profile of the semiconductor device according to the second embodiment of the present invention. The feature of this embodiment is that the p-type region 4 which is the body region of the protection circuit MOSFET has a retrograde profile in which the impurity concentration in the silicon is about one digit higher than the surface concentration. Here, 4a is the profile of the n-type diffusion layer for reducing the surface concentration of 4a of the profile [5] of the p-type diffusion layer. As a result, the threshold voltage of the protection circuit MOSFET is suppressed to about 1.5 V or less as in the first embodiment, and the cutoff circuit works even if the external gate voltage drops to about 3 V. Further, there is an effect that the effect of the parasitic npn transistor constituted by the drain and body of the protection circuit MOSFET and the drain of the power MOSFET can be suppressed.

  FIG. 10 is a sectional structural view of a semiconductor device according to the third embodiment of the present invention. The feature of the present embodiment is that the p-type region 4 is formed deeper than the p-type region 5. As a result, the threshold voltage of the protection circuit MOSFET is suppressed to about 1.5 V or less, as in the first embodiment, and the parasitic npn formed by the drain of the protection circuit MOSFET, the body, and the drain of the power MOSFET. The effect of the transistor can be suppressed.

  FIG. 12 is a plan view of a semiconductor device according to the fourth embodiment of the present invention. In the present embodiment as well, in the same manner as in the first embodiment, the temperature detection element is arranged between the protection circuit region other than the temperature detection element and the source pad (P7, P8, P9, P10, P11, P12, P13, (In the region surrounded by P14, P15, P16). Further, in this embodiment, the temperature detection element is brought close to the region where the chip temperature is highest while suppressing the source electrode resistance, so that the corners of the protection circuit region other than the temperature detection element are made into four or more polygons. Yes.

  FIG. 13 is a plan view of a semiconductor device according to the fifth embodiment of the present invention. In the present embodiment, an example of arrangement of temperature detecting elements when there are a plurality of source pads is shown. In the present embodiment as well, in the same manner as in the first embodiment, the temperature detection element is arranged between the protection circuit region other than the temperature detection element and the source pad (P17, P18, P19, P20, P21, P22, P23, (In the region surrounded by P24). In addition, the temperature detecting element may be placed in one place, but in order to increase the temperature detection accuracy, the temperature detecting element is provided in two places in the present embodiment. For example, in the case of the circuit of FIG. 1, it may be divided into D3a, D3b, D3c, D3g and D3d, D3e, D3f and arranged at two locations.

  FIG. 14 is a circuit diagram of a semiconductor device according to the sixth embodiment of the present invention. In the present embodiment, a circuit in the case where two temperature detection elements are arranged apart from each other as shown in FIG. 13 is shown. Of course, in this embodiment, the temperature detection accuracy is improved by arranging the temperature detection diodes in parallel.

  FIG. 15 is a plan view of a semiconductor device according to the seventh embodiment of the present invention. The feature of this embodiment is that a temperature detection diode is arranged immediately below the source pad where the chip temperature becomes highest in a load short circuit accident.

  FIG. 16 shows a cross-sectional structure of the d-d 'portion of FIG. The present embodiment is characterized in that the second metal electrode layer 18 is provided on the protective circuit with the insulating layer 16 interposed therebetween. For this reason, the temperature detection circuit can be arranged immediately below the source pad as shown in FIG. In addition, when the second metal electrode layer 18 is formed on the temperature detection element, that is, to cover the temperature detection diode portion as in the present embodiment, the heat generated in the second metal electrode layer 18 is also reduced. Since it is transmitted through the insulating layer 16, there is an effect that the response speed of temperature detection is increased. For this reason, even when the temperature detecting element is not disposed directly under the source pad, the thermal response speed is improved by adding the second metal electrode layer 18.

  FIG. 17 is a circuit diagram of a semiconductor device according to the eighth embodiment of the present invention. The only difference between this embodiment and FIG. 1 is the connection point of the gate terminal of M5. In the case of this embodiment, positive feedback is not applied to the latch circuit as shown in FIG. 1, but the second effect by adding M5 as described above, that is, the drain of the power MOSFET by adding M5 in this circuit. When the terminal becomes negative, the drain voltage of M5 also decreases due to the influence of the parasitic npn transistor, so that M1 can be turned off sufficiently deeply. For this reason, it becomes easy to operate the interruption circuit at high speed.

  FIG. 18 is a circuit diagram of a semiconductor device according to the ninth embodiment of the present invention. The present embodiment is characterized in that the operation of M5 in FIG. 17 is realized by M10. M10 also serves as the polycrystalline silicon diode D1 of the constant voltage circuit.

  FIG. 19 is a circuit diagram of a semiconductor device according to the tenth embodiment of the present invention. In this embodiment, the drain terminal of the power MOSFET becomes negative, and the gate voltage of M6 is easily held by the polycrystalline silicon diode D8 even if the information of the latch circuit is lost. In the present embodiment, the reset of the cutoff circuit is completely completed because the voltage Vx needs to be lowered due to the leakage current of the diode D8.

  FIG. 20 is a circuit diagram of the semiconductor device according to the eleventh embodiment of the present invention. In this embodiment, the current in the latch circuit is prevented from flowing through the resistor R0a. As a result, when the cutoff circuit starts to work, there is an effect that it is possible to prevent the voltage Vz2 or Vz1 from fluctuating due to an increase in the current of R0a and the cutoff condition becoming unstable. FIG. 21 is a circuit diagram of a semiconductor device according to a twelfth embodiment of the present invention. The circuit diagrams of the embodiments so far have been related to the latch type overheat protection circuit built-in power MOSFET. On the other hand, in the present embodiment, in the case of the hysteresis type overheat protection built-in power MOSFET that is automatically released when the chip temperature drops, for example, by about 100 ° C. even if the chip becomes hot and the cutoff circuit operates. FIG. The feature of the present embodiment is that the connection between FIG. 1 and M3 is different and that M5 is not required (M3 comes to work the same as M5). The present embodiment is different from the latch type circuit only in the behavior after the shut-off circuit operates, and the characteristics of this circuit are the same as those described in the first embodiment.

  FIG. 22 is a circuit diagram of a semiconductor device according to a thirteenth embodiment of the present invention. In this embodiment, a hysteresis circuit and a latch circuit are incorporated, and the hysteresis circuit operates at a lower temperature than the latch circuit. As a result, the hysteresis circuit works for slow temperature rise, and the shut-off circuit is automatically released after the chip cools down.However, the hysteresis circuit operates and feeds back to the temperature detection circuit for a sudden increase in chip temperature. Since the latch circuit also operates before this, the cut-off state is maintained even after the chip cools down. In other words, it is possible to operate differently depending on the situation, such as the latch circuit works when the load is abnormal, such as a load short circuit, and the hysteresis circuit works when the chip temperature rises due to a slow rise in ambient temperature. It is.

  FIG. 23 is a circuit diagram of a semiconductor device according to a fourteenth embodiment of the present invention. The present embodiment is characterized in that M11 is added to the overcurrent protection circuit and connected to the hysteresis circuit. When an overcurrent with a relatively low level flows, the gate current of the power MOSFET is lowered by M7 to limit the overcurrent as in the previous embodiments, but an overcurrent with a relatively high level such as when the load is short-circuited. When a current flows, the hysteresis circuit is operated by M11 to completely cut off until the chip temperature decreases. As a result, it is possible to protect against a sudden rise in the chip temperature that does not keep up with the response of the temperature detection circuit. If M11 of this embodiment is added to the circuit of FIG. 22 and the drain of M11 is connected to the gate of M4 ′, it is possible to incorporate a latch-type overheat cutoff characteristic and a hysteresis-type overcurrent cutoff circuit. is there.

  FIG. 24 is a circuit diagram of a semiconductor device according to a fifteenth embodiment of the present invention, and FIG. 25 is a sectional view thereof. The high-concentration P-type semiconductor substrate 19 is a collector, the high-concentration n-type region 20 is an n-type buffer layer for preventing minority carrier injection from the collector, the n-type epitaxial layer 2 is an n-base, the p-region 10 is a p-type base, The high concentration n-type region 12 is an emitter. In the present embodiment, an IGBT (Insulated Gate Bipolar Transistor) is used instead of a power MOSFET and an overcurrent protection circuit is built in. M9 is a main IGBT, and M8 is a sense IGBT. A feature of this embodiment is that, in order to prevent a parasitic current from the collector to the gate when the gate becomes negative, the polycrystalline silicon diodes D7a to D7c and D0e to D0h are provided as described in the description of FIG. It is a point that is provided. In the case of IGBT, when the gate voltage becomes negative and the drain-body diode of the protection circuit MOSFET M7 is forward-biased, it is composed of an n region 13a, a p region 4, n-type regions 2 and 20, and a p region 19. Since the parasitic thyristor operates, the situation is more serious than in the case of the power MOSFET. In order to prevent the operation of the parasitic thyristor, the breakdown voltage and the forward voltage of the polycrystalline silicon diode may be set so as to satisfy the following relationship based on the same concept as in FIG.

BV (D7a) + BV8 (D7b) + BV (D7c)>
Vf (D0e) + BV (D0f) + Vf (D0g) + BV (D0h)
Here, BV (D7a) = BV8 (D7b) = BV (D7c) = BV (D0f) = BV (D0h) = 7V, Vf (D0e) = BV (D0f) = Vf (D0g) = 0.4V
If the breakdown voltage is not required when the gate becomes negative, the polycrystalline silicon diodes may be only D7a and D0e. In this case,
BV (D7a)> Vf (D0e)
If this relational expression is established, the parasitic thyristor operation can be prevented. When this element is operated at high speed by an emitter follower circuit (a circuit in which a collector is connected to a power source and an emitter is connected to a load), a current flows from the emitter terminal to the gate terminal. The right side of the inequality increases. Therefore, when it is necessary to increase the allowable current from the emitter terminal to the gate terminal, the gate protection circuit composed of D0e, D0f, D0g, and D0h is formed as an external diode to satisfy the above inequality and D7a, It is necessary to prevent the breakdown of D7b and D7c.

  FIG. 26 shows a three-layer inverter circuit using the IGBT with built-in overcurrent protection circuit shown in FIG. In the case of the circuit of FIG. 24, since a leak current does not occur from the collector of the IGBT to the gate even when a negative voltage is applied to the gate as described above, the IGBT with a built-in overcurrent protection circuit is configured with an emitter follower as in this embodiment. It is possible to use.

  In FIG. 27, the gate current increases rapidly when the protection circuit built-in power MOSFET cutoff circuit described in the present invention is activated. For this reason, after monitoring this gate current using the gate current detection circuit, and when the shut-off operation works with the power MOSFET with built-in overheat protection circuit, the output Vout of the microcomputer, which is the controller, is set to a low potential, and after checking for abnormalities It is possible to construct a highly reliable system in which Vout is set to a high potential again.

  FIG. 28 is a supplementary explanatory diagram of the operation of FIG. T1 is a chip temperature at which the hysteresis type overheat cutoff circuit starts to operate, T2 is a temperature at which the hysteresis type cutoff operation is released, and T3 is a chip temperature at which the latch type overheat cutoff circuit operates. When the chip temperature is equal to or lower than T1, the drain current Id flows. If the rise in the chip temperature is slow, the cutoff circuit works when the chip temperature reaches T1, and the chip temperature falls, and when T2, the current automatically flows. However, when the rising speed of the chip temperature is abrupt, the chip temperature increases even after the systemic circuit starts to work, and reaches the operating temperature T3 of the latch circuit. In this case, the drain current is not automatically restored even after the power MOSFET is cut off and the chip temperature is lowered, and it is necessary to reset the external gate terminal to zero volt once.

  In various embodiments of the present invention described above (planar structure of semiconductor device: chip layout), the constant voltage circuit diodes D2a to D2f (see FIG. 1) have temperature characteristics similar to those of the temperature detection diodes D3a to D3g. Since it has, it can arrange in the same place (refer FIG. 2) as D3a-D3g including resistance R1.

  The present invention can be used for a power insulated gate semiconductor device.

M1 to M7, M10, M11, M2 ′ to M6 ′ MOSFET for protection circuit
M8 Sense element of power MOSFET (IGBT) M9 Main element of power MOSFET (IGBT) D1 to D9 Diode D0a to D0h Gate protection circuit diode D1, D2a to D2f Constant voltage circuit diode D3a to D3f Temperature detection diode D4aD4b , D4c Overcurrent protection circuit diode D5, D6, D6 ′, D7 Negative voltage protection diode C Capacitors R0a to R0c, R1, R2, R2a, R2b, R3, R3 ′, R4, R4 ′, Rg, Rg1, Rg2 , Rs resistance 1, 2, 11, 12, 20 n-type region 3, 6, 8, 9, 14, 16 Insulating layer 4, 5, 10, 13, 19 p-type region 7 Polycrystalline silicon layer 7a, 7c, 7c n-type polycrystalline silicon layers 7b, 7d p-type polycrystalline silicon layers 15, 17, 18 Metal electrode layers M1-M9 MOSFET for protection circuit

Claims (7)

A semiconductor device comprising a first insulated gate bipolar transistor and a second insulated gate bipolar transistor and comprising a first external terminal, a second external terminal and a third external terminal,
The collectors of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor are connected to each other,
The gates of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor are connected to each other,
Each collector is connected to the first external terminal;
An emitter of the first insulated gate bipolar transistor is connected to the second external terminal;
Each of the gates is connected to the third external terminal. Comprising a first MOSFET;
A drain of the first MOSFET is connected to a gate of the second insulated gate bipolar transistor;
An emitter of the second insulated gate bipolar transistor is connected to a gate of the first MOSFET;
2. The semiconductor device according to claim 1, wherein a current-voltage conversion unit is connected between the emitter of the second insulated gate bipolar transistor and the second external terminal.   3. The semiconductor device according to claim 2, wherein the current-voltage conversion means is a first diode having an anode connected to an emitter of the second insulated gate bipolar transistor and a cathode connected to the second external terminal.   3. The semiconductor device according to claim 2, further comprising: a second diode having an anode connected to a gate of the second insulated gate bipolar transistor and a cathode connected to a drain of the first MOSFET.   2. The semiconductor device according to claim 1, further comprising a resistance element between the first external terminal and a base of the second insulated gate bipolar transistor. A third diode and a fourth diode;
A cathode of the third diode is connected to a gate of the second insulated gate bipolar transistor;
The semiconductor device according to claim 1, wherein an anode of the third diode is connected to the second external terminal. A third diode and a fourth diode;
A cathode of the third diode is connected to a gate of the second insulated gate bipolar transistor;
An anode of the fourth diode is connected to a gate of the second insulated gate bipolar transistor;
6. The semiconductor device according to claim 5, wherein a cathode of the fourth diode is connected to the second external terminal.

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