JPH0266666A - Inter-cpu interruption processing method - Google Patents

Abstract

PURPOSE:To infinitely increase the number of interruption vectors by securing such a constitution where a CPU of the interruption request side writes the address of an interruption process routine into an interruption vector register for each interruption request and a CPU of the interruption process side fetches the interruption vector register to carry out the interruption process with an interruption request. CONSTITUTION:A CPU 2 writes an instruction for jump to an interruption process routine into an IVR 10 before transmission of an interruption request. Then the CPU 2 sends an interruption request signal IRQ to a CPU 1. The CPU 1 receives the signal IRQ and sends an interruption acknowledge signal IACK to the CPU 2 to perform a jump to an address of the IVR 10 from an address of a memory 6. The CPU 2 receives the signal IACK and clears the signal IRQ. The CPU 1 carries out the jump instruction of the IVR 10 and performs an interruption process. The CPU 2 rewrites the contents of the IVR 10 based on the program of a memory 8 and transmits the signal IRQ in case another interruption is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to
This invention relates to an interrupt processing method between LJs.

(Prior Art) In a computer, the CPLI is connected via an input/output port. llll! When exchanging data with the A-device, the operation of external input/output equipment is slower than that of the CPU, so if the CPU were to randomly receive data each time, it would be a big waste of time. So input/output l! ! After instructing one device to transfer data, the GPU performs another task, and if it processes the data as soon as it is sent, it becomes a very efficient system. 3 for this kind of thinking
Interrupts were subsequently invented.

Next, an example of requesting an interrupt from the CP LJ to another CPU will be explained with reference to the drawings. FIG. 2 is a diagram illustrating a conventional interrupt procedure. In the figure, 1 is a CPLJ that performs a cutting operation while an operation is being performed, and 2 is a C P jJ that requests an interrupt to the CPUI and causes the interrupt operation to be performed. This conventional interrupt processing procedure is performed as follows.

(2) CPU2 sends an interrupt request signal IRQ to cpui.

■CP tJ 1 receives this and CP tJ
2, returns the interrupt recognition signal 91ACK to CP (J
■CP tJ When 2 receives the interrupt recognition signal IACK, it sends an interrupt vector number (address of the scraping processing program) to CPU 1 depending on the type of the interrupt.
Send VP.

(2) When the CPU 1 receives the interrupt vector number IVP, the CPU 1 reads the contents rv of the address specified by the interrupt vector number 1 IVP in the lid file (hereinafter referred to as rVF) 3 to the interrupt.

(CPU 1 then jumps to address 1v and executes interrupt processing.

(rIIffl to be solved by the invention) In a conventional device that performs the above processing, if the number of interrupts is large, l VP
3, the contents of many addresses must be stored in IVs, which requires a large amount of memory. Also, the contents of the interrupt are IVF
This is due to the interrupt vector written in 1 in 3, and it is difficult to change the process at any time. Furthermore, upon receiving the interrupt request IRQ, the interrupt recognition signal rAcK is sent to j
When receiving the interrupt vector number 1vP, it is necessary to send the interrupt vector file IMF to the CPU 1.
The present invention was made in view of the above-mentioned problem, and its purpose is to simplify the interrupt processing procedure, and to reduce the number of interrupt vectors from the mathematics of interrupt processing. The object of the present invention is to realize a method for processing interrupts between CPUs that can handle an infinite number of interrupts.

(Means for Solving the Problems) The present invention for solving the above-mentioned problems is a method for converting CP tJ to other C
In an inter-CPU interrupt processing method for a PU, an interrupt vector register is provided that is connected to the CPU on the interrupt requesting side to enable reading and writing, and to the CPU on the interrupt processing side so as to enable reading. , the address of the interrupt processing routine is written into the interrupt vector register each time an interrupt request is made, and the interrupt processing side CP tJ fetches the interrupt vector register and executes a command.

(Function) The interrupt requesting side CP (J inserts the address of the interrupt processing routine into the interrupt vector register each time an interrupt request is made, and the interrupt processing side CPLJ fetches the interrupt vector register based on the interrupt request and executes processing.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram for carrying out an interrupt processing method according to an embodiment of the present invention. In the figure, parts equivalent to those in FIG. 2 are given the same reference numerals. Memory 6 stores the program of CPLJl, and GPtJl is 1-Tabus 7.
connected via. A memory 8 stores programs for the CPU 2 and is connected to the CPU 2 via a data bus 9.
The CPU 2 is connected to the CPU 2 via a data bus 9 so as to be readable from the CPU 2, and the CPU 2 is connected to the CPU 2 via a data bus 9 so that the CPU 2 can be read from and processed by the CPU 2. Incorporated, C
This is an interrupt vector register (hereinafter referred to as TVR) that provides a jump instruction to PU1.

Next, the operation of the circuit of the embodiment will be explained. , CPU2 to c
The case where an interrupt is applied to pu i is as follows.

(2) Before issuing an interrupt request, the CPU 2 inserts a jump instruction to the interrupt processing routine into IVRlo.

(2) CPLI2 sends an interrupt request signal IRQ to CPU1.

■When CPU 1 receives the interrupt request signal IRQ,
It sends an interrupt recognition signal rAcK to the CPU 2 and jumps from the address of the memory 6 to the address of IVRIO. C
When the PU2 receives the interrupt recognition signal IACK, it clears the interrupt request signal IRQ, and the CPU1 subsequently executes the IVRIO jump instruction and enters interrupt processing.

■If the CPLJ2 wants to issue another interrupt, it rewrites the contents of IVRlo based on the program in the memory 8 and sends out the interrupt request signal IRQ.As explained above, according to this embodiment, the following occurs. You can expect good results.

(In the conventional circuit, D CPU 1 had to receive the interrupt request signal IRQ, then receive the interrupt vector number IVP, and then take out the interrupt vector ■v from the cover file 3 to the vl interrupt. In the circuit according to the method of this embodiment, upon receiving the interrupt request IRQ, it is sufficient to simply return the interrupt recognition signal rAcK and jump to the address of IVRlo.

(2) In the conventional method, the number of interrupt vectors was limited to the size of IVFlo, but according to this embodiment, an infinite number of interrupt vectors can be set with register 1gA of rVRlo.

■By doing the following, you can prioritize interrupts without using a priority encoder.CP (J2 is rVRl
o, and if it is "0", rewrite IVRlo, "'
o ” If there is no t', IVRlo is 110 I+ if it has a higher priority compared to the vector to be processed now.
If not, the value of rVRlo is replaced and an interrupt request signal IRQ is sent. CPLll
clears the value + v r < io when the interrupt processing is completed.

(2) If a jump command to the reset processing routine is installed in the TVR 10, it can also be used in common with the reset signal q.

(Effects of the Invention) As explained in detail above, the interrupt processing procedure is simplified, and an unlimited number of interrupts can be handled, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 shows the method of the present invention in practice! FIG. 2 is a circuit diagram of a conventional method.

Claims (1)

[Claims] In an inter-CPU interrupt processing method performed from a CPU to another CPU, an interrupt vector is connected so as to enable reading and writing to the interrupt requesting CPU, and to enable reading from the interrupt servicing CPU. Interrupt processing between CPUs, comprising a register, writing an address of an interrupt processing routine in the interrupt vector register each time an interrupt request is made, and the CPU on the interrupt processing side fetches the interrupt vector register and executes a command. Method.