KR930005843B1 - Method for controlling subprocessor in multiprocessor system - Google Patents

Abstract

The method for efficient and high speed data transfer of the host processor data to all the subprocessors in the system that the host processor generates the same signals for down-loading, comprises the following steps of: providing several group signals for the designated channels of which number is pre-determined to the each one of subprocessors (20); down loading formatted data to sub-processors (20) with using virtual memory address generated by the host processor (10); receiving, buffering and transferring above formatted data to the subprocessors (20); multiplexing interrupts which are generated by each of sub processors when the access cycle is successfully terminated.

Description

Control Method of Multiple Subprocessors in Multiprocessor System

1 is a block diagram schematically illustrating signal communication between a host processor and a signal processor through a bus interface.

FIG. 2 shows the bus interface of FIG. 1 in more detail, illustrating a subprocessor control method in accordance with the present invention. FIG.

* Explanation of symbols for main parts of the drawings

10: host processor 20: subprocessor

40: control signal generator 42: data direction control unit

45: interrupt concentrator

The present invention relates to a multiprocessor system, and more particularly to a method for controlling a plurality of subprocessors of a subsystem, for example a digital signal processor (DSP), by a host processor of a main system.

In general, a multiprocessor system refers to a system having two or more processors that share a memory, an input / output device, and a bus.

In a typical computing system, the main system includes a CPU which is a general-purpose microprocessor to a host processor and an input / output processor (IOP) for input / output control in the concept of a sub-processor. Since a microprocessor requires a lot of computation time, there is a signal processing processor which is one or more processors that independently process a digital signal assigned to the microprocessor independently.

The second processor in the signal processing unit focusing on such a high speed digital arithmetic function is commonly referred to as a DSP (Digital Signal Processor). Widely used in FFT.

It may include an interface means for signal communication between the main system and the subsystem and the signal processing unit, in the above description that the main system and the signal processing unit may be integrated in a single PCB board or may be separate from each other. You should know

In addition, the present invention will be described with reference to "multi-bus structure of a multiple processor system" of the patent application filed on the same day as the present application.

In the case where there are a plurality of DSPs in the signal processing unit, since the plurality of DSPs individually perform the assigned digital signal processing but are all dependent by one host processor, all control signals must be provided from the host processor. In other words, the conventional host processor and subprocessor configuration generally uses the same memory and bus under the concept of one-to-one connection, and thus, when processing a signal input through multiple channels of the signal processor, it is difficult to control the subprocessor. have. In particular, there may be cases where the control signals or data downloaded from the host processor to each subprocessor are different and may be common. In the case of different signals as in the former, the host processor and the subprocessor are mutually one-to-one. The relationship will be chosen to provide a different signal to the input channel of each subprocessor. However, even with the same control signal, the host processor must repeatedly provide the same data to the input channel of each subprocessor.

In this case, the channel is generally simply a means for relaying data and may be understood as a means for performing an operation of a signal processor.

Such control signals may include, for example, signals for enabling, resetting, or initializing the channels of each DSP, processing mode selection signals for each DSP, acknowledgment (ACK) signals for interrupt requests, and memory means for the DSP. RAM) may include a signal for initializing it.

If a signal provided to a signal processing unit having a plurality of channels is processed according to a one-to-one concept, it takes time (number of signal processing unit channels) x (signal transmission time), which causes a waste of time. In addition, this may cause a problem that the data processing capacity of the main system is significantly reduced.

Accordingly, an object of the present invention is to provide a method for efficiently collectively controlling subprocessors in a plurality of signal processing units by one host processor when the control signals transmitted from the host processor to the channel of the signal processing unit are the same. Therefore, the present invention will be a method of controlling only one subprocessor from the viewpoint of the host processor.

The method of the present invention for achieving the above object is to allocate an area of the main memory (particularly RAM) of the host processor for each control signal provided to each channel of the signal processor, when the same control signal is downloaded from the host processor Decoding the data accessed by the address corresponding to the allocated area of the memory to generate various control signals. In addition, the signal transmission may further include the step of collectively requesting the interrupt to the host processor by collecting the interrupt signal indicating that the operation of each sub-processor is finished.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, an exemplary description in which one host processor controls a plurality of subprocessors using a dual bus structure, wherein reference numeral 10 is a host processor in the main system, and 12 is a main processor in the main system. Data memory means (RAM). Each of the DSPs 21, 22, 23, ... of the signal processor 20 has a plurality of channels, and the channels are CH1, CH2,... It is represented by CHn.

Referring now to FIG. 2, the illustrated bus interface 100 is shown in greater detail in FIG.

Typically the computer system has address lines which can each access a respective area of the data memory means 12. For example, a 16-bit computer will usually have more than 16 (typically 24) address lines, which has 16 Mbytes of physical memory capacity. In addition, a massive virtual address space of 1 Gbyte / task can be provided.

The physical address space is called real mode (or real address mode) in some systems, and the virtual address space is called protect mode (or protected virtual address mode). When such a virtual address is actually used, it is possible to convert it to a real memory address, which may be possible by characteristic hardware or a program.

The present invention allocates the memory space of the virtual address area for each control signal provided to each channel of the signal processor to generate the control signal provided to each channel.

The following table shows an example of allocating memory areas.

[table]

In the above table, the CH1 monitor data of the subprocessor is indicated to be allocated to the 280001 (hexadecimal) address of the host processor for processing, and other signals such as reset or interrupt are also described. Memory is allocated and formatted configuration and overall contents are omitted.

When the host processor downloads control signals to a plurality of subprocessors, the host processor 10 accesses the corresponding area of the memory means 12 in which the necessary control signals are recorded in some form.

The control signal generator 40 converts the sub-processor control signal corresponding to the virtual n-bit address signal output from the memory means 12. Such a conversion function may be easily implemented by those skilled in the art by using buffering, for example, decoding techniques.

In the figure, control signals are represented as RESET, ACK, INITAL,... As described above. It will be ENABLE traffic light. These signals will be collectively input to each channel CH1 to CHn.

The data, address and control buffers 31, 32 and 33 are means for temporarily latching data, address and control data, and are connected to the data, address and control buses, respectively.

When downloading the same data from the host processor to each subprocessor of the signal processor, the data D0, D1 to Dn are provided to the respective channels CH1, CH2 to CHn through the data bus buffer 31.

Since the data bus has bidirectional characteristics, the direction control section 42 allows the user to select whether the data is transmitted in the direction of the host processor 10 or the signal processing sections 21, 22,...

The address bus buffer 32 and the control line buffer 33 respectively transmit address and control signals (read RD and write WR, ... (C)) output from the host processor 10 to each channel CH1 to CHn. To provide.

The bus on / off controller 41 operates by decoding by the control signal generator 0 to control on / off the data bus buffer 31, the address bus buffer 32 and the control line buffer 33. . This on / off control can be loaded on a bus located in the buffers.

The present invention further includes a step in which each signal processor 21, 22, ... collectively transmits an interrupt signal INT notifying the host processor 10 of its completion. The channel interrupt concentrator 45 transmits the interrupt signals collected from the channels CH1 to CHn to the host processor 10. Accordingly, the host processor 10 may collectively provide an acknowledgment signal (ACK) to each channel as described above to acknowledge it as a channel of the signal processor.

Claims (2)

In the method of controlling a subprocessor of a multiprocessor system comprising a host processor and a plurality of subprocessors having a plurality of channels that independently process data allocated to the host processor independently of the host processor. A virtual area other than the physical storage area of the memory means 12 associated with 10) is provided to each panel CH1 to CHn of the subprocessor 20 for allocating for each signal; When the same signal or data is downloaded from the host processor 10 to the plurality of subprocessors 20, the corresponding signal is accessed by designating the address of the corresponding virtual area in the memory means 12 in which the signal is allocated and stored. Outputting format data; Receiving the output format data, and buffering the data to provide the same data to each channel of the subprocessor. The integrated interrupt signal of claim 1, wherein when the batched results of the plurality of subprocessors 20 are transmitted to the host processor 10, the interrupt request signal generated from each channel of each subprocessor is received. And a channel interrupt tangential unit (45) for outputting the signal to the host processor.