CN1019336B - Microprocessor vectored interrupts - Google Patents

Abstract

The present invention relates to a data processing system which comprises a plurality of subsystems together connected to one system bus. The subsystems communicate with each other by mutually transmitting commands by the system bus. The subsystems are identified by channel numbers. Each subsystem provided with a device for receiving a priority interrupt application command stores interrupt vectors in a random-access memory, the vectors addressed by the channel numbers of the subsystem putting forward the interruption designating the offset which needs to be added to a base address of an exception vector table, and each exception vector stores an internal storage initial address of an interrupt program.

Description

Microprocessor vectored interrupts

The present invention relates to data handling system.More precisely, relate to be used for expanding the device of microprocessor interrupt capabilities.

Generally speaking, microprocessor can be accepted a limited number of preferential interruption.For example, 32 bit microprocessors 68020 of Mo Tuoluola company have seven grades of interrupt priority levels, and the 7th grade is limit priority, the no interrupt request of zero level representative.

Described according to " 32 bit microprocessor MC68020 user manual " second edition that Prentice-Hall publishing company publishes, when microprocessor carries out the abnormal interruption processing, it obtains a vector number from interrupting device, and the interrupt level that will be responded number is put into address bus A ₁-A ₃On.If vectorial number is not produced by interrupting device, then vector is specified in the external logic request automatically.Processor is inner to produce a vector number, and this vector is number by interrupt level number decision.

But in a data handling system that has a plurality of processors and a large amount of peripheral subsystems, the preferential interrupt number that is provided is too limited.

Therefore, provide a kind of follow-on data handling system, making it have a large amount of preferential interruptions is exactly purpose of the present invention.

A kind of data handling system has comprised many subsystems, and all these subsystems are connected on the system bus, form conventional subsystem with these subsystems, and this in addition conventional subsystem comprises non-proprietary subsystem (NPE).This non-proprietary subsystem is carried out non-proprietary application software.

NPE receives interruptive command from other subsystem.These orders comprise the channel number of NPE, the function code of the operation that the channel number of request subsystem and explanation NPE will carry out.NPE has comprised an interruption coincidence register IIR, and it is storing the channel number of interrupting device.

When receiving order, if the CPU (central processing unit) on the NPE (CPU) is not being carried out higher order, it will receive an override requests, and answer it.

When CPU answers this when order, be stored in the address input end that channel number among the IIR is added to interrupt vector array random-access memory (ram).RAM has stored the eight biased amounts of shifting in the unit of corresponding each channel number.

Exception vector table is being stored pointer, and it points to the start address of interrupt routine.This interrupt routine is used for handling interrupt requests.CPU provides a base address, four times of additions of this base address and offset vector value, thus in exception vector table, finding this pointer, this pointer is exactly the start address of interrupt routine.

According to following detailed description of the accompanying drawings, can understand the executive mode of the inventive method well, constructive method of apparatus of the present invention and its working method.

Fig. 1 is the block diagram of total system, and it has comprised the detailed logic block diagram of non-proprietary subsystem.

Fig. 2 is the form that sends to some order on the system bus.

Fig. 3 is for handling preferential detailed logic of interrupting.

Fig. 4 is for using used flow graph in the example of the present invention.

Fig. 1 is the block diagram of data handling system 1, it comprises a system management facility (SMF) 32, some selectable process devices 34, an external memory storage 30 and some optional peripheral subsystems 36 and a non-proprietary subsystem 3, all these is connected on the system bus 16, SMF32 provides startup and central authorities' control of whole data handling system 1, and external memory storage 30, optional processor 34 and optional peripheral subsystem 36 are all worked routinely.

Non-proprietary system (NPE) 3 provides a series of interface systems, and non-proprietary operating systems can connect by these interface systems.The construction personnel of system can combine the standard software of conventional subsystem in each side existing application software and the data handling system 1, thus the method for the problem that is resolved.NPE3 comprises 10 and non-memory access unit 14 of 4, one Memory Management Unit of 2, one science processing units of a CPU (central processing unit) (CPU) (SPU) (MMU).All these is attached on address bus 6 and the data bus 8.Memory access unit (MRU) 12 is connected to data bus 8, and is connected on the MMU10 by physical address bus 18, and local storage 28 is connected on the MRU12 by data bus 24 and address bus 26.MRU12 and NMRU14 are connected on the system bus 16.

CPU2 is typical Mo Tuoluola 68020 microprocessors.It produces 32 bit address signals on address bus 6, receive on data bus 8 or produce 32 bit data signals, and some control ends are arranged.SPU4 is typical Mo Tuoluola 68881 floating-point coprocessors.Floating point instruction is carried out in SPU4 and CPU2 cooperation.CPU2 gets finger, and carries out instruction decode, calculates effective address, sets up the operand index value.Execute instruction by SPU4 then.

Preferential interrupt logic 38 is handled the interruptive command that receives from system bus 16.

MMU10 is typical Mo Tuoluola 68851 memory paging management unit.Its receives the CPU2 logical address that is transmitted by address bus 6, and produces an actual address and be sent on the bus 18.MRU12 receives actual address from MMU10 and system bus 16, and determines it is visit local storage 28, or access external memory 30.If for local storage is write, MRU12 adds parity check bit to each from the data byte that CPU2 receives, and writes in the unit of local storage 28 addressing.If for local storage is read, MRU12 obtains data from selected cell, carries out parity checking, then data is sent to the CPU2 or SPU4 or the system bus 16 that require data.

If direct access external memory 30, then MRU12 sends the address to system bus 16, and control and data message carry out write operation to external memory storage 30.In read operation, MRU12 delivers to address and control information on the address bus 16.In this case.Data message (channel number) is determined transmitting element, and therefore, in half bus cycles of back, response command will comprise the data of being asked and the address and the channel number of request unit.

Eight of MMU10, MRU12 supports, sixteen bit, 24 and 32 bit manipulations (1,2,3 and 4 byte).

NMRU14 controls all non-memory commands, comprises inner NPE3(part) non-memory command and system bus 16(outside) last all non-memory commands.Local non-memory command provides many registers for the programmer.Outside non-memory command provides many registers for program number in the controller that is connected to system bus 16.

Fig. 2 is the form of some typical non-memory commands.To output command that another subsystem that is connected to system bus 16 sends data the 8th to 17, comprised the channel number of receiving subsystem from a subsystem that is connected to system bus 16 at address bus 16-2, also comprise a function code in 18 to 23 of address bus 16-2, what comprise in 0 to 31 of data bus 16-4 is data.Control signal on control bus 16-6 is memory index signal BSMREF.Its explanation, this is not the order of storer 30.The half bus cycle signal BSSHBC in back illustrates that this is not in the previous order of response.Each subsystem will only respond unique channel number.Function code has illustrated the operation that receiving subsystem will carry out.

Also be noted that input command and its input response.Specified the channel number that sends subsystem for the 0th to 9 that notices data bus 16-4.In the input response command, this channel number appears on the 8th to 17 of address wire 16-2.Notice that it is response to previous input command that the BSSHBC signal indicates this.

Interruptive command is handled by principle of the present invention.This order comprises: the sexadecimal channel number OF of NPE3 and sexadecimal function code 03; Data bus 16-4 comprises the channel number of equipment in the subsystem that propose to interrupt or the subsystem and interrupt level number.

If the program current rank that its interrupt levels is just being carried out greater than CPU2, then NPE3 will handle current the interruption.

About Fig. 3, all orders on the NPE3 receiving system bus 16.Channel signal BSAD8-17 receives by address bus 16-2 and driver 66, and it is added on the logic 76.The channel number of NPE3 is provided with by switch (not drawing).Control signal BSSHBC and BSMREF also are added on the logic 76 by control bus 16-6 and driver 78.If 10 to 17 of signal BSAD indicate a sexadecimal channel number OF, then signal ITSAME step-down if signal BSAD8.BSAD9, BSMREF and BSSHBC are low, then produces signal CPINTF.Signal CPINTF is added to the input end of clock that interrupts coincidence register (IIR) 54, interrupts coincidence register (IIR) 54 0 to 15 by data bus 16-4 and driver 68 memory data signal BSDT, also 16 of memory address signal BSAD to 23.16 to 23 two low levels that comprise sexadecimal function code 03 and channel number of address signal BSAD.0 to 9 channel number that has indicated equipment in source subsystem or the subsystem of signal BSDT, 10 to 15 interrupt level that indicate the source subsystem of signal BSDT.

Logic 76 also produces signal MBINTR, just as the horizontal line on the signal name surperficial, it is low effectively.Signal MBINTR remains valid always, and up to bus recall signal ACKMBI step-down, signal MBINTR is added on the programmable logic array (PAL) 70.Here, with other more senior request competition to CPU2.Limit priority (7) is given signal PWFAIL, and this signal means urgent power down for hanging down.Inferior limit priority (6) is given signal ATMROV, and this signal is reduced to a predetermined value for low explanation counter timer.The limit priority of one-level (5) is given signal TICKED once more, and its explanation real-time clock has reached a predetermined value.The priority of lower one-level (3) is given signal DBINTR, and its explanation is inserted into the selectable unit of NPE3 and is asking to interrupt.

First degree priority (1) is distributed to signal MBINTR, and it is low that it produces signal IPL2, the low and IPLO height of IPL1.These signals are added on the CPU2.If CPU2 is not in the order of handling higher priority, then it does not answer this order, and 0 to 15 of 0 to 2 and the address signal CPLA of signal FCODE is added on the PAL72, and they all be that height then produces interruption recall signal CPINTA, make its step-down.In order to produce signal CPINTA, address gating signal AS also takes place in CPU2.

28 to 30 of signal CPINTA. MBINTR and CPPA is added on the PAL74, forced signal ACKMBI step-down, thus forced signal MBINTR is high.

Now, interruptive command visit CPU2.Signal CPINTA is added on the logic 64, and the output that produces IIR register 54 allows signal ENINTR.The channel number and the signal CPDT16-25 that are stored in the IIR register 54 pass through data bus 8 and Port Multiplier (MUX) 50, are added to the address input end of the random access memory 52 of depositing interrupt vector.RAM52 is made of two 1024 * 4 random access memory, and it store vectorial.These vectorial functions will illustrate with Fig. 4.The low signal CPINTA that is added on the MUX50 selects data bus signal CPDT16-25 during the read operation of RAM52, high signal CPINTA is at the signal CPLA8-17 that selects during the write operation of RAM52 on the address bus 6.

RAM52 is allowed by signal ENVECR step-down.In the address when earlier logical, signal ENVECR or produced by RAM write signal LDVECR is perhaps produced by RAM read signal RDVECR, and perhaps by signal CPINTA and actual address signal CPPA28, CPPA29 and CPPA30 produce.

Signal LDCECR or RDVECR during non-interrupt operation by shown in Boolean equation produce.

Signal LDVECR is produced by PAL56, and signal RDVECR is produced by PAL58, notices that data strobe signal DS is controlling writing regularly of RAM52.

In cycle (FCODEO, FCODE1 and FCODE2 equal scale-of-eight 5), PAL58 also produces the RDINTR signal of visit RAM52, (FCODEO, FCODE1 and FCODE2 equal scale-of-eight 7) handling interrupt in cpu cycle at manager data.

Following Boolean expression has been described PAL56, and 58,62,70,72 and 74 and the logic function of logic 64 and 76.

Interrupt to the CPU2 request by system bus 16.

CPINTF＝ BSADB· BSAD9· ITSAME· BSMREF· BSSHBC

MBINTR＝CPINTF·ACKMBI

ACKMBI＝CPINTA·CPPA·28;CPPA·29;CCPA·30， MBINTR

CPINTA＝FCODE2.FCODE1.FCODE0.CPLA12.

CPLA13.CPLA14.CPLA15

CPINTA＝ CPINTA. AS

IPL2＝ PWPAIL+ ATMROV+ TICKED

IPL1＝ PWPAIL+ ATMROV+（TICKED.DBINTR）

IPL0＝ PWFAIL+AT.TROV.（ TIOKED+ DBINTR+MBINTR）

HHH-does not have the LLL-of interruption limit priority

ITSAME=channel number comparer

BSAD10. BSAD11. BSAD12. BSAD13.

BSAD14.BSAD15.BSAD16.BSAD17

Channel number (sexadecimal OF)

Interrupt vector table 52

(permission) ENVECR=AS (LDVECR+ RDVECR+ (CPINTA. CPPA28. CPPA29.

CCPA30））

(writing)

LDVECR＝ AS.R/

.FCODE2. FCODE1.FCODE0. DS.CPLA0.CPLA1.CPLA2.CPLA3.CPLA4.CPLA5. CPLA6.CPLA7

(reading)

RDVECR＝ AS.R/ W.FCODE2. FCIDE1.FCODE0.CPLA0.CPLA1.CPLA2.CPLA3. CPLA4.CPLA5.CPLA6. CPLA7

Interrupt coincidence register 54

(writing) CPINTF

(output allows) ENINTR=CPINTA+ RDINTR

RDINTR= AS.CPRDWR.FCODE2.FCO DE1.

FCODE0.CPLA0.CPLA1.CPLA2.

CPLA3.CPLA4.CPLA5.CPLA6.CPLA7

Fig. 4 is an example of interrupt diagnostic of the present invention.Taking orders in 80, the channel number and the interrupt permission signal that receive order, function code, interrupting device from system bus 16 are stored in the IIR register 54, and look-at-me MBINTR also will ask privilege of access scrambler 70.If priority encoder 70 does not have higher override requests, then be the IPL0-2 request visit CPU2 of scale-of-eight 1.If CPU2 is not in the order of carrying out higher priority, then CPU2 allows 54 outputs of IIR register.

The channel number of supposing interrupting device is sexadecimal EO(11100000), addressing EO unit then.Suppose that what deposit in the unit of sexadecimal EO indication is sexadecimal number 72, then is added to this value on the drift computer 82.The vector basis address, sexadecimal, 1000 also are added on the drift computer 82.The vector basis address is the first address of exception vector table 84 in storer 28 or 30, and drift computer 80 is added to side-play amount on the sexadecimal base address 1000.Side-play amount is four times (1000H+4(72H) of memory address content among the RAM52).Result of calculation is sexadecimal 11C8.This is the address of interrupt routine 86 pointers in storer 28 or 30.For example, the content among the hexadecimal address 11C8 is a sexadecimal 4000.Thereby CPU will forward sexadecimal 4000 addresses places to, begin to carry out interrupt routine.

We are described in detail the present invention with reference to preferred embodiment.Those of ordinary skill in the art can understand, can change in form and on the details, but all not leave central idea of the present invention and scope.

Claims (3)

1, a processor that is used to cause data handling system is inserted device among the execution with an interruption subroutine, this data handling system has second subsystem (36) of one first subsystem (3) and a plurality of connected and described first subsystem communication, wherein each described second subsystem is when on behalf of it, described first subsystem of request carry out a subroutine, send an interruptive command to described first subsystem, described order comprises the identiflication number of this second subsystem; Wherein said first subsystem gives interruption by described command request according to the priority relative value that is consistent with described interruptive command, is being carried out the priority of this processing by the processor of described first subsystem; Be used to cause that the device that described data processor is inserted corresponding interruption subroutine among the execution is characterised in that,

First addressable memory (52) has appropriate address (vector) in its each addressable unit, this address is unique for each the different identiflication number in described second subsystem;

Second addressable memory (84) has the address (pointer) in the system storage (28,30) of interruption subroutine in its addressable unit, this address is unique for the different identiflication numbers of described second subsystem;

Logical circuit (72,50), the identiflication number that is used for being given the interruptive command of interruption is added to described first memory, as its address;

Counter (82), the base address that is used for the relative address of will read from described first addressable memory and a unit in the described storer is combined, to produce an address of described second memory;

Be used for the address that described counter produces is added to the circuit of described second memory;

Thereby will be used to visit this system storage from the address (pointer) that described second addressable memory is read, so that obtain corresponding interruption subroutine and it is inserted among the execution.

2, according to the device of claim 1, its feature also is:

Register (54) is used to receive and keep in the described interruptive command that is sent by described second subsystem, and this register and described logical circuit (72,50) are connected, and to its command recognition numbering that provides described register memory to have.

3, according to the device of claim 2, its feature further is:

The central processing unit (CPU2) that is connected with described system storage is in order to receive wherein accessed interruption subroutine and it is inserted among the execution.