JPH0256456U - - Google Patents
Info
- Publication number
- JPH0256456U JPH0256456U JP13450588U JP13450588U JPH0256456U JP H0256456 U JPH0256456 U JP H0256456U JP 13450588 U JP13450588 U JP 13450588U JP 13450588 U JP13450588 U JP 13450588U JP H0256456 U JPH0256456 U JP H0256456U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- die island
- wire
- die
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000008188 pellet Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の半導体装置の平面
説明図、第２図は従来の半導体装置の平面説面図
である。 Ｂ……半導体装置、７……ダイアイランド、７
１……アースワイヤボンデイング用パターン、７
２……リード端子、８……リードフレーム、８１
，８２……インナリード、８１ａ，８２ａ……先
端部、９……ペレツト、９１，９２……ワイヤボ
ンデイングパツト、９３……アースワイヤボンデ
イングパツト、１１，１１′，１２……金細線、
１３……パツケージ。
説明図、第２図は従来の半導体装置の平面説面図
である。 Ｂ……半導体装置、７……ダイアイランド、７
１……アースワイヤボンデイング用パターン、７
２……リード端子、８……リードフレーム、８１
，８２……インナリード、８１ａ，８２ａ……先
端部、９……ペレツト、９１，９２……ワイヤボ
ンデイングパツト、９３……アースワイヤボンデ
イングパツト、１１，１１′，１２……金細線、
１３……パツケージ。
Claims (1)
- 【実用新案登録請求の範囲】 ダイアイランドに搭載固着したペレツトのアー
スボンデイングパツトのアースをワ嫡ヤを介して
上記ダイアイランドから取るようにした半導体装
置において、 上記ダイアイランドに上記ワイヤをボンデイン
グするためのパターン部を１個又は複数個延出形
成したことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13450588U JPH0256456U (ja) | 1988-10-17 | 1988-10-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13450588U JPH0256456U (ja) | 1988-10-17 | 1988-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0256456U true JPH0256456U (ja) | 1990-04-24 |
Family
ID=31393322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13450588U Pending JPH0256456U (ja) | 1988-10-17 | 1988-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0256456U (ja) |
-
1988
- 1988-10-17 JP JP13450588U patent/JPH0256456U/ja active Pending