JPH0255812B2 - - Google Patents
Info
- Publication number
- JPH0255812B2 JPH0255812B2 JP60088977A JP8897785A JPH0255812B2 JP H0255812 B2 JPH0255812 B2 JP H0255812B2 JP 60088977 A JP60088977 A JP 60088977A JP 8897785 A JP8897785 A JP 8897785A JP H0255812 B2 JPH0255812 B2 JP H0255812B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- block
- memory
- address
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60088977A JPS61248145A (ja) | 1985-04-26 | 1985-04-26 | メモリ制御装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60088977A JPS61248145A (ja) | 1985-04-26 | 1985-04-26 | メモリ制御装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61248145A JPS61248145A (ja) | 1986-11-05 |
| JPH0255812B2 true JPH0255812B2 (cs) | 1990-11-28 |
Family
ID=13957854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60088977A Granted JPS61248145A (ja) | 1985-04-26 | 1985-04-26 | メモリ制御装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61248145A (cs) |
-
1985
- 1985-04-26 JP JP60088977A patent/JPS61248145A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61248145A (ja) | 1986-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5537572A (en) | Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM) | |
| EP0112442B1 (en) | Data storage hierarchy and its use for data storage space management | |
| CA1124888A (en) | Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability | |
| KR100339904B1 (ko) | 캐시 프로세스용 시스템 및 방법 | |
| CA1180465A (en) | Method and apparatus for limiting data occupancy in a cache | |
| JPH06348595A (ja) | キャッシュ装置 | |
| JPH0340046A (ja) | キャッシュメモリ制御方式および情報処理装置 | |
| JPS6111865A (ja) | メモリアクセス制御方式 | |
| JPH04205041A (ja) | マルチプロセッサシステム | |
| JP2000512050A (ja) | マイクロプロセッサキャッシュの一貫性 | |
| JPH0115903B2 (cs) | ||
| JPH044617B2 (cs) | ||
| JPH0255812B2 (cs) | ||
| JPH0156411B2 (cs) | ||
| JPS5918786B2 (ja) | 階層構成メモリ・システム | |
| JPH0529943B2 (cs) | ||
| JPH0354649A (ja) | バッファ記憶制御方式 | |
| JPH0210446A (ja) | バッファ記憶装置 | |
| JPH10133948A (ja) | キャッシュメモリ装置 | |
| EP0400851A2 (en) | Efficient cache utilizing a store buffer | |
| JPH08147216A (ja) | データ処理装置 | |
| JPH02188849A (ja) | キャッシュメモリ方式 | |
| JPH07152650A (ja) | キャッシュ制御装置 | |
| JPH0689228A (ja) | キャッシュメモリ制御装置 | |
| JPS61235960A (ja) | キヤツシユメモリの制御方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |