JPH0252298B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an input/output control device, and particularly to a buffer memory control method.

[Prior art]

An input/output control device generally includes a buffer memory therein, but the capacity of the buffer memory must correspond to the length of one recording unit of the device to be controlled. Therefore, the capacity of the buffer memory is the maximum length of one recording unit among the devices to be controlled, but if the capacity is less than that, a plurality of buffer memories will be required. However, if the length is adjusted to the maximum length of one recording unit, there will be some unused parts when controlling a device with a unit length smaller than that, which is generally wasteful and also causes a large loss of time. Furthermore, when using a plurality of devices, in the conventional method, it is necessary to switch them at high speed within the transfer time, which is not only an economic burden due to switching circuits, but also technically complicated.

[Purpose of the invention]

The present invention has been proposed in view of the problems of the conventional example described above, and is an input device equipped with a plurality of buffer memories that can be operated independently or in conjunction depending on the size of one recording unit length of a control device. The purpose is to provide an output control device.

[Structure of the invention]

The present invention includes a first buffer memory, a first buffer memory address register indicating a storage address of the first buffer memory, a first buffer memory control register holding control information for controlling the first buffer memory, and a first buffer memory address register indicating a storage address of the first buffer memory. a second buffer memory, a second buffer memory address register indicating a storage address of the second buffer memory, and a second buffer memory;
a second buffer memory control register that holds control information for controlling the buffer memory of the first buffer memory;
According to the conditions of the buffer memory address register, the information in the first buffer memory control register is transferred to the second buffer memory control register, and specific information is written in the first buffer memory control register. The buffer memory and the second buffer memory are characterized in that they can be operated in conjunction with each other or can be operated independently.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a system including an input/output control device according to an embodiment of the present invention. The channel device 1 connects the input/output control device 4,
6. The input/output control device 4 is a magnetic tape control device, and controls a magnetic tape unit 5 (hereinafter abbreviated as MTU) via a bus line 11. Further, the input/output control device 6 is a line printer control device and controls the line printer 7. The central processing unit 2 retrieves instructions stored in the main memory 3, decodes them, and executes them. That is, if the command is an input/output command, the channel device 1 is activated, and the activated channel device 1 retrieves the command from the main storage device 3 and sends it to a specific input/output control device. Thereafter, the channel device 1 starts data transfer with the input/output control device.

The input/output control device 4 will be explained below as an example. FIG. 2 is a block diagram of the data path relationship of the input/output control device 4. The microprocessor 40 is connected to a read only memory 42, a read/write memory 41, buffer memory address registers 21, 31, and buffer memory control registers 22, 32 via a CPU bus 50. The microprocessor 40 has a buffer memory address register 2.
1, 31 and buffer memory control register 2
It is possible to read and write to 2 and 32. The first buffer memory 20 includes a buffer memory address register 21, a buffer memory control register 22, a write data selector 44, and a read data buffer register 23.
is connected to. Second buffer memory 30
is connected to a buffer memory address register 31, a buffer memory control register 32, a write data selector 44, and a read data buffer register 33. The read data selector 43 is connected to the read data buffer registers 23 and 33.
is input, and the data is sent via the bus line 11.
It is sent to the MTU 5 and to the channel device 1 via the bus line 10. Write data selector 44 selects bus line 10 or bus line 11 and sends the data on the bus to buffer memories 20 and 30. FIG. 3 is a more detailed block diagram of the input/output control device of FIG. 2. First, the first buffer memory 20
Explain. A flip-flop 300 holding a buffer memory read request from the channel is connected to AND circuits 104 and 204 via a signal line 304. The buffer memory write request holding flip-flop 301 from the channel is connected to the signal line 305.
Write data selector 44, AND circuit 1 via
It is connected to 05,205. Flip-flop 3 holding buffer memory read request from MTU
02 is connected to the AND circuit 106 through the signal line 306,
206. Buffer memory write request holding flip-flop 303 from MTU
is connected to the write data selector 4 via the signal line 307.
4. Connected to AND circuits 107 and 207. The selector 109 selects either data from the CPU bus 50 or fixed data, and sets the data in the buffer memory control register 22. The control register 22 consists of flip-flops (hereinafter abbreviated as FF) 320, 111, 112, 113, and 114. FF320 has buffer memory 20,30
It outputs the connection control signal of signal line 3.
09 to the AND circuit 321. FF1
Reference numeral 11 outputs a read control signal for the channel device 1, which is connected to the AND circuit 1 via a signal line 152.
04, connected to selector 209. FF112
outputs the write control signal of the channel device, and is connected to the AND circuit 105, via the signal line 153.
Connected to selector 209. FF113 is MTU
It outputs a read control signal from 5,
It is connected to the AND circuit 106 and the selector 209 via a signal line 154. FF114 outputs the write control signal from MTU5, and is connected to signal line 1.
It is connected to the AND circuit 107 and the selector 209 via 55. AND circuit 104 is connected to OR circuit 102 via signal line 156. AND circuit 10
5 is connected to the OR circuit 103 via a signal line 158. AND circuit 106 is connected to OR via signal line 157.
Connected to circuit 102. AND circuit 107 is connected to OR circuit 103 via signal line 159.
The OR circuit 102 is connected to the buffer memory control circuit 100, the AND circuit 101, and the read data selector 43 via a signal line 160. OR circuit 10
3 is connected to the buffer memory control circuit 100 via a signal line 161. The buffer memory address register 21 is an increment register indicating the address of data stored in the buffer memory 20, and data can be set by the CPU bus 50. Further, address information is sent to the buffer memory control circuit 100 through a signal line 150. Also, when a carry occurs as a result of stepping, a signal is sent via the signal line 310.
A signal is sent to the AND circuit 321. A buffer memory control circuit 100 controls the buffer memory 20. Address information is sent via the signal line 151,
It also sends a write instruction signal to the buffer memory 20 via the signal line 162. Further, during a read operation, a latch timing signal for read data is sent to the AND circuit 101 via the signal line 163. Furthermore, although not shown in FIG.
Various control signals such as reset signals 0, 301, 302, and 303 are also generated and distributed as necessary. The buffer memory 20 starts from the channel device 1.
This is a temporary data storage unit when transferring data to the MTU 5 or transferring data from the MTU 5 to the channel device 1. Data read from the buffer memory 20 is held in the read data buffer register 23 via the signal line 164.
AND circuit 101 is connected to read data buffer register 23 via signal line 165. Signal line 165 is for latching the data on signal line 164 into buffer register 23. Read data buffer register 23 is connected to read data selector 43 via signal line 166. The read data selector 43 is connected to the signal line 160 or the signal line
260, the data on signal line 166 is transferred to signal line 2.
66. Select the data above. The selected data is sent to the channel device 1 via the bus line 10 or to the MTU 5 via the bus line 11. The write data selector 44 selects data on the bus line 10 or data on the bus line 11 using the signal line 305 and the signal line 307. The selected data is transferred to the buffer memories 20, 30 via a signal line 311.
sent to. AND circuit 321 is connected to buffer memory control registers 22, 32 and selectors 109, 209 via signal line 308. When the AND circuit 321 is established, the data in the buffer memory control register 22 is set in the buffer memory control register 32, and then fixed data (zero in the embodiment) is set in the buffer memory control register 22.

The configuration of the second buffer memory is FF320 and
They are the same except for the AND circuit 321, and the same explanation can be made by replacing 2× with 3× or 1×× with 2×× in the description of the first buffer memory.

Next, the operation when writing from the channel device 1 to the MTU 5 of the input/output control device according to this embodiment will be explained. In the case of a general data length, the input/output control device 4 receives a command for writing a general data length. Then, the microprocessor 40 shown in FIG. 2 sets the FF112 in FIG. 3 via the CPU bus 50, and sets the FF320,
111, 113, 114, 211-214 are reset. The buffer memory address registers 21 and 31 are also reset. After that, when the buffer memory write request FF301 from the channel is set, the data on the bus line 10 is selected by the signal line 305, the AND circuit 105 is established, and the buffer memory control circuit 100 is activated. The buffer memory control circuit 100 connects the signal line 311 according to the address indicated in the buffer memory address register 21.
The above data is stored in the buffer memory 20.
Thereafter, the buffer memory address register 21 is incremented. In this way, data of one recording length is entered into the buffer memory 20. Then processor 40 is FF
Set 113 and FF212, FF320, 11
1, 112, 114, 211, 213, 214. Also, at the same time as resetting buffer memory address registers 21 and 31, MTU5
Activate. Even if the buffer memory write request FF301 from the channel is set, no data is stored in the buffer memory 20 this time, but data from the channel is stored in the buffer memory 30 in the same manner as described above. Further, when the read request FF 302 from the MTU 5 is set, the AND circuit 106 is established, and therefore the OR circuit 102 is established and the buffer memory control circuit 100 is activated. The buffer memory control circuit 100 reads data from the buffer memory 20 according to the address indicated by the buffer memory address register 21. Then, a signal is sent to the signal line 163 within the readout time.
Establish the AND circuit 101 and buffer memory 2
Read data from 0 is set in the read data buffer register 23. Thereafter, the buffer memory address register 21 is incremented. selector 4
3 sends the data on the signal line 166 via the bus line 11 to the MTU 5 through the signal line 160 and records it on the tape. The operation of storing data in the buffer memory 30 and the operation of reading data from the buffer memory 20 are performed in parallel, so that data transfer is processed at high speed. When the buffer memory 20 becomes empty and data of one record length is stored in the buffer memory 30, the data is read from the buffer memory 30 and sent to the MTU 5, and the data from the channel device is stored in the buffer memory 20.

In the case of writing with the maximum recording length, the input/output control device 5 receives a command indicating that the writing is with the maximum recording length. The microprocessor 40 sets FF320 and FF112 in FIG.
~214 is reset. The buffer memory address registers 21 and 31 are also reset. After that, buffer memory write request FF from the channel
When 301 is set, data from the channel device is stored in the buffer memory 20 in the same way as a general data length write operation. However, before one recording length is completely stored in the buffer memory 20, a carry occurs from the buffer memory register 21. When this carry occurs, the AND circuit 321
is established, and the information in the buffer memory control register 22 is set in the buffer memory control register 32 via the signal line 308. Thereafter, fixed data zero is set in the buffer memory control register 22. That is, the control register 22 is cleared.
After that, a buffer memory write request is made from the channel.
When FF301 is set, buffer memory 2
Data consecutive to 0 is stored in the buffer memory 30. FF when data storage for one record length is completed.
Set 320 and FF113, FF111, 11
2,114,211-214 are reset. The buffer memory address registers 21 and 31 are reset and the MTU 5 is activated. When read request FF302 from MTU5 is set, data is read from buffer memory 20, and MTU5
sent to. Buffer memory address register 2
When a carry is output from 1, the AND circuit 321 is established, the data in the buffer memory control register 22 is set in the buffer memory control register 32, and the buffer memory control register 22 is cleared. After that, the data in the buffer memory 30 will be
Sent to MTU5.

Although the operation for writing from the channel device 1 to the MTU 5 has been described above, it is obvious that the operation for reading data from the MTU 5 and transferring data to the channel device 1 can be performed in the same manner. Also the first
Although the carry from the buffer memory address register 21 is used when transferring from the buffer memory 20 to the second buffer memory 30, it is obvious that it can be realized under other conditions. It is also obvious that after the data in the buffer memory control register 22 is set in the buffer memory control register 32, a specific pattern, such as a transition flag bit, can be set in the buffer memory control register 22. Also, in the embodiment, the case of two buffer memories was explained, but if the maximum recording length is three or four times the general recording length, two or three buffer memories equivalent to the first buffer memory may be provided and connected in cascade. It is also obvious that this can be realized by making connections and finally connecting something equivalent to the second buffer memory.

As explained above, the present invention connects the first buffer memory and the second buffer memory only when the maximum recording length is rarely used, and connects the first buffer memory and the second buffer memory when the recording length is frequently used. Since each can operate independently, there is no need to have a large buffer memory with a maximum recording length, which is economical. In addition, technically complex control to quickly switch between two low-capacity buffer memories within a transfer unit time is no longer required.
Furthermore, there is no need for a circuit for switching buffer memories, which has the effect of making it possible to design an input/output control device easily and economically.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a system including an input/output control device according to an embodiment of the present invention, FIG. 2 is a block diagram of data path relationships of the input/output control device according to an embodiment of the present invention, and FIG. 3 1 is a detailed block diagram of an input/output control device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Channel device, 2... Central processing unit, 3... Main storage device, 4, 6... Input/output control device, 5... Magnetic tape device, 7... Line printer, 20, 30... Buffer memory, 21, 31... Buffer memory Address register, 22, 32... Buffer memory control register, 23, 24... Buffer register, 4
3,109,209...Selector, 44...Write data selector, 111-114, 211-21
4,300-303...Flip-flop.

Claims (1)

[Claims] 1. A first buffer memory, a first buffer memory address register indicating a storage address of the first buffer memory, and a first buffer memory control register holding control information for controlling the first buffer memory. , a second buffer memory, and a second buffer memory.
a second buffer memory address register that indicates a storage address of the buffer memory; and a second buffer memory control register that holds control information for controlling the second buffer memory; According to the conditions of the first buffer memory address register, the information of the first buffer memory control register is transferred to the second buffer memory control register, and specific information is written to the first buffer memory control register. An input/output control device in which the buffer memory and the second buffer memory can be operated in conjunction with each other or can be operated independently.