JPH0251753A - Rom address designating circuit - Google Patents

Abstract

PURPOSE:To extend the ROM areas in number larger than the address signal lines by designating plural ROM blocks of the same size based on the address designating data given together with a specific higher rank address signal. CONSTITUTION:A microprocessor can directly read and write a basic ROM 10 and a basic RAM 11. While the extension ROM 4-7 can read the ROM 10 and the RAM 11 via a ROM address designating circuit. Either one of ROM 4-7 can be read by enabling one of these ROM 4-7 when data (0, 1, 2 and 3 with ROM 4, 5, 6 and 7 respectively) are set at a register circuit 1. In other words, the microprocessor can designate the ROM 10, extension ROM groups 4-7 and the RAM 11 with use of address signals A14 and A15.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to ROM addressing circuits.

[Conventional technology]

Conventional ROM addressing circuits select a ROM address by decoding only the address signal conveyed by the address signal line.

[Problem that the invention seeks to solve]

According to the conventional circuit described above, the memory access area is
This ROM is limited by the number of address signal lines.
It was not possible to store a program larger than the area in the ROM.

[Means for solving problems]

The circuit of the present invention includes a register circuit that latches address designating data given when a specific upper address signal designating a memory block is generated, and a decoder circuit that decodes the contents of this register circuit. The present invention is characterized in that a plurality of ROM blocks of the same size can be specified by an upper address signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In FIG. 1, 1 is a 2-bit extended address signal A16 . Register circuit for latching A17, 2 is extended address signal A1
6. A decoder circuit which inputs A17 and outputs the base signal of the enable signals ROMC3O to ROMC33 of the four expansion ROMs 4 to 7. 3 is a decoder circuit that takes the logical product of the output of the AND circuit 8 and the output of the decoder circuit 2 and enables the expansion ROMs 4 to 7. AND circuit 4 outputs signals ROMC50-3, inputs enable signal ROMC50, read signal MRD, and address signal AO-A13 and outputs addresses 4000o-7
Extended R allocated to 16 byte area of FFFH
OM, 5 is enable signal ROMC5I and read signal M
Input RD and address signal AO-A13 to 5 address 4
000H to 7FFF, 16 is an expansion ROM allocated to a byte area, and 6 is an address 4000o to 7FPF into which enable signal ROMC32, read signal MRD, and address signal AO-A13 are input.

Expansion ROM allocated to an area of 16 bytes, 7
inputs enable signal ROMC33, read signal MRD, and address signal AO-A13, and reads address 4000o~
7FFF)l, 16 is an expansion ROM allocated to a byte area, 8 is an AND circuit that inputs the address signal A14.15 and outputs a signal that becomes the input of the AND circuit 3, and 9 inputs the address signal A14.15. An AND circuit that outputs the enable signal of the basic ROM 10, 10 inputs the enable signal of the output of the AND circuit 9, the read signal MRD, and the address signal AO-A13, and inputs the address 0000H to 3F.
Basic RO allocated to 16 byte area of FFH
M, 11 is the enable signal A15. Read signal MRD,
Light signal MWR.

Input address signal AO-A14 and address 80008
R allocated to 32 byte area of ~FFFFH
It is AM.

Next, the operation of this circuit will be explained.

Basic ROM10 and RAMII can be directly read/written from a microprocessor (not shown), but expansion ROMs 4 to 7 can be read by this circuit.Any one of expansion ROMs 4 to 7 can be read. In this case, the expansion R
One of OM4-7 is enabled and can be read.

That is, from the microprocessor, the basic ROM10.
Expansion ROM groups 4-7. Any one of RAM II can also be designated by address signals A14 and A15. When the address signal A14 is true and A15 is false, the microprocessor can specify one of the expansion ROMs 4 to 7 by supplying the above-mentioned data to the register circuit 1. FIG. 2 shows a map of memory allocated in this manner.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which multiple ROM blocks of the same size can be specified for the same upper address signal by addressing data given together with a specific upper address signal. Therefore, the ROM is
It has the effect of expanding the area.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing memory allocation in this circuit. 1...Register circuit, 2...Decoder circuit, 3, 8
゜9...AND circuit, 4,5,6.7...Extended RO
M, 10--Basic ROM, 11-RAM.

Claims (1)

[Claims] A register circuit that latches addressing data given when a specific upper address signal designating a memory block is generated, and a decoder circuit that decodes the contents of the register circuit are provided. A ROM addressing circuit is characterized in that it is capable of specifying multiple ROM blocks of the same size.